largely reimplement pci_conf_print():
* print all configuration space registers. Then, where possible, interpret them. (That is, PRESENT ALL THE DATA, then interpret it -- don't hide data behind interpretation. Also, when interpreting fields, try to print out the specific value that's being interpreted.) * handle different header types. * allow caller to specify a function which can interpret the device-dependent header and is responsible for pretty-printing it. It spews (use 'options MSGBUFSIZE=...' 8-), but when you want the data, you really want _all_ of it. Still needs some cleanup and additional code (e.g. interepretation of PCI-PCI (type 1) and PCI-Cardbus (type 2(?)) bridge headers).
This commit is contained in:
cgd
parent
27b21a3a47
commit
4b0876c74b
@ -1,8 +1,9 @@
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/* $NetBSD: pci_subr.c,v 1.25 1998/05/03 19:46:15 thorpej Exp $ */
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/* $NetBSD: pci_subr.c,v 1.26 1998/05/18 17:25:17 cgd Exp $ */
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/*
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* Copyright (c) 1997 Zubin D. Dittia. All rights reserved.
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* Copyright (c) 1995, 1996 Christopher G. Demetriou. All rights reserved.
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* Copyright (c) 1995, 1996, 1998
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* Christopher G. Demetriou. All rights reserved.
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* Copyright (c) 1994 Charles Hannum. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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@ -49,6 +50,11 @@
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#include <dev/pci/pcidevs.h>
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#endif
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static void pci_conf_print_common __P((pci_chipset_tag_t, pcitag_t,
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const pcireg_t *regs));
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static void pci_conf_print_type1 __P((pci_chipset_tag_t, pcitag_t,
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const pcireg_t *regs));
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/*
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* Descriptions of known PCI classes and subclasses.
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*
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@ -317,26 +323,26 @@ pci_devinfo(id_reg, class_reg, showclass, cp)
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* pci_conf_print(pa->pa_pc, pa->pa_tag);
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* #endif
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*/
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void
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pci_conf_print(pc, tag)
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#define i2o(i) ((i) * 4)
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#define o2i(o) ((o) / 4)
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static void
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pci_conf_print_common(pc, tag, regs)
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pci_chipset_tag_t pc;
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pcitag_t tag;
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const pcireg_t *regs;
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{
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pcireg_t rval, mask;
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int reg, s;
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#ifdef PCIVERBOSE
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struct pci_knowndev *kdp;
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static const char on_str[] = "ON", off_str[] = "OFF";
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#endif
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struct pci_class *classp, *subclassp;
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pcireg_t rval;
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printf("PCI configuration registers:\n");
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rval = pci_conf_read(pc, tag, PCI_ID_REG);
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rval = regs[o2i(PCI_ID_REG)];
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#ifndef PCIVERBOSE
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printf(" Vendor ID: 0x%04x\n", PCI_VENDOR(rval));
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printf(" Device ID: 0x%04x\n", PCI_PRODUCT(rval));
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printf(" Vendor ID: 0x%04x\n", PCI_VENDOR(rval));
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printf(" Device ID: 0x%04x\n", PCI_PRODUCT(rval));
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#else
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for (kdp = pci_knowndevs; kdp->vendorname != NULL; kdp++) {
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if (kdp->vendor == PCI_VENDOR(rval) &&
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@ -346,48 +352,41 @@ pci_conf_print(pc, tag)
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}
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}
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if (kdp->vendorname != NULL)
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printf(" Vendor Name: %s\n", kdp->vendorname);
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printf(" Vendor Name: %s (0x%04x)\n", kdp->vendorname,
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PCI_VENDOR(rval));
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else
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printf(" Vendor ID: 0x%04x\n", PCI_VENDOR(rval));
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printf(" Vendor ID: 0x%04x\n", PCI_VENDOR(rval));
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if (kdp->productname != NULL && (kdp->flags & PCI_KNOWNDEV_NOPROD) == 0)
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printf(" Device Name: %s\n", kdp->productname);
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printf(" Device Name: %s (0x%04x)\n", kdp->productname,
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PCI_PRODUCT(rval));
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else
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printf(" Device ID: 0x%04x\n", PCI_PRODUCT(rval));
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printf(" Device ID: 0x%04x\n", PCI_PRODUCT(rval));
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#endif /* PCIVERBOSE */
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rval = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
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#define onoff(str, bit) \
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printf(" %s: %s\n", (str), (rval & (bit)) ? "on" : "off");
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#ifndef PCIVERBOSE
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printf(" Command/Status Register: 0x%08x\n", rval);
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#else
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rval = regs[o2i(PCI_COMMAND_STATUS_REG)];
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#define onoff(reg) ((rval & (reg)) ? on_str : off_str)
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printf(" Command Register:\n");
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printf(" I/O space accesses %s\n", onoff(PCI_COMMAND_IO_ENABLE));
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printf(" Mem space accesses %s\n", onoff(PCI_COMMAND_MEM_ENABLE));
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printf(" Bus mastering %s\n", onoff(PCI_COMMAND_MASTER_ENABLE));
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printf(" Special cycles %s\n", onoff(PCI_COMMAND_SPECIAL_ENABLE));
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printf(" MWI transactions %s\n",
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onoff(PCI_COMMAND_INVALIDATE_ENABLE));
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printf(" Palette snooping %s\n", onoff(PCI_COMMAND_PALETTE_ENABLE));
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printf(" Parity error checking %s\n",
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onoff(PCI_COMMAND_PARITY_ENABLE));
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printf(" Address/Data stepping %s\n",
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onoff(PCI_COMMAND_STEPPING_ENABLE));
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printf(" System Error (SERR) %s\n", onoff(PCI_COMMAND_SERR_ENABLE));
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printf(" Fast back-to-back transactions %s\n",
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onoff(PCI_COMMAND_BACKTOBACK_ENABLE));
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printf(" Status Register:\n");
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printf(" 66 MHz capable %s\n", onoff(PCI_STATUS_66MHZ_SUPPORT));
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printf(" User Definable Features (UDF) support %s\n",
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onoff(PCI_STATUS_UDF_SUPPORT));
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printf(" Fast back-to-back capable %s\n",
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onoff(PCI_STATUS_BACKTOBACK_SUPPORT));
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printf(" Data parity error detected %s\n",
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onoff(PCI_STATUS_PARITY_ERROR));
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printf(" Command register: 0x%04x\n", rval & 0xffff);
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onoff("I/O space accesses", PCI_COMMAND_IO_ENABLE);
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onoff("Memory space accesses", PCI_COMMAND_MEM_ENABLE);
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onoff("Bus mastering", PCI_COMMAND_MASTER_ENABLE);
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onoff("Special cycles", PCI_COMMAND_SPECIAL_ENABLE);
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onoff("MWI transactions", PCI_COMMAND_INVALIDATE_ENABLE);
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onoff("Palette snooping", PCI_COMMAND_PALETTE_ENABLE);
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onoff("Parity error checking", PCI_COMMAND_PARITY_ENABLE);
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onoff("Address/data stepping", PCI_COMMAND_STEPPING_ENABLE);
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onoff("System error (SERR)", PCI_COMMAND_SERR_ENABLE);
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onoff("Fast back-to-back transactions", PCI_COMMAND_BACKTOBACK_ENABLE);
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printf(" DEVSEL timing ");
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printf(" Status register: 0x%04x\n", (rval >> 16) & 0xffff);
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onoff("66 MHz capable", PCI_STATUS_66MHZ_SUPPORT);
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onoff("User Definable Features (UDF) support", PCI_STATUS_UDF_SUPPORT);
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onoff("Fast back-to-back capable", PCI_STATUS_BACKTOBACK_SUPPORT);
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onoff("Data parity error detected", PCI_STATUS_PARITY_ERROR);
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printf(" DEVSEL timing: ");
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switch (rval & PCI_STATUS_DEVSEL_MASK) {
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case PCI_STATUS_DEVSEL_FAST:
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printf("fast");
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@ -398,23 +397,21 @@ pci_conf_print(pc, tag)
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case PCI_STATUS_DEVSEL_SLOW:
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printf("slow");
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break;
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default:
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printf("unknown/reserved"); /* XXX */
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break;
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}
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printf("\n");
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printf(" (0x%x)\n", (rval & PCI_STATUS_DEVSEL_MASK) >> 25);
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printf(" Slave signaled Target Abort %s\n",
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onoff(PCI_STATUS_TARGET_TARGET_ABORT));
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printf(" Master received Target Abort %s\n",
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onoff(PCI_STATUS_MASTER_TARGET_ABORT));
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printf(" Master received Master Abort %s\n",
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onoff(PCI_STATUS_MASTER_ABORT));
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printf(" Asserted System Error (SERR) %s\n",
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onoff(PCI_STATUS_SPECIAL_ERROR));
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printf(" Parity error detected %s\n",
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onoff(PCI_STATUS_PARITY_DETECT));
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#endif /* PCIVERBOSE */
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onoff("Slave signaled Target Abort", PCI_STATUS_TARGET_TARGET_ABORT);
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onoff("Master received Target Abort", PCI_STATUS_MASTER_TARGET_ABORT);
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onoff("Master received Master Abort", PCI_STATUS_MASTER_ABORT);
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onoff("Asserted System Error (SERR)", PCI_STATUS_SPECIAL_ERROR);
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onoff("Parity error detected", PCI_STATUS_PARITY_DETECT);
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rval = pci_conf_read(pc, tag, PCI_CLASS_REG);
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#undef onoff
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rval = regs[o2i(PCI_CLASS_REG)];
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for (classp = pci_class; classp->name != NULL; classp++) {
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if (PCI_CLASS(rval) == classp->val)
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break;
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@ -426,26 +423,39 @@ pci_conf_print(pc, tag)
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subclassp++;
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}
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if (classp->name != NULL) {
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printf(" Class Name: %s\n", classp->name);
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printf(" Class Name: %s (0x%02x)\n", classp->name,
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PCI_CLASS(rval));
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if (subclassp != NULL && subclassp->name != NULL)
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printf(" Subclass Name: %s\n", subclassp->name);
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printf(" Subclass Name: %s (0x%02x)\n",
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subclassp->name, PCI_SUBCLASS(rval));
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else
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printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval));
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printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval));
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} else {
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printf(" Class ID: 0x%02x\n", PCI_CLASS(rval));
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printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval));
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printf(" Class ID: 0x%02x\n", PCI_CLASS(rval));
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printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval));
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}
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printf(" Interface: 0x%02x\n", PCI_INTERFACE(rval));
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printf(" Revision ID: 0x%02x\n", PCI_REVISION(rval));
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printf(" Interface: 0x%02x\n", PCI_INTERFACE(rval));
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printf(" Revision ID: 0x%02x\n", PCI_REVISION(rval));
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rval = pci_conf_read(pc, tag, PCI_BHLC_REG);
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rval = regs[o2i(PCI_BHLC_REG)];
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printf(" BIST: 0x%02x\n", PCI_BIST(rval));
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printf(" Header Type: 0x%02x%s (0x%02x)\n", PCI_HDRTYPE_TYPE(rval),
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PCI_HDRTYPE_MULTIFN(rval) ? "+multifunction" : "",
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PCI_HDRTYPE(rval));
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printf(" Latency Timer: 0x%02x\n", PCI_LATTIMER(rval));
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printf(" Cache Line Size: 0x%02x\n", PCI_CACHELINE(rval));
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}
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printf(" BIST: 0x%02x\n", PCI_BIST(rval));
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printf(" Header Type: 0x%02x\n", PCI_HDRTYPE(rval));
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printf(" Latency Timer: 0x%02x\n", PCI_LATTIMER(rval));
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printf(" Cache Line Size: 0x%02x\n", PCI_CACHELINE(rval));
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static void
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pci_conf_print_type1(pc, tag, regs)
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pci_chipset_tag_t pc;
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pcitag_t tag;
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const pcireg_t *regs;
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{
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int off, s;
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pcireg_t mask, rval;
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for (reg = PCI_MAPREG_START; reg < PCI_MAPREG_END; reg += 4) {
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for (off = PCI_MAPREG_START; off < PCI_MAPREG_END; off += 4) {
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/*
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* Section 6.2.5.1, `Address Maps', tells us that:
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*
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@ -456,51 +466,76 @@ pci_conf_print(pc, tag)
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* the bottom n bits of the address to 0. As recommended,
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* we write all 1s and see what we get back.
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*/
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s = splhigh();
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rval = pci_conf_read(pc, tag, reg);
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pci_conf_write(pc, tag, reg, 0xffffffff);
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mask = pci_conf_read(pc, tag, reg);
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pci_conf_write(pc, tag, reg, rval);
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splx(s);
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rval = regs[o2i(off)];
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if (rval != 0) {
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/*
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* The following sequence seems to make some devices
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* (e.g. host bus bridges, which don't normally
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* have their space mapped) very unhappy, to
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* the point of crashing the system.
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*
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* Therefore, if the mapping register is zero to
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* start out with, don't bother trying.
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*/
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s = splhigh();
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pci_conf_write(pc, tag, off, 0xffffffff);
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mask = pci_conf_read(pc, tag, off);
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pci_conf_write(pc, tag, off, rval);
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splx(s);
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} else
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mask = 0;
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printf(" Mapping register at 0x%02x: ", off);
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if (rval == 0) {
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printf("not implemented(?)\n");
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} else if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM) {
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const char *type, *cache;
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if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM) {
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if (PCI_MAPREG_MEM_SIZE(mask) == 0)
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continue;
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printf(" Mapping register 0x%02x\n", reg);
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printf(" Base Address: 0x%08x, size 0x%08x, "
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"type = mem", PCI_MAPREG_MEM_ADDR(rval),
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PCI_MAPREG_MEM_SIZE(mask));
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switch (PCI_MAPREG_MEM_TYPE(rval)) {
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case PCI_MAPREG_MEM_TYPE_32BIT:
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printf(", 32-bit");
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type = "32-bit";
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break;
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case PCI_MAPREG_MEM_TYPE_32BIT_1M:
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printf(", 32-bit-1M");
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type = "32-bit-1M";
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break;
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case PCI_MAPREG_MEM_TYPE_64BIT:
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printf(", 64-bit");
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type = "64-bit";
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break;
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default:
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type = "unknown (XXX)";
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break;
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}
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if (PCI_MAPREG_MEM_CACHEABLE(rval))
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printf(", cacheable");
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cache = "";
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else
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printf(", not cacheable");
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printf("\n");
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cache = "non";
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printf("%s %scacheable memory\n", type, cache);
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printf(" base address: 0x%08x, size: 0x%08x\n",
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PCI_MAPREG_MEM_ADDR(rval),
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PCI_MAPREG_MEM_SIZE(mask));
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} else {
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if (PCI_MAPREG_IO_SIZE(mask) == 0)
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continue;
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printf(" Mapping register 0x%02x\n", reg);
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printf(" Base Address: 0x%08x, size 0x%08x, "
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"type = i/o\n", PCI_MAPREG_IO_ADDR(rval),
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printf("i/o\n");
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printf(" base address: 0x%08x, size: 0x%08x\n",
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PCI_MAPREG_IO_ADDR(rval),
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PCI_MAPREG_IO_SIZE(mask));
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}
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}
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rval = pci_conf_read(pc, tag, PCI_INTERRUPT_REG);
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printf(" Cardbus CIS Pointer: 0x%08x\n", regs[o2i(0x28)]);
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printf(" Maximum Latency: 0x%08x\n", (rval >> 24) & 0xff);
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printf(" Minimum Grant: 0x%08x\n", (rval >> 16) & 0xff);
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printf(" Interrupt pin: 0x%08x", PCI_INTERRUPT_PIN(rval));
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rval = regs[o2i(0x2c)];
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printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval));
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printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval));
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/* XXX */
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printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x30)]);
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printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]);
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printf(" Reserved @ 0x38: 0x%08x\n", regs[o2i(0x38)]);
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rval = regs[o2i(PCI_INTERRUPT_REG)];
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printf(" Maximum Latency: 0x%02x\n", (rval >> 24) & 0xff);
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printf(" Minimum Grant: 0x%02x\n", (rval >> 16) & 0xff);
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printf(" Interrupt pin: 0x%02x", PCI_INTERRUPT_PIN(rval));
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switch (PCI_INTERRUPT_PIN(rval)) {
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case PCI_INTERRUPT_PIN_NONE:
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printf(" (none)");
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@ -519,5 +554,67 @@ pci_conf_print(pc, tag)
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break;
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}
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printf("\n");
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printf(" Interrupt line: 0x%08x\n", PCI_INTERRUPT_LINE(rval));
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printf(" Interrupt line: 0x%02x\n", PCI_INTERRUPT_LINE(rval));
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}
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void
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pci_conf_print(pc, tag, printfn)
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pci_chipset_tag_t pc;
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pcitag_t tag;
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void (*printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *);
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{
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pcireg_t regs[o2i(256)];
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int off, hdrtype;
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void (*typeprintfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *);
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printf("PCI configuration registers:\n");
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for (off = 0; off < 256; off += 4)
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regs[o2i(off)] = pci_conf_read(pc, tag, off);
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#define print16regs(offset) \
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printf(" 0x%02x: 0x%08x 0x%08x 0x%08x 0x%08x\n", (offset), \
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regs[o2i((offset))], regs[o2i((offset) + 4)], \
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regs[o2i((offset) + 8)], regs[o2i((offset) + 12)]);
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/* common header */
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printf(" Common header:\n");
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for (off = 0; off < 16; off += 16)
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print16regs(off);
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printf("\n");
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pci_conf_print_common(pc, tag, regs);
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printf("\n");
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/* type-dependent header */
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hdrtype = PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]);
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printf(" Type %d header:\n", hdrtype);
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for (off = 16; off < 64; off += 16)
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print16regs(off);
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printf("\n");
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switch (hdrtype) { /* XXX make a table, eventually */
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case 0:
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typeprintfn = &pci_conf_print_type1;
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break;
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case 1:
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/* XXX */
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default:
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typeprintfn = 0;
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}
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if (typeprintfn)
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(*typeprintfn)(pc, tag, regs);
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else
|
||||
printf(" Don't know how to pretty-print type %d header.\n",
|
||||
hdrtype);
|
||||
printf("\n");
|
||||
|
||||
/* device-dependent header */
|
||||
printf(" Device-dependent header:\n");
|
||||
for (off = 64; off < 256; off += 16)
|
||||
print16regs(off);
|
||||
printf("\n");
|
||||
if (printfn)
|
||||
(*printfn)(pc, tag, regs);
|
||||
else
|
||||
printf(" Don't know how to pretty-print device-dependent header.\n");
|
||||
printf("\n");
|
||||
}
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: pcivar.h,v 1.30 1998/05/15 12:35:06 tsubai Exp $ */
|
||||
/* $NetBSD: pcivar.h,v 1.31 1998/05/18 17:25:18 cgd Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1996, 1997 Christopher G. Demetriou. All rights reserved.
|
||||
@ -159,7 +159,8 @@ int pci_mapreg_map __P((struct pci_attach_args *, int, pcireg_t, int,
|
||||
* Helper functions for autoconfiguration.
|
||||
*/
|
||||
void pci_devinfo __P((pcireg_t, pcireg_t, int, char *));
|
||||
void pci_conf_print __P((pci_chipset_tag_t, pcitag_t));
|
||||
void pci_conf_print __P((pci_chipset_tag_t, pcitag_t,
|
||||
void (*)(pci_chipset_tag_t, pcitag_t, const pcireg_t *)));
|
||||
void set_pci_isa_bridge_callback __P((void (*)(void *), void *));
|
||||
|
||||
#endif /* _DEV_PCI_PCIVAR_H_ */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user