XU4 FDT final checkpoint
step N of N: get rid of baggage by removing whole files. What's left is in approximately the same shape as when the FDT update started, that is mostly broken. What's missing is most of the 76 devices recognized in the dtd. In other words, This is barely the start of a port. Next up, gpio then i2c, followed either by straightening out usb or getting the sdhc driver to work -- both probably require getting the interrupt combiner to work first. A large chunk of work is left to do on the clocks. I barely got them attaching to fdt and didn't do anything to take advantage of the information in the dtd. None of the other existing drivers, such as they are, properly request gpios, i2c or clocks, and, of course power domains are off the table.
This commit is contained in:
marty
parent
7bb55e0310
commit
4abb095283
@ -1,309 +0,0 @@
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/* $NetBSD: exynos4_loc.c,v 1.11 2014/09/05 08:01:05 skrll Exp $ */
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/*-
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* Copyright (c) 2014 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Nick Hudson
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arm/samsung/exynos_io.h>
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#include <arm/samsung/exynos_intr.h>
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#include <arm/samsung/exynos4_reg.h>
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#define IRQ_G3D_IRQGP IRQ_SPI(127)
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#define IRQ_G3D_IRQPP3 IRQ_SPI(126)
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#define IRQ_G3D_IRQPP2 IRQ_SPI(125)
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#define IRQ_G3D_IRQPP1 IRQ_SPI(124)
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#define IRQ_G3D_IRQPP0 IRQ_SPI(123)
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#define IRQ_G3D_IRQGPMMU IRQ_SPI(122)
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#define IRQ_G3D_IRQPPMMU3 IRQ_SPI(121)
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#define IRQ_G3D_IRQPPMMU2 IRQ_SPI(120)
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#define IRQ_G3D_IRQPPMMU1 IRQ_SPI(119)
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#define IRQ_G3D_IRQPPMMU0 IRQ_SPI(118)
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#define IRQ_G3D_IRQPMU IRQ_SPI(117)
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#define IRQ_C2C_SSCM_1 IRQ_SPI(116)
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#define IRQ_TSI IRQ_SPI(115)
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#define IRQ_CEC IRQ_SPI(114)
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#define IRQ_SLIMBUS IRQ_SPI(113)
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#define IRQ_SSS IRQ_SPI(112)
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#define IRQ_GPS IRQ_SPI(111)
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#define IRQ_PMU IRQ_SPI(110)
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#define IRQ_KEYPAD IRQ_SPI(109)
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#define IRQ_FIMC_LITE1 IRQ_SPI(106)
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#define IRQ_FIMC_LITE0 IRQ_SPI(105)
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#define IRQ_SPDIF IRQ_SPI(104)
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#define IRQ_PCM2 IRQ_SPI(103)
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#define IRQ_PCM1 IRQ_SPI(102)
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#define IRQ_PCM0 IRQ_SPI(101)
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#define IRQ_AC97 IRQ_SPI(100)
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#define IRQ_I2S2 IRQ_SPI(99)
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#define IRQ_I2S1 IRQ_SPI(98)
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#define IRQ_I2S0 IRQ_SPI(97)
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#define IRQ_AUDIO_SS IRQ_SPI(96)
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#define IRQ_ISP_1 IRQ_SPI(95)
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#define IRQ_MFC IRQ_SPI(94)
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#define IRQ_HDMI_I2C IRQ_SPI(93)
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#define IRQ_HDMI IRQ_SPI(92)
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#define IRQ_MIXER IRQ_SPI(91)
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#define IRQ_ISP_0 IRQ_SPI(90)
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#define IRQ_G2D IRQ_SPI(89)
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#define IRQ_JPEG IRQ_SPI(88)
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#define IRQ_FIMC3 IRQ_SPI(87)
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#define IRQ_FIMC2 IRQ_SPI(86)
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#define IRQ_FIMC1 IRQ_SPI(85)
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#define IRQ_FIMC0 IRQ_SPI(84)
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#define IRQ_ROTATOR IRQ_SPI(83)
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#define IRQ_MIPI_CSI_2LANE IRQ_SPI(80)
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#define IRQ_MIPI_DSI_4LANE IRQ_SPI(79)
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#define IRQ_MIPI_CSI_4LANE IRQ_SPI(78)
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#define IRQ_SDMMC IRQ_SPI(77)
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#define IRQ_HSMMC3 IRQ_SPI(76)
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#define IRQ_HSMMC2 IRQ_SPI(75)
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#define IRQ_HSMMC1 IRQ_SPI(74)
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#define IRQ_HSMMC0 IRQ_SPI(73)
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#define IRQ_GPIO_C2C IRQ_SPI(72)
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#define IRQ_HSOTG IRQ_SPI(71)
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#define IRQ_UHOST IRQ_SPI(70)
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#define IRQ_G1_IRQ IRQ_SPI(69)
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#define IRQ_SPI2 IRQ_SPI(68)
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#define IRQ_SPI1 IRQ_SPI(67)
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#define IRQ_SPI0 IRQ_SPI(66)
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#define IRQ_I2C7 IRQ_SPI(65)
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#define IRQ_I2C6 IRQ_SPI(64)
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#define IRQ_I2C5 IRQ_SPI(63)
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#define IRQ_I2C4 IRQ_SPI(62)
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#define IRQ_I2C3 IRQ_SPI(61)
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#define IRQ_I2C2 IRQ_SPI(60)
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#define IRQ_I2C1 IRQ_SPI(59)
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#define IRQ_I2C0 IRQ_SPI(58)
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#define IRQ_G0_IRQ IRQ_SPI(57)
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#define IRQ_UART3 IRQ_SPI(55)
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#define IRQ_UART2 IRQ_SPI(54)
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#define IRQ_UART1 IRQ_SPI(53)
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#define IRQ_UART0 IRQ_SPI(52)
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#define IRQ_NFC IRQ_SPI(51)
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#define IRQ_IEM_IEC IRQ_SPI(50)
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#define IRQ_IEM_APC IRQ_SPI(49)
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#define IRQ_GPIO_LB IRQ_SPI(47)
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#define IRQ_GPIO_RT IRQ_SPI(46)
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#define IRQ_RTC_TIC IRQ_SPI(45)
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#define IRQ_RTC_ALARM IRQ_SPI(44)
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#define IRQ_WDT IRQ_SPI(43)
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#define IRQ_TIMER4 IRQ_SPI(41)
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#define IRQ_TIMER3 IRQ_SPI(40)
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#define IRQ_TIMER2 IRQ_SPI(39)
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#define IRQ_TIMER1 IRQ_SPI(38)
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#define IRQ_TIMER0 IRQ_SPI(37)
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#define IRQ_PDMA1 IRQ_SPI(36)
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#define IRQ_PDMA0 IRQ_SPI(35)
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#define IRQ_MDMA IRQ_SPI(34)
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#define IRQ_C2C_SSCM_0 IRQ_SPI(33)
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#define IRQ_EINT16_31 IRQ_SPI(32)
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#define IRQ_EINT_15 IRQ_SPI(31)
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#define IRQ_EINT_14 IRQ_SPI(30)
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#define IRQ_EINT_13 IRQ_SPI(29)
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#define IRQ_EINT_12 IRQ_SPI(28)
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#define IRQ_EINT_11 IRQ_SPI(27)
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#define IRQ_EINT_10 IRQ_SPI(26)
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#define IRQ_EINT_9 IRQ_SPI(25)
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#define IRQ_EINT_8 IRQ_SPI(24)
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#define IRQ_EINT_7 IRQ_SPI(23)
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#define IRQ_EINT_6 IRQ_SPI(22)
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#define IRQ_EINT_5 IRQ_SPI(21)
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#define IRQ_EINT_4 IRQ_SPI(20)
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#define IRQ_EINT_3 IRQ_SPI(19)
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#define IRQ_EINT_2 IRQ_SPI(18)
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#define IRQ_EINT_1 IRQ_SPI(17)
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#define IRQ_EINT_0 IRQ_SPI(16)
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/* rest of PPI's marked reserved */
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#define IRQ_MCT_L IRQ_PPI(12)
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#define IRQ_MCT_G IRQ_PPI(10)
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#define IRQ_CPU_NIRQOUT_3 EXYNOS_COMBINERIRQ(19, 6)
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#define IRQ_PARITYFAILSCU_3 EXYNOS_COMBINERIRQ(19, 5)
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#define IRQ_PARITYFAIL3 EXYNOS_COMBINERIRQ(19, 4)
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#define IRQ_NCTIIRQ_3 EXYNOS_COMBINERIRQ(19, 3)
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#define IRQ_PMUIRQ_3 EXYNOS_COMBINERIRQ(19, 2)
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#define IRQ_MCT_L0_IRQ EXYNOS_COMBINERIRQ(19, 0)
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#define IRQ_CPU_NIRQOUT_2 EXYNOS_COMBINERIRQ(18, 6)
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#define IRQ_PARITYFAILSCU_2 EXYNOS_COMBINERIRQ(18, 5)
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#define IRQ_PARITYFAIL2 EXYNOS_COMBINERIRQ(18, 4)
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#define IRQ_NCTIIRQ_2 EXYNOS_COMBINERIRQ(18, 3)
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#define IRQ_PMUIRQ_2 EXYNOS_COMBINERIRQ(18, 2)
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#define IRQ_MCT_L1_IRQ EXYNOS_COMBINERIRQ(18, 0)
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#define IRQ_MCT_L2_IRQ EXYNOS_COMBINERIRQ(17, 7)
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#define IRQ_SYSMMU_ISP_CX_1 EXYNOS_COMBINERIRQ(17, 5)
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#define IRQ_SYSMMU_FIMC_FD_1 EXYNOS_COMBINERIRQ(17, 4)
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#define IRQ_SYSMMU_FIMC_DRC_1 EXYNOS_COMBINERIRQ(17, 3)
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#define IRQ_SYSMMU_FIMC_ISP_1 EXYNOS_COMBINERIRQ(17, 2)
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#define IRQ_SYSMMU_FIMC_LITE1_1 EXYNOS_COMBINERIRQ(17, 1)
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#define IRQ_SYSMMU_FIMC_LITE0_1 EXYNOS_COMBINERIRQ(17, 0)
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#define IRQ_MCT_L3_IRQ EXYNOS_COMBINERIRQ(16, 7)
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#define IRQ_SYSMMU_ISP_CX_0 EXYNOS_COMBINERIRQ(16, 5)
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#define IRQ_SYSMMU_FIMC_FD_0 EXYNOS_COMBINERIRQ(16, 4)
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#define IRQ_SYSMMU_FIMC_DRC_0 EXYNOS_COMBINERIRQ(16, 3)
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#define IRQ_SYSMMU_FIMC_ISP_0 EXYNOS_COMBINERIRQ(16, 2)
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#define IRQ_SYSMMU_FIMC_LITE1_0 EXYNOS_COMBINERIRQ(16, 1)
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#define IRQ_SYSMMU_FIMC_LITE0_0 EXYNOS_COMBINERIRQ(16, 0)
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#define IRQ_DECERRINTR EXYNOS_COMBINERIRQ(15, 7)
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#define IRQ_SLVERRINTR EXYNOS_COMBINERIRQ(15, 6)
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#define IRQ_ERRRDINTR EXYNOS_COMBINERIRQ(15, 5)
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#define IRQ_ERRRTINTR EXYNOS_COMBINERIRQ(15, 4)
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#define IRQ_ERRWDINTR EXYNOS_COMBINERIRQ(15, 3)
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#define IRQ_ERRWTINTR EXYNOS_COMBINERIRQ(15, 2)
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#define IRQ_ECNTRINTR EXYNOS_COMBINERIRQ(15, 1)
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#define IRQ_SCUEVABORT EXYNOS_COMBINERIRQ(15, 0)
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#define IRQ_CPU_NIRQOUT_1 EXYNOS_COMBINERIRQ(14, 6)
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#define IRQ_CPU_NIRQOUT_0 EXYNOS_COMBINERIRQ(13, 5)
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#define IRQ_MCT_G3 EXYNOS_COMBINERIRQ(12, 7)
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#define IRQ_MCT_G2 EXYNOS_COMBINERIRQ(12, 6)
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#define IRQ_MCT_G1 EXYNOS_COMBINERIRQ(12, 5)
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#define IRQ_MCT_G0 EXYNOS_COMBINERIRQ(12, 4)
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#define IRQ_MIPI_HSI EXYNOS_COMBINERIRQ(12, 1)
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#define IRQ_UART4 EXYNOS_COMBINERIRQ(12, 0)
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#define IRQ_LCD0_3 EXYNOS_COMBINERIRQ(11, 3)
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#define IRQ_LCD0_2 EXYNOS_COMBINERIRQ(11, 2)
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#define IRQ_LCD0_1 EXYNOS_COMBINERIRQ(11, 1)
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#define IRQ_LCD0_0 EXYNOS_COMBINERIRQ(11, 0)
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#define IRQ_DMC1_PPC_PEREV_M EXYNOS_COMBINERIRQ(10, 7)
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#define IRQ_DMC1_PPC_PEREV_A EXYNOS_COMBINERIRQ(10, 6)
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#define IRQ_DMC0_PPC_PEREV_M EXYNOS_COMBINERIRQ(10, 5)
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#define IRQ_DMC0_PPC_PEREV_A EXYNOS_COMBINERIRQ(10, 4)
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#define IRQ_ADC EXYNOS_COMBINERIRQ(10, 3)
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#define IRQ_L2CACHE EXYNOS_COMBINERIRQ(10, 2)
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#define IRQ_RP_TIMER EXYNOS_COMBINERIRQ(10, 1)
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#define IRQ_GPIO_AUDIO EXYNOS_COMBINERIRQ(10, 0)
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#define IRQ_PPMU_ISP_X EXYNOS_COMBINERIRQ(9, 7)
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#define IRQ_PPMU_MFC_M1 EXYNOS_COMBINERIRQ(9, 6)
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#define IRQ_PPMU_MFC_M0 EXYNOS_COMBINERIRQ(9, 5)
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#define IRQ_PPMU_3D EXYNOS_COMBINERIRQ(9, 4)
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#define IRQ_PPMU_TV_M0 EXYNOS_COMBINERIRQ(9, 3)
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#define IRQ_PPMU_FILE_D_M0 EXYNOS_COMBINERIRQ(9, 2)
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#define IRQ_PPMU_ISP_MX EXYNOS_COMBINERIRQ(9, 1)
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#define IRQ_PPMU_LCD0 EXYNOS_COMBINERIRQ(9, 0)
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#define IRQ_PPMU_IMAGE_M0 EXYNOS_COMBINERIRQ(8, 7)
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#define IRQ_PPMU_CAMIF_M0 EXYNOS_COMBINERIRQ(8, 6)
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#define IRQ_PPMU_D_RIGHT_M0 EXYNOS_COMBINERIRQ(8, 5)
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#define IRQ_PPMU_D_LEFT_M0 EXYNOS_COMBINERIRQ(8, 4)
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#define IRQ_PPMU_ACP0_M0 EXYNOS_COMBINERIRQ(8, 3)
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#define IRQ_PPMU_XIU_R_S1 EXYNOS_COMBINERIRQ(8, 2)
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#define IRQ_PPMU_XIU_R EXYNOS_COMBINERIRQ(8, 1)
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#define IRQ_PPMU_XIU_L EXYNOS_COMBINERIRQ(8, 0)
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#define IRQ_SYSMMU_MFC_M1_1 EXYNOS_COMBINERIRQ(7, 6)
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#define IRQ_SYSMMU_MFC_M0_1 EXYNOS_COMBINERIRQ(7, 5)
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#define IRQ_SYSMMU_TV_M0_1 EXYNOS_COMBINERIRQ(7, 4)
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#define IRQ_SYSMMU_LCD0_M0_1 EXYNOS_COMBINERIRQ(7, 2)
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#define IRQ_SYSMMU_GPS_1 EXYNOS_COMBINERIRQ(7, 1)
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#define IRQ_SYSMMU_ROTATOR_1 EXYNOS_COMBINERIRQ(7, 0)
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#define IRQ_SYSMMU_2D_1 EXYNOS_COMBINERIRQ(6, 7)
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#define IRQ_SYSMMU_JPEG_1 EXYNOS_COMBINERIRQ(6, 6)
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#define IRQ_SYSMMU_FIMC3_1 EXYNOS_COMBINERIRQ(6, 5)
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#define IRQ_SYSMMU_FIMC2_1 EXYNOS_COMBINERIRQ(6, 4)
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#define IRQ_SYSMMU_FIMC1_1 EXYNOS_COMBINERIRQ(6, 3)
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#define IRQ_SYSMMU_FIMC0_1 EXYNOS_COMBINERIRQ(6, 2)
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#define IRQ_SYSMMU_SSS_1 EXYNOS_COMBINERIRQ(6, 1)
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#define IRQ_SYSMMU_MDMA_1 EXYNOS_COMBINERIRQ(6, 0)
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#define IRQ_SYSMMU_MFC_M1_0 EXYNOS_COMBINERIRQ(5, 6)
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#define IRQ_SYSMMU_MFC_M0_0 EXYNOS_COMBINERIRQ(5, 5)
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#define IRQ_SYSMMU_TV_M0_0 EXYNOS_COMBINERIRQ(5, 4)
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#define IRQ_SYSMMU_LCD0_M0_0 EXYNOS_COMBINERIRQ(5, 2)
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#define IRQ_SYSMMU_GPS_0 EXYNOS_COMBINERIRQ(5, 1)
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#define IRQ_SYSMMU_ROTATOR_0 EXYNOS_COMBINERIRQ(5, 0)
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#define IRQ_SYSMMU_2D_0 EXYNOS_COMBINERIRQ(4, 7)
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#define IRQ_SYSMMU_JPEG_0 EXYNOS_COMBINERIRQ(4, 6)
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#define IRQ_SYSMMU_FIMC3_0 EXYNOS_COMBINERIRQ(4, 5)
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#define IRQ_SYSMMU_FIMC2_0 EXYNOS_COMBINERIRQ(4, 4)
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#define IRQ_SYSMMU_FIMC1_0 EXYNOS_COMBINERIRQ(4, 3)
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#define IRQ_SYSMMU_FIMC0_0 EXYNOS_COMBINERIRQ(4, 2)
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#define IRQ_SYSMMU_SSS_0 EXYNOS_COMBINERIRQ(4, 1)
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#define IRQ_SYSMMU_MDMA_0 EXYNOS_COMBINERIRQ(4, 0)
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#define IRQ_NCTIIRQ_ISP EXYNOS_COMBINERIRQ(3, 6)
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#define IRQ_PMUIRQ_ISP EXYNOS_COMBINERIRQ(3, 5)
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#define IRQ_TMU_1 EXYNOS_COMBINERIRQ(3, 4)
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#define IRQ_NCTIIRQ_1 EXYNOS_COMBINERIRQ(3, 3)
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#define IRQ_PMUIRQ_1 EXYNOS_COMBINERIRQ(3, 2)
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#define IRQ_PARITYFAILSCU_1 EXYNOS_COMBINERIRQ(3, 1)
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#define IRQ_PARITYFAIL1 EXYNOS_COMBINERIRQ(3, 0)
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#define IRQ_PARRINTR EXYNOS_COMBINERIRQ(2, 6)
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#define IRQ_PARRDINTR EXYNOS_COMBINERIRQ(2, 5)
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#define IRQ_TMU_0 EXYNOS_COMBINERIRQ(2, 4)
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#define IRQ_NCTIIRQ_0 EXYNOS_COMBINERIRQ(2, 3)
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#define IRQ_PMUIRQ_0 EXYNOS_COMBINERIRQ(2, 2)
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#define IRQ_PARITYFAILSCU_0 EXYNOS_COMBINERIRQ(2, 1)
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#define IRQ_PARITYFAIL0 EXYNOS_COMBINERIRQ(2, 0)
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#define IRQ_TZASC1_1 EXYNOS_COMBINERIRQ(1, 3)
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#define IRQ_TZASC1_0 EXYNOS_COMBINERIRQ(1, 2)
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#define IRQ_TZASC0_1 EXYNOS_COMBINERIRQ(1, 1)
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#define IRQ_TZASC0_0 EXYNOS_COMBINERIRQ(1, 0)
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#define IRQ_MDNIE_LCD0_3 EXYNOS_COMBINERIRQ(0, 3)
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#define IRQ_MDNIE_LCD0_2 EXYNOS_COMBINERIRQ(0, 2)
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#define IRQ_MDNIE_LCD0_1 EXYNOS_COMBINERIRQ(0, 1)
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#define IRQ_MDNIE_LCD0_0 EXYNOS_COMBINERIRQ(0, 0)
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#define OFFANDSIZE(p,n) \
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EXYNOS4##p##_##n##_OFFSET, 0x10000
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static const struct exyo_locators exynos4_locators[] = {
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{ "exyogpio", 0, 0, NOPORT, NOINTR, 0 },
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{ "exyoiic", 0, 0, NOPORT, NOINTR, 0 },
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{ "mct", OFFANDSIZE(,MCT), NOPORT, IRQ_MCT_G, 0 },
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{ "exyowdt", OFFANDSIZE(,WDT), NOPORT, IRQ_WDT, 0 },
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{ "sscom", OFFANDSIZE(,UART0), 0, IRQ_UART0, 0 },
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{ "sscom", OFFANDSIZE(,UART1), 1, IRQ_UART1, 0 },
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{ "sscom", OFFANDSIZE(,UART2), 2, IRQ_UART2, 0 },
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{ "sscom", OFFANDSIZE(,UART3), 3, IRQ_UART3, 0 },
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{ "exyousb", OFFANDSIZE(,USB2HOST), NOPORT, IRQ_UHOST, 0 },
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};
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||||
|
||||
const struct exyo_locinfo exynos4_locinfo = {
|
||||
.locators = exynos4_locators,
|
||||
.nlocators = __arraycount(exynos4_locators)
|
||||
};
|
||||
|
||||
|
||||
/* flag signal the use of gpio */
|
||||
static const struct exyo_locators exynos4_i2c_locators[] = {
|
||||
/* busname, sdabit, slcbit, func */
|
||||
{ "iic0", OFFANDSIZE(,I2C0), 0, IRQ_I2C0, 1 , "GPD1", 0, 1, 2 },
|
||||
{ "iic1", OFFANDSIZE(,I2C1), 1, IRQ_I2C1, 1 , "GPD1", 2, 3, 2 },
|
||||
{ "iic2", OFFANDSIZE(,I2C2), 2, IRQ_I2C2, 1 , "GPA0", 6, 7, 2 },
|
||||
{ "iic3", OFFANDSIZE(,I2C3), 3, IRQ_I2C3, 1 , "GPA1", 2, 3, 3 },
|
||||
{ "iic4", OFFANDSIZE(,I2C4), 4, IRQ_I2C4, 1 , "GPB", 0, 1, 3 },
|
||||
{ "iic5", OFFANDSIZE(,I2C5), 5, IRQ_I2C5, 1 , "GPB", 2, 3, 3 },
|
||||
{ "iic6", OFFANDSIZE(,I2C6), 6, IRQ_I2C6, 1 , "GPC1", 3, 4, 4 },
|
||||
{ "iic7", OFFANDSIZE(,I2C7), 7, IRQ_I2C7, 1 , "GPD0", 2, 3, 3 },
|
||||
{ "iic8", OFFANDSIZE(,I2CHDMI), 8, IRQ_HDMI_I2C, 0 , "", 0, 0, 0 },
|
||||
};
|
||||
|
||||
|
||||
const struct exyo_locinfo exynos4_i2c_locinfo = {
|
||||
.locators = exynos4_i2c_locators,
|
||||
.nlocators = __arraycount(exynos4_i2c_locators)
|
||||
};
|
||||
|
||||
@ -1,300 +0,0 @@
|
||||
/* $NetBSD: exynos4_reg.h,v 1.13 2014/09/05 08:01:05 skrll Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 2014 The NetBSD Foundation, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This code is derived from software contributed to The NetBSD Foundation
|
||||
* by Reinoud Zandijk.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
|
||||
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _ARM_SAMSUNG_EXYNOS4_REG_H_
|
||||
#define _ARM_SAMSUNG_EXYNOS4_REG_H_
|
||||
|
||||
/*
|
||||
* Physical memory layout of Exynos SoCs as per documentation
|
||||
*
|
||||
* Base Address Limit Address Size Description
|
||||
* 0x00000000 0x00010000 64 KB iROM
|
||||
* 0x02000000 0x02010000 64 KB iROM (mirror of 0x0 to 0x10000)
|
||||
* 0x02020000 0x02060000 256 KB iRAM
|
||||
* 0x03000000 0x03020000 128 KB Data memory or general purpose of Samsung
|
||||
* Reconfigurable Processor SRP.
|
||||
* 0x03020000 0x03030000 64 KB I-cache or general purpose of SRP.
|
||||
* 0x03030000 0x03039000 36 KB Configuration memory (write only) of SRP
|
||||
* 0x03810000 0x03830000 AudioSS's SFR region
|
||||
* 0x04000000 0x05000000 16 MB Bank0 of Static ROM Controller (SMC)
|
||||
* (16-bit only)
|
||||
* 0x05000000 0x06000000 16 MB Bank1 of SMC
|
||||
* 0x06000000 0x07000000 16 MB Bank2 of SMC
|
||||
* 0x07000000 0x08000000 16 MB Bank3 of SMC
|
||||
* 0x08000000 0x0C000000 64 MB Reserved
|
||||
* 0x0C000000 0x0CD00000 Reserved
|
||||
* 0x0CE00000 0x0D000000 SFR region of Nand Flash Contr. (NFCON)
|
||||
* 0x10000000 0x14000000 SFR region
|
||||
* 0x40000000 0xA0000000 1.5 GB Memory of Dynamic Memory Contr. (DMC)-0
|
||||
* 0xA0000000 0x00000000 1.5 GB Memory of DMC-1
|
||||
*/
|
||||
|
||||
/*
|
||||
*
|
||||
* The exynos can boot from its iROM or from an external Nand memory. Since
|
||||
* these are normally hardly used they are excluded from the normal register
|
||||
* space here.
|
||||
*
|
||||
* XXX What about the audio subsystem region. Where are the docs?
|
||||
*
|
||||
* EXYNOS_CORE_PBASE points to the main SFR region.
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
* SFR Special Function Register
|
||||
* ISP In-System Programming, like a JTAG
|
||||
* ACP Accelerator Coherency Port
|
||||
* SSS Security Sub System
|
||||
* GIC Generic Interurrupt Controller
|
||||
* PMU Power Management Unit
|
||||
* DMC 2D Graphics engine
|
||||
* LEFTBUS Data bus / Peripheral bus
|
||||
* RIGHTBUS ,,
|
||||
* G3D 3D Graphics engine
|
||||
* MFC Multi-Format Codec
|
||||
* LCD0 LCD display
|
||||
* MCT Multi Core Timer
|
||||
* CMU Clock Management Unit
|
||||
* TMU Thermal Management Unit
|
||||
* PPMU Pin Parametric Measurement Unit (?)
|
||||
* MMU Memory Management Unit
|
||||
* MCTimer ?
|
||||
* WDT Watch Dog Timer
|
||||
* RTC Real Time Clock
|
||||
* KEYIF Keypad interface
|
||||
* SECKEY ?
|
||||
* TZPC TrustZone Protection Controller
|
||||
* UART Universal asynchronous receiver/transmitter
|
||||
* I2C Inter IC Connect
|
||||
* SPI Serial Peripheral Interface Bus
|
||||
* I2S Inter-IC Sound, Integrated Interchip Sound, or IIS
|
||||
* PCM Pulse-code modulation, audio stream at set fixed rate
|
||||
* SPDIF Sony/Philips Digital Interface Format
|
||||
* Slimbus Serial Low-power Inter-chip Media Bus
|
||||
* SMMU System mmu. No idea as how its programmed (or not)
|
||||
* PERI-L UART, I2C, SPI, I2S, PCM, SPDIF, PWM, I2CHDMI, Slimbus
|
||||
* PERI-R CHIPID, SYSREG, PMU/CMU/TMU Bus I/F, MCTimer, WDT, RTC, KEYIF,
|
||||
* SECKEY, TZPC
|
||||
*/
|
||||
|
||||
/*
|
||||
* Note that this table is not 80-char friendly, this is done to allow more
|
||||
* elaborate comments to clarify the register offsets use
|
||||
*/
|
||||
|
||||
/* CORE */
|
||||
#define EXYNOS4_CORE_SIZE 0x04000000
|
||||
#define EXYNOS4_SDRAM_PBASE 0x40000000
|
||||
|
||||
#define EXYNOS4_SYSREG_OFFSET 0x00010000
|
||||
#define EXYNOS4_PMU_OFFSET 0x00020000 /* Power Management Unit */
|
||||
#define EXYNOS4_CMU_TOP_PART_OFFSET 0x00030000 /* Clock(s) management unit */
|
||||
#define EXYNOS4_CMU_EPLL 0x0003C010 /* Audio and ext. interf. clock */
|
||||
#define EXYNOS4_CMU_VPLL 0x0003C020 /* Video core (dither?) clock */
|
||||
#define EXYNOS4_CMU_CORE_ISP_PART_OFFSET 0x00040000 /* Clock(s) management unit */
|
||||
#define EXYNOS4_CMU_MPLL 0x00040008 /* MEM cntr. clock */
|
||||
#define EXYNOS4_CMU_APLL 0x00044000 /* ARM core clock */
|
||||
#define EXYNOS4_MCT_OFFSET 0x00050000 /* Multi Core Timer */
|
||||
#define EXYNOS4_WDT_OFFSET 0x00060000 /* Watch Dog Timer */
|
||||
#define EXYNOS4_RTC_OFFSET 0x00070000 /* Real Time Clock */
|
||||
#define EXYNOS4_KEYIF_OFFSET 0x000A0000 /* Keypad interface */
|
||||
#define EXYNOS4_HDMI_CEC_OFFSET 0x000B0000 /* HDMI Consumer Electronic Control */
|
||||
#define EXYNOS4_TMU_OFFSET 0x000C0000 /* Thermal Managment */
|
||||
#define EXYNOS4_SECKEY_OFFSET 0x00100000 /* XXX unknown XXX */
|
||||
#define EXYNOS4_TZPC0_OFFSET 0x00110000 /* ARM Trusted Zone Protection Controller */
|
||||
#define EXYNOS4_TZPC1_OFFSET 0x00120000
|
||||
#define EXYNOS4_TZPC2_OFFSET 0x00130000
|
||||
#define EXYNOS4_TZPC3_OFFSET 0x00140000
|
||||
#define EXYNOS4_TZPC4_OFFSET 0x00150000
|
||||
#define EXYNOS4_TZPC5_OFFSET 0x00160000
|
||||
#define EXYNOS4_INTCOMBINER_OFFSET 0x00440000 /* combines first 32 interrupt sources */
|
||||
#define EXYNOS4_GIC_CNTR_OFFSET 0x00480000 /* generic interrupt controller offset */
|
||||
#define EXYNOS4_GIC_DISTRIBUTOR_OFFSET 0x00490000
|
||||
#define EXYNOS4_AP_C2C_OFFSET 0x00540000 /* Chip 2 Chip XXX doc? XXX */
|
||||
#define EXYNOS4_CP_C2C_MODEM_OFFSET 0x00580000
|
||||
#define EXYNOS4_DMC0_OFFSET 0x00600000 /* Dynamic Memory Controller */
|
||||
#define EXYNOS4_DMC1_OFFSET 0x00610000
|
||||
#define EXYNOS4_PPMU_DMC_L_OFFSET 0x006A0000 /* event counters XXX ? */
|
||||
#define EXYNOS4_PPMU_DMC_R_OFFSET 0x006B0000
|
||||
#define EXYNOS4_PPMU_CPU_OFFSET 0x006C0000
|
||||
#define EXYNOS4_GPIO_C2C_OFFSET 0x006E0000
|
||||
#define EXYNOS4_TZASC_LR_OFFSET 0x00700000 /* trust zone access control */
|
||||
#define EXYNOS4_TZASC_LW_OFFSET 0x00710000
|
||||
#define EXYNOS4_TZASC_RR_OFFSET 0x00720000
|
||||
#define EXYNOS4_TZASC_RW_OFFSET 0x00730000
|
||||
#define EXYNOS4_G2D_ACP_OFFSET 0x00800000 /* 2D graphics engine */
|
||||
#define EXYNOS4_SSS_OFFSET 0x00830000 /* Security Sub System */
|
||||
#define EXYNOS4_CORESIGHT_1_OFFSET 0x00880000 /* 1st region */
|
||||
#define EXYNOS4_CORESIGHT_2_OFFSET 0x00890000 /* 2nd region */
|
||||
#define EXYNOS4_CORESIGHT_3_OFFSET 0x008B0000 /* 3rd region */
|
||||
#define EXYNOS4_SMMUG2D_ACP_OFFSET 0x00A40000 /* system mmu for 2D graphics engine */
|
||||
#define EXYNOS4_SMMUSSS_OFFSET 0x00A50000 /* system mmu for SSS */
|
||||
#define EXYNOS4_GPIO_RIGHT_OFFSET 0x01000000
|
||||
#define EXYNOS4_GPIO_LEFT_OFFSET 0x01400000
|
||||
#define EXYNOS4_FIMC0_OFFSET 0x01800000 /* image for display */
|
||||
#define EXYNOS4_FIMC1_OFFSET 0x01810000
|
||||
#define EXYNOS4_FIMC2_OFFSET 0x01820000
|
||||
#define EXYNOS4_FIMC3_OFFSET 0x01830000
|
||||
#define EXYNOS4_JPEG_OFFSET 0x01840000 /* JPEG Codec */
|
||||
#define EXYNOS4_MIPI_CSI0_OFFSET 0x01880000 /* MIPI-Slim bus Interface */
|
||||
#define EXYNOS4_MIPI_CSI1_OFFSET 0x01890000
|
||||
#define EXYNOS4_SMMUFIMC0_OFFSET 0x01A20000 /* system mmus */
|
||||
#define EXYNOS4_SMMUFIMC1_OFFSET 0x01A30000
|
||||
#define EXYNOS4_SMMUFIMC2_OFFSET 0x01A40000
|
||||
#define EXYNOS4_SMMUFIMC3_OFFSET 0x01A50000
|
||||
#define EXYNOS4_SMMUJPEG_OFFSET 0x01A60000
|
||||
#define EXYNOS4_FIMD0_OFFSET 0x01C00000 /* LCD0 */
|
||||
#define EXYNOS4_MIPI_DSI0_OFFSET 0x01C80000 /* LCD0 */
|
||||
#define EXYNOS4_SMMUFIMD0_OFFSET 0x01E20000 /* system mmus */
|
||||
#define EXYNOS4_FIMC_ISP_OFFSET 0x02000000 /* (digital) camera video input */
|
||||
#define EXYNOS4_FIMC_DRC_TOP_OFFSET 0x02010000
|
||||
#define EXYNOS4_FIMC_FD_TOP_OFFSET 0x02040000
|
||||
#define EXYNOS4_MPWM_ISP_OFFSET 0x02110000 /* (specialised?) PWM */
|
||||
#define EXYNOS4_I2C0_ISP_OFFSET 0x02130000 /* I2C bus */
|
||||
#define EXYNOS4_I2C1_ISP_OFFSET 0x02140000
|
||||
#define EXYNOS4_MTCADC_ISP_OFFSET 0x02150000 /* (specialised?) AD Converter */
|
||||
#define EXYNOS4_PWM_ISP_OFFSET 0x02160000 /* PWM */
|
||||
#define EXYNOS4_WDT_ISP_OFFSET 0x02170000 /* Watch Dog Timer */
|
||||
#define EXYNOS4_MCUCTL_ISP_OFFSET 0x02180000 /* XXX unknown XXX */
|
||||
#define EXYNOS4_UART_ISP_OFFSET 0x02190000 /* uart base clock */
|
||||
#define EXYNOS4_SPI0_ISP_OFFSET 0x021A0000
|
||||
#define EXYNOS4_SPI1_ISP_OFFSET 0x021B0000
|
||||
#define EXYNOS4_GIC_C_ISP_OFFSET 0x021E0000
|
||||
#define EXYNOS4_GIC_D_ISP_OFFSET 0x021F0000
|
||||
#define EXYNOS4_SYSMMU_FIMC_ISP_OFFSET 0x02260000
|
||||
#define EXYNOS4_SYSMMU_FIMC_DRC_OFFSET 0x02270000
|
||||
#define EXYNOS4_SYSMMU_FIMC_FD_OFFSET 0x022A0000
|
||||
#define EXYNOS4_SYSMMU_ISPCPU_OFFSET 0x022B0000
|
||||
#define EXYNOS4_FIMC_LITE0_OFFSET 0x02390000 /* external image input? */
|
||||
#define EXYNOS4_FIMC_LITE1_OFFSET 0x023A0000
|
||||
#define EXYNOS4_SYSMMU_FIMC_LITE0_OFFSET 0x023B0000
|
||||
#define EXYNOS4_SYSMMU_FIMC_LITE1_OFFSET 0x023C0000
|
||||
#define EXYNOS4_USBDEV0_OFFSET 0x02480000 /* XXX unknown XXX */
|
||||
#define EXYNOS4_USBDEV0_1_OFFSET 0x02480000
|
||||
#define EXYNOS4_USBDEV0_2_OFFSET 0x02490000
|
||||
#define EXYNOS4_USBDEV0_3_OFFSET 0x024A0000
|
||||
#define EXYNOS4_USBDEV0_4_OFFSET 0x024B0000
|
||||
#define EXYNOS4_TSI_OFFSET 0x02500000 /* Transport Stream Interface */
|
||||
#define EXYNOS4_SDMMC0_OFFSET 0x02510000 /* SD card interface */
|
||||
#define EXYNOS4_SDMMC1_OFFSET 0x02520000
|
||||
#define EXYNOS4_SDMMC2_OFFSET 0x02530000
|
||||
#define EXYNOS4_SDMMC3_OFFSET 0x02540000
|
||||
#define EXYNOS4_SDMMC4_OFFSET 0x02550000
|
||||
#define EXYNOS4_MIPI_HSI_OFFSET 0x02560000 /* LCD0 */
|
||||
#define EXYNOS4_SROMC_OFFSET 0x02570000
|
||||
|
||||
#define EXYNOS4_USB2HOST_OFFSET 0x02580000
|
||||
#define EXYNOS4_USB2_HOST_EHCI_OFFSET 0x02580000
|
||||
#define EXYNOS4_USB2_HOST_OHCI_OFFSET 0x02590000
|
||||
#define EXYNOS4_USB2_HOST_PHYCTRL_OFFSET 0x025B0000
|
||||
#define EXYNOS4_USBOTG1_OFFSET 0x025B0000 /* USB On The Go interface */
|
||||
|
||||
#define EXYNOS4_PDMA0_OFFSET 0x02680000 /* Peripheral DMA */
|
||||
#define EXYNOS4_PDMA1_OFFSET 0x02690000
|
||||
#define EXYNOS4_GADC_OFFSET 0x026C0000 /* General AD Converter */
|
||||
#define EXYNOS4_ROTATOR_OFFSET 0x02810000 /* Image rotator for video output */
|
||||
#define EXYNOS4_SMDMA_OFFSET 0x02840000 /* (s) Memory DMA */
|
||||
#define EXYNOS4_NSMDMA_OFFSET 0x02850000 /* (ns) Memory DMA */
|
||||
#define EXYNOS4_SMMUROTATOR_OFFSET 0x02A30000 /* system mmu for rotator */
|
||||
#define EXYNOS4_SMMUMDMA_OFFSET 0x02A40000
|
||||
#define EXYNOS4_VP_OFFSET 0x02C00000 /* Video Processor */
|
||||
#define EXYNOS4_MIXER_OFFSET 0x02C10000 /* Video mixer */
|
||||
#define EXYNOS4_HDMI0_OFFSET 0x02D00000
|
||||
#define EXYNOS4_HDMI1_OFFSET 0x02D10000
|
||||
#define EXYNOS4_HDMI2_OFFSET 0x02D20000
|
||||
#define EXYNOS4_HDMI3_OFFSET 0x02D30000
|
||||
#define EXYNOS4_HDMI4_OFFSET 0x02D40000
|
||||
#define EXYNOS4_HDMI5_OFFSET 0x02D50000
|
||||
#define EXYNOS4_HDMI6_OFFSET 0x02D60000
|
||||
#define EXYNOS4_SMMUTV_OFFSET 0x02E20000
|
||||
#define EXYNOS4_G3D_OFFSET 0x03000000 /* 3D Graphics Accelerator */
|
||||
#define EXYNOS4_PPMU_3D_OFFSET 0x03220000
|
||||
#define EXYNOS4_MFC_OFFSET 0x03400000 /* Multi Format Codec */
|
||||
#define EXYNOS4_SMMUMFC_L_OFFSET 0x03620000
|
||||
#define EXYNOS4_SMMUMFC_R_OFFSET 0x03630000
|
||||
#define EXYNOS4_PMMU_MFC_L_OFFSET 0x03660000 /* ? */
|
||||
#define EXYNOS4_PMMU_MFC_R_OFFSET 0x03670000 /* ? */
|
||||
#define EXYNOS4_UART0_OFFSET 0x03800000 /* serial port 0 */
|
||||
#define EXYNOS4_UART1_OFFSET 0x03810000 /* serial port 1 */
|
||||
#define EXYNOS4_UART2_OFFSET 0x03820000 /* serial port 2 */
|
||||
#define EXYNOS4_UART3_OFFSET 0x03830000 /* serial port 3 */
|
||||
#define EXYNOS4_UART4_OFFSET 0x03840000 /* serial port 4 */
|
||||
#define EXYNOS4_I2C0_OFFSET 0x03860000 /* Inter Integrated Circuit (I2C) */
|
||||
#define EXYNOS4_I2C1_OFFSET 0x03870000 /* Inter Integrated Circuit (I2C) */
|
||||
#define EXYNOS4_I2C2_OFFSET 0x03880000 /* Inter Integrated Circuit (I2C) */
|
||||
#define EXYNOS4_I2C3_OFFSET 0x03890000 /* Inter Integrated Circuit (I2C) */
|
||||
#define EXYNOS4_I2C4_OFFSET 0x038A0000 /* Inter Integrated Circuit (I2C) */
|
||||
#define EXYNOS4_I2C5_OFFSET 0x038B0000 /* Inter Integrated Circuit (I2C) */
|
||||
#define EXYNOS4_I2C6_OFFSET 0x038C0000 /* Inter Integrated Circuit (I2C) */
|
||||
#define EXYNOS4_I2C7_OFFSET 0x038D0000 /* Inter Integrated Circuit (I2C) */
|
||||
#define EXYNOS4_I2CHDMI_OFFSET 0x038E0000 /* I2C for HDMI */
|
||||
#define EXYNOS4_SPI0_OFFSET 0x03920000 /* Serial Peripheral Interface0 */
|
||||
#define EXYNOS4_SPI1_OFFSET 0x03930000 /* Serial Peripheral Interface0 */
|
||||
#define EXYNOS4_SPI2_OFFSET 0x03940000 /* Serial Peripheral Interface0 */
|
||||
#define EXYNOS4_I2S1_OFFSET 0x03960000 /* sound */
|
||||
#define EXYNOS4_I2S2_OFFSET 0x03970000 /* sound */
|
||||
#define EXYNOS4_PCM1_OFFSET 0x03980000 /* sound */
|
||||
#define EXYNOS4_PCM2_OFFSET 0x03990000 /* sound */
|
||||
#define EXYNOS4_AC97_OFFSET 0x039A0000 /* AC97 audio codec sound */
|
||||
#define EXYNOS4_SPDIF_OFFSET 0x039B0000 /* SPDIF sound */
|
||||
#define EXYNOS4_PWMTIMER_OFFSET 0x039D0000
|
||||
|
||||
/* AUDIOCORE */
|
||||
#define EXYNOS4_AUDIOCORE_OFFSET 0x04000000 /* on 1Mb L1 chunk */
|
||||
#define EXYNOS4_AUDIOCORE_VBASE (EXYNOS_CORE_VBASE + EXYNOS4_AUDIOCORE_OFFSET)
|
||||
#define EXYNOS4_AUDIOCORE_PBASE 0x03800000 /* Audio SFR */
|
||||
#define EXYNOS4_AUDIOCORE_SIZE 0x00100000
|
||||
|
||||
#define EXYNOS4_GPIO_I2S0_OFFSET (EXYNOS4_AUDIOCORE_OFFSET + 0x00060000)
|
||||
|
||||
/* used Exynos4 USB PHY registers */
|
||||
#define USB_PHYPWR 0x00
|
||||
#define PHYPWR_FORCE_SUSPEND __BIT(1)
|
||||
#define PHYPWR_ANALOG_POWERDOWN __BIT(3)
|
||||
#define PHYPWR_OTG_DISABLE __BIT(4)
|
||||
#define PHYPWR_SLEEP_PHY0 __BIT(5)
|
||||
#define PHYPWR_NORMAL_MASK 0x19
|
||||
#define PHYPWR_NORMAL_MASK_PHY0 (__BITS(3,3) | 1)
|
||||
#define PHYPWR_NORMAL_MASK_PHY1 __BITS(6,3)
|
||||
#define PHYPWR_NORMAL_MASK_HSIC0 __BITS(9,3)
|
||||
#define PHYPWR_NORMAL_MASK_HSIC1 __BITS(12,3)
|
||||
#define USB_PHYCLK 0x04 /* holds FSEL_CLKSEL_ */
|
||||
#define USB_RSTCON 0x08
|
||||
#define RSTCON_SWRST __BIT(0)
|
||||
#define RSTCON_HLINK_RWRST __BIT(1)
|
||||
#define RSTCON_DEVPHYLINK_SWRST __BIT(2)
|
||||
#define RSTCON_DEVPHY_SWRST __BITS(0,3)
|
||||
#define RSTCON_HOSTPHY_SWRST __BITS(3,4)
|
||||
#define RSTCON_HOSTPHYLINK_SWRST __BITS(7,4)
|
||||
|
||||
|
||||
#endif /* _ARM_SAMSUNG_EXYNOS4_REG_H_ */
|
||||
|
||||
@ -1,255 +0,0 @@
|
||||
/* $NetBSD: exynos5_loc.c,v 1.13 2015/12/05 13:32:27 jmcneill Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 2014 The NetBSD Foundation, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This code is derived from software contributed to The NetBSD Foundation
|
||||
* by Nick Hudson
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
|
||||
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <arm/samsung/exynos_io.h>
|
||||
#include <arm/samsung/exynos_intr.h>
|
||||
|
||||
#include <arm/samsung/exynos5_reg.h>
|
||||
|
||||
#define IRQ_RP_TIMER IRQ_SPI(127)
|
||||
#define IRQ_CAM_B IRQ_SPI(126)
|
||||
#define IRQ_CAM_A IRQ_SPI(125)
|
||||
#define IRQ_MDMA1 IRQ_SPI(124)
|
||||
#define IRQ_MCT_L1 IRQ_SPI(121)
|
||||
#define IRQ_MCT_L0 IRQ_SPI(120)
|
||||
#define IRQ_G3D_IRQMMU IRQ_SPI(119)
|
||||
#define IRQ_G3D_IRQJOB IRQ_SPI(118)
|
||||
#define IRQ_G3D_IRQGPU IRQ_SPI(117)
|
||||
#define IRQ_SATA IRQ_SPI(115)
|
||||
#define IRQ_CEC IRQ_SPI(114)
|
||||
#define IRQ_DP1_1 IRQ_SPI(113)
|
||||
#define IRQ_INTFEEDCTRL_SSS IRQ_SPI(112)
|
||||
#define IRQ_PMU IRQ_SPI(111)
|
||||
#define IRQ_CAM_C IRQ_SPI(110)
|
||||
#define IRQ_SATAPMEREQ IRQ_SPI(109)
|
||||
#define IRQ_SATAPHY IRQ_SPI(108)
|
||||
#define IRQ_ADC0 IRQ_SPI(106)
|
||||
#define IRQ_SPDIF IRQ_SPI(105)
|
||||
#define IRQ_PCM2 IRQ_SPI(104)
|
||||
#define IRQ_PCM1 IRQ_SPI(103)
|
||||
#define IRQ_PCM0 IRQ_SPI(102)
|
||||
#define IRQ_AC97 IRQ_SPI(101)
|
||||
#define IRQ_I2S2 IRQ_SPI(100)
|
||||
#define IRQ_I2S1 IRQ_SPI(99)
|
||||
#define IRQ_I2S0 IRQ_SPI(98)
|
||||
#define IRQ_AUDIO_SS IRQ_SPI(97)
|
||||
#define IRQ_MFC IRQ_SPI(96)
|
||||
#define IRQ_HDMI IRQ_SPI(95)
|
||||
#define IRQ_MIXER IRQ_SPI(94)
|
||||
#define IRQ_EFNFCON_1 IRQ_SPI(93)
|
||||
#define IRQ_EFNFCON_0 IRQ_SPI(92)
|
||||
#define IRQ_G2D IRQ_SPI(91)
|
||||
#define IRQ_EFNFCON_DMA IRQ_SPI(90)
|
||||
#define IRQ_JPEG IRQ_SPI(89)
|
||||
#define IRQ_GSCL3 IRQ_SPI(88)
|
||||
#define IRQ_GSCL2 IRQ_SPI(87)
|
||||
#define IRQ_GSCL1 IRQ_SPI(86)
|
||||
#define IRQ_GSCL0 IRQ_SPI(85)
|
||||
#define IRQ_ROTATOR IRQ_SPI(84)
|
||||
#define IRQ_WDT_IOP IRQ_SPI(83)
|
||||
#define IRQ_MIPI_DSI_4LANE IRQ_SPI(82)
|
||||
#define IRQ_EFNFCON_DMA_ABORT IRQ_SPI(81)
|
||||
#define IRQ_MIPI_CSI_B IRQ_SPI(80)
|
||||
#define IRQ_MIPI_CSI_A IRQ_SPI(79)
|
||||
#define IRQ_SDMMC3 IRQ_SPI(78)
|
||||
#define IRQ_SDMMC2 IRQ_SPI(77)
|
||||
#define IRQ_SDMMC1 IRQ_SPI(76)
|
||||
#define IRQ_SDMMC0 IRQ_SPI(75)
|
||||
#define IRQ_USBOTG IRQ_SPI(74)
|
||||
#define IRQ_MIPI_HSI IRQ_SPI(73)
|
||||
#define IRQ_USB_DRD30 IRQ_SPI(72)
|
||||
#define IRQ_USB_HOST20 IRQ_SPI(71)
|
||||
#define IRQ_SPI2 IRQ_SPI(70)
|
||||
#define IRQ_SPI1 IRQ_SPI(69)
|
||||
#define IRQ_SPI0 IRQ_SPI(68)
|
||||
#define IRQ_CPU_NFIQ_1 IRQ_SPI(67)
|
||||
#define IRQ_CPU_NFIQ_0 IRQ_SPI(66)
|
||||
#define IRQ_TMU IRQ_SPI(65)
|
||||
#define IRQ_HDMI_I2C IRQ_SPI(64)
|
||||
#define IRQ_I2C7 IRQ_SPI(63)
|
||||
#define IRQ_I2C6 IRQ_SPI(62)
|
||||
#define IRQ_I2C5 IRQ_SPI(61)
|
||||
#define IRQ_I2C4 IRQ_SPI(60)
|
||||
#define IRQ_I2C3_USI3 IRQ_SPI(59)
|
||||
#define IRQ_I2C2_USI2 IRQ_SPI(58)
|
||||
#define IRQ_I2C1_USI1 IRQ_SPI(57)
|
||||
#define IRQ_I2C0_USI0 IRQ_SPI(56)
|
||||
#define IRQ_MONOCNT IRQ_SPI(55)
|
||||
#define IRQ_UART3 IRQ_SPI(54)
|
||||
#define IRQ_UART2 IRQ_SPI(53)
|
||||
#define IRQ_UART1 IRQ_SPI(52)
|
||||
#define IRQ_UART0 IRQ_SPI(51)
|
||||
#define IRQ_GPIO_C2C IRQ_SPI(50)
|
||||
#define IRQ_GPIO IRQ_SPI(47)
|
||||
#define IRQ_GPIO_LB IRQ_SPI(46)
|
||||
#define IRQ_GPIO_RT IRQ_SPI(45)
|
||||
#define IRQ_RTC_TIC IRQ_SPI(44)
|
||||
#define IRQ_RTC_ALARM IRQ_SPI(43)
|
||||
#define IRQ_WDT IRQ_SPI(42)
|
||||
#define IRQ_RTIC IRQ_SPI(41)
|
||||
#define IRQ_TIMER4 IRQ_SPI(40)
|
||||
#define IRQ_TIMER3 IRQ_SPI(39)
|
||||
#define IRQ_TIMER2 IRQ_SPI(38)
|
||||
#define IRQ_TIMER1 IRQ_SPI(37)
|
||||
#define IRQ_TIMER0 IRQ_SPI(36)
|
||||
#define IRQ_PDMA1 IRQ_SPI(35)
|
||||
#define IRQ_PDMA0 IRQ_SPI(34)
|
||||
#define IRQ_MDMA0_CORE IRQ_SPI(33)
|
||||
|
||||
#define IRQ_SYSMMU_DRCISP_1 EXYNOS_COMBINERIRQ(11, 7)
|
||||
#define IRQ_SYSMMU_ODC_1 EXYNOS_COMBINERIRQ(11, 1)
|
||||
#define IRQ_SYSMMU_ODC_0 EXYNOS_COMBINERIRQ(11, 0)
|
||||
|
||||
#define IRQ_SYSMMU_ISP_1 EXYNOS_COMBINERIRQ(10, 7)
|
||||
#define IRQ_SYSMMU_ISP_0 EXYNOS_COMBINERIRQ(10, 6)
|
||||
#define IRQ_SYSMMU_DIS0_1 EXYNOS_COMBINERIRQ(10, 5)
|
||||
#define IRQ_SYSMMU_DIS0_0 EXYNOS_COMBINERIRQ(10, 4)
|
||||
#define IRQ_DP1 EXYNOS_COMBINERIRQ(10, 3)
|
||||
|
||||
#define IRQ_SYSMMU_DIS1_1 EXYNOS_COMBINERIRQ(9, 5)
|
||||
#define IRQ_SYSMMU_DIS1_0 EXYNOS_COMBINERIRQ(9, 4)
|
||||
|
||||
#define IRQ_SYSMMU_MFCL_1 EXYNOS_COMBINERIRQ(8, 6)
|
||||
#define IRQ_SYSMMU_MFCL_0 EXYNOS_COMBINERIRQ(8, 5)
|
||||
|
||||
#define IRQ_SYSMMU_TV_M0_1 EXYNOS_COMBINERIRQ(7, 5)
|
||||
#define IRQ_SYSMMU_TV_M0_0 EXYNOS_COMBINERIRQ(7, 4)
|
||||
#define IRQ_SYSMMU_MDMA1_1 EXYNOS_COMBINERIRQ(7, 3)
|
||||
#define IRQ_SYSMMU_MDMA1_0 EXYNOS_COMBINERIRQ(7, 2)
|
||||
#define IRQ_SYSMMU_MDMA0_1 EXYNOS_COMBINERIRQ(7, 1)
|
||||
#define IRQ_SYSMMU_MDMA0_0 EXYNOS_COMBINERIRQ(7, 0)
|
||||
|
||||
#define IRQ_SYSMMU_SSS_1 EXYNOS_COMBINERIRQ(6, 7)
|
||||
#define IRQ_SYSMMU_SSS_0 EXYNOS_COMBINERIRQ(6, 6)
|
||||
#define IRQ_SYSMMU_RTIC_1 EXYNOS_COMBINERIRQ(6, 5)
|
||||
#define IRQ_SYSMMU_RTIC_0 EXYNOS_COMBINERIRQ(6, 4)
|
||||
#define IRQ_SYSMMU_MFCR_1 EXYNOS_COMBINERIRQ(6, 3)
|
||||
#define IRQ_SYSMMU_MFCR_0 EXYNOS_COMBINERIRQ(6, 2)
|
||||
#define IRQ_SYSMMU_ARM_1 EXYNOS_COMBINERIRQ(6, 1)
|
||||
|
||||
#define IRQ_SYSMMU_ARM_0 EXYNOS_COMBINERIRQ(5, 0)
|
||||
#define IRQ_SYSMMU_3DNR_1 EXYNOS_COMBINERIRQ(5, 7)
|
||||
#define IRQ_SYSMMU_3DNR_0 EXYNOS_COMBINERIRQ(5, 6)
|
||||
#define IRQ_SYSMMU_MCUISP_1 EXYNOS_COMBINERIRQ(5, 5)
|
||||
#define IRQ_SYSMMU_MCUISP_0 EXYNOS_COMBINERIRQ(5, 4)
|
||||
#define IRQ_SYSMMU_SCALERCISP_1 EXYNOS_COMBINERIRQ(5, 3)
|
||||
#define IRQ_SYSMMU_SCALERCISP_0 EXYNOS_COMBINERIRQ(5, 2)
|
||||
#define IRQ_SYSMMU_FDISP_1 EXYNOS_COMBINERIRQ(5, 1)
|
||||
#define IRQ_SYSMMU_FDISP_0 EXYNOS_COMBINERIRQ(5, 0)
|
||||
|
||||
#define IRQ_MCUIOP_CTIIRQ EXYNOS_COMBINERIRQ(4, 7)
|
||||
#define IRQ_MCUIOP_PMUIRQ EXYNOS_COMBINERIRQ(4, 6)
|
||||
#define IRQ_MCUISP_CTIIRQ EXYNOS_COMBINERIRQ(4, 5)
|
||||
#define IRQ_MCUISP_PMUIRQ EXYNOS_COMBINERIRQ(4, 4)
|
||||
#define IRQ_SYSMMU_JPEGX_1 EXYNOS_COMBINERIRQ(4, 3)
|
||||
#define IRQ_SYSMMU_JPEGX_0 EXYNOS_COMBINERIRQ(4, 2)
|
||||
#define IRQ_SYSMMU_ROTATOR_1 EXYNOS_COMBINERIRQ(4, 1)
|
||||
#define IRQ_SYSMMU_ROTATOR_0 EXYNOS_COMBINERIRQ(4, 0)
|
||||
|
||||
#define IRQ_SYSMMU_SCALERPISP_1 EXYNOS_COMBINERIRQ(3, 7)
|
||||
#define IRQ_SYSMMU_SCALERPISP_0 EXYNOS_COMBINERIRQ(3, 6)
|
||||
#define IRQ_SYSMMU_FIMC_LITE0_1 EXYNOS_COMBINERIRQ(3, 5)
|
||||
#define IRQ_SYSMMU_FIMC_LITE0_0 EXYNOS_COMBINERIRQ(3, 4)
|
||||
#define IRQ_SYSMMU_DISP1_M0_1 EXYNOS_COMBINERIRQ(3, 3)
|
||||
#define IRQ_SYSMMU_DISP1_M0_0 EXYNOS_COMBINERIRQ(3, 2)
|
||||
#define IRQ_SYSMMU_FIMC_LITE2_1 EXYNOS_COMBINERIRQ(3, 1)
|
||||
#define IRQ_SYSMMU_FIMC_LITE2_0 EXYNOS_COMBINERIRQ(3, 0)
|
||||
|
||||
#define IRQ_SYSMMU_GSCL3_1 EXYNOS_COMBINERIRQ(2, 7)
|
||||
#define IRQ_SYSMMU_GSCL3_0 EXYNOS_COMBINERIRQ(2, 6)
|
||||
#define IRQ_SYSMMU_GSCL2_1 EXYNOS_COMBINERIRQ(2, 5)
|
||||
#define IRQ_SYSMMU_GSCL2_0 EXYNOS_COMBINERIRQ(2, 4)
|
||||
#define IRQ_SYSMMU_GSCL1_1 EXYNOS_COMBINERIRQ(2, 3)
|
||||
#define IRQ_SYSMMU_GSCL1_0 EXYNOS_COMBINERIRQ(2, 2)
|
||||
#define IRQ_SYSMMU_GSCL0_1 EXYNOS_COMBINERIRQ(2, 1)
|
||||
#define IRQ_SYSMMU_GSCL0_0 EXYNOS_COMBINERIRQ(2, 0)
|
||||
|
||||
#define IRQ_CPU_NCNTVIRQ_0 EXYNOS_COMBINERIRQ(1, 7)
|
||||
#define IRQ_CPU_NCNTPSIRQ_0 EXYNOS_COMBINERIRQ(1, 6)
|
||||
#define IRQ_CPU_NCNTPSNIRQ_0 EXYNOS_COMBINERIRQ(1, 5)
|
||||
#define IRQ_CPU_NCNTHPIRQ_0 EXYNOS_COMBINERIRQ(1, 4)
|
||||
#define IRQ_CPU_NCTIIRQ_0 EXYNOS_COMBINERIRQ(1, 3)
|
||||
#define IRQ_CPU_NPMUIRQ_0 EXYNOS_COMBINERIRQ(1, 2)
|
||||
#define IRQ_CPU_PARITYFAILSCU_0 EXYNOS_COMBINERIRQ(1, 1)
|
||||
#define IRQ_CPU_PARITYFAIL0 EXYNOS_COMBINERIRQ(1, 0)
|
||||
|
||||
#define IRQ_TZASC_XR1BXW EXYNOS_COMBINERIRQ(0, 7)
|
||||
#define IRQ_TZASC_XR1BXR EXYNOS_COMBINERIRQ(0, 6)
|
||||
#define IRQ_TZASC_XLBXW EXYNOS_COMBINERIRQ(0, 5)
|
||||
#define IRQ_TZASC_XLBXR EXYNOS_COMBINERIRQ(0, 4)
|
||||
#define IRQ_TZASC_DRBXW EXYNOS_COMBINERIRQ(0, 3)
|
||||
#define IRQ_TZASC_DRBXR EXYNOS_COMBINERIRQ(0, 2)
|
||||
#define IRQ_TZASC_CBXW EXYNOS_COMBINERIRQ(0, 1)
|
||||
#define IRQ_TZASC_CBXR EXYNOS_COMBINERIRQ(0, 0)
|
||||
|
||||
|
||||
#define OFFANDSIZE(p,n) \
|
||||
EXYNOS5##p##_##n##_OFFSET, 0x10000
|
||||
|
||||
static const struct exyo_locators exynos5_locators[] = {
|
||||
{ "exy5422clk", OFFANDSIZE(,CMU_CORE_PART), NOPORT, NOINTR, 0 },
|
||||
{ "exyogpio", 0, 0, NOPORT, NOINTR, 0 },
|
||||
{ "exyoiic", 0, 0, NOPORT, NOINTR, 0 },
|
||||
{ "exyowdt", OFFANDSIZE(,WDT), NOPORT, IRQ_WDT, 0 },
|
||||
{ "sscom", OFFANDSIZE(,UART0), 0, IRQ_UART0, 0 },
|
||||
{ "sscom", OFFANDSIZE(,UART1), 1, IRQ_UART1, 0 },
|
||||
{ "sscom", OFFANDSIZE(,UART2), 2, IRQ_UART2, 0 },
|
||||
{ "sscom", OFFANDSIZE(,UART3), 3, IRQ_UART3, 0 },
|
||||
{ "exyousb", OFFANDSIZE(,USB2HOST), NOPORT, IRQ_USB_HOST20, 0 },
|
||||
};
|
||||
|
||||
const struct exyo_locinfo exynos5_locinfo = {
|
||||
.locators = exynos5_locators,
|
||||
.nlocators = __arraycount(exynos5_locators)
|
||||
};
|
||||
|
||||
|
||||
/* flag signal the use of gpio */
|
||||
static const struct exyo_locators exynos5_i2c_locators[] = {
|
||||
/* busname, sdabit, slcbit, func */
|
||||
{ "iic0", OFFANDSIZE(,I2C0), 0, IRQ_I2C0_USI0, 1 , "GPB3", 0, 1, 2 },
|
||||
{ "iic1", OFFANDSIZE(,I2C1), 1, IRQ_I2C1_USI1, 1 , "GPB3", 2, 3, 2 },
|
||||
{ "iic2", OFFANDSIZE(,I2C2), 2, IRQ_I2C2_USI2, 1 , "GPA0", 6, 7, 3 },
|
||||
{ "iic3", OFFANDSIZE(,I2C3), 3, IRQ_I2C3_USI3, 1 , "GPA1", 2, 3, 3 },
|
||||
{ "iic4", OFFANDSIZE(,I2C4), 4, IRQ_I2C4, 1 , "GPA2", 0, 1, 3 },
|
||||
{ "iic5", OFFANDSIZE(,I2C5), 5, IRQ_I2C5, 1 , "GPA2", 2, 3, 3 },
|
||||
{ "iic6", OFFANDSIZE(,I2C6), 6, IRQ_I2C6, 1 , "GPB1", 3, 4, 4 },
|
||||
{ "iic7", OFFANDSIZE(,I2C7), 7, IRQ_I2C7, 1 , "GPB2", 2, 3, 3 },
|
||||
{ "iic8", OFFANDSIZE(,I2CHDMI), 8, IRQ_HDMI_I2C, 0 , "", 0, 0, 0 },
|
||||
};
|
||||
|
||||
|
||||
const struct exyo_locinfo exynos5_i2c_locinfo = {
|
||||
.locators = exynos5_i2c_locators,
|
||||
.nlocators = __arraycount(exynos5_i2c_locators)
|
||||
};
|
||||
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: exynos_chipid.c,v 1.1 2015/12/21 00:52:50 marty Exp $ */
|
||||
/* $NetBSD: exynos_chipid.c,v 1.2 2015/12/21 04:58:50 marty Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 2015 The NetBSD Foundation, Inc.
|
||||
@ -34,7 +34,7 @@
|
||||
#include "gpio.h"
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__KERNEL_RCSID(1, "$NetBSD: exynos_chipid.c,v 1.1 2015/12/21 00:52:50 marty Exp $");
|
||||
__KERNEL_RCSID(1, "$NetBSD: exynos_chipid.c,v 1.2 2015/12/21 04:58:50 marty Exp $");
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/bus.h>
|
||||
@ -47,7 +47,6 @@ __KERNEL_RCSID(1, "$NetBSD: exynos_chipid.c,v 1.1 2015/12/21 00:52:50 marty Exp
|
||||
#include <dev/gpio/gpiovar.h>
|
||||
|
||||
#include <arm/samsung/exynos_reg.h>
|
||||
#include <arm/samsung/exynos_io.h>
|
||||
#include <arm/samsung/exynos_intr.h>
|
||||
|
||||
#include <dev/fdt/fdtvar.h>
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: exynos_combiner.c,v 1.1 2015/12/21 00:52:50 marty Exp $ */
|
||||
/* $NetBSD: exynos_combiner.c,v 1.2 2015/12/21 04:58:50 marty Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 2015 The NetBSD Foundation, Inc.
|
||||
@ -34,7 +34,7 @@
|
||||
#include "gpio.h"
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__KERNEL_RCSID(1, "$NetBSD: exynos_combiner.c,v 1.1 2015/12/21 00:52:50 marty Exp $");
|
||||
__KERNEL_RCSID(1, "$NetBSD: exynos_combiner.c,v 1.2 2015/12/21 04:58:50 marty Exp $");
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/bus.h>
|
||||
@ -46,7 +46,6 @@ __KERNEL_RCSID(1, "$NetBSD: exynos_combiner.c,v 1.1 2015/12/21 00:52:50 marty Ex
|
||||
#include <arm/cortex/gic_intr.h>
|
||||
|
||||
#include <arm/samsung/exynos_reg.h>
|
||||
#include <arm/samsung/exynos_io.h>
|
||||
#include <arm/samsung/exynos_intr.h>
|
||||
|
||||
#include <dev/fdt/fdtvar.h>
|
||||
|
||||
@ -1,85 +0,0 @@
|
||||
/* $NetBSD: exynos_dma.c,v 1.1 2014/04/29 16:47:10 reinoud Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 2012 The NetBSD Foundation, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This code is derived from software contributed to The NetBSD Foundation
|
||||
* by Nick Hudson
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
|
||||
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "opt_exynos.h"
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__KERNEL_RCSID(0, "$NetBSD: exynos_dma.c,v 1.1 2014/04/29 16:47:10 reinoud Exp $");
|
||||
|
||||
#define _ARM32_BUS_DMA_PRIVATE
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/bus.h>
|
||||
|
||||
#include <arm/samsung/exynos_reg.h>
|
||||
#include <arm/samsung/exynos_var.h>
|
||||
|
||||
struct arm32_bus_dma_tag exynos_bus_dma_tag = {
|
||||
_BUS_DMAMAP_FUNCS,
|
||||
_BUS_DMAMEM_FUNCS,
|
||||
_BUS_DMATAG_FUNCS,
|
||||
};
|
||||
|
||||
struct arm32_dma_range exynos_coherent_dma_ranges[1] = {
|
||||
[0] = {
|
||||
.dr_sysbase = 0, /* filled in */
|
||||
.dr_busbase = 0, /* filled in */
|
||||
.dr_flags = _BUS_DMAMAP_COHERENT,
|
||||
},
|
||||
};
|
||||
|
||||
struct arm32_bus_dma_tag exynos_coherent_bus_dma_tag = {
|
||||
._ranges = exynos_coherent_dma_ranges,
|
||||
._nranges = __arraycount(exynos_coherent_dma_ranges),
|
||||
_BUS_DMAMAP_FUNCS,
|
||||
_BUS_DMAMEM_FUNCS,
|
||||
_BUS_DMATAG_FUNCS,
|
||||
};
|
||||
|
||||
|
||||
#ifndef EXYNOS4
|
||||
# define EXYNOS4_SDRAM_PBASE 0
|
||||
#endif
|
||||
#ifndef EXYNOS5
|
||||
# define EXYNOS5_SDRAM_PBASE 0
|
||||
#endif
|
||||
void
|
||||
exynos_dma_bootstrap(psize_t memsize)
|
||||
{
|
||||
bus_addr_t dram_base = IS_EXYNOS4_P() ?
|
||||
EXYNOS4_SDRAM_PBASE : EXYNOS5_SDRAM_PBASE;
|
||||
|
||||
KASSERT(dram_base);
|
||||
exynos_coherent_dma_ranges[0].dr_sysbase = dram_base;
|
||||
exynos_coherent_dma_ranges[0].dr_busbase = dram_base;
|
||||
exynos_coherent_dma_ranges[0].dr_len = memsize;
|
||||
}
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: exynos_gpio.c,v 1.14 2015/12/19 21:42:31 marty Exp $ */
|
||||
/* $NetBSD: exynos_gpio.c,v 1.15 2015/12/21 04:58:50 marty Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 2014 The NetBSD Foundation, Inc.
|
||||
@ -34,7 +34,7 @@
|
||||
#include "gpio.h"
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__KERNEL_RCSID(1, "$NetBSD: exynos_gpio.c,v 1.14 2015/12/19 21:42:31 marty Exp $");
|
||||
__KERNEL_RCSID(1, "$NetBSD: exynos_gpio.c,v 1.15 2015/12/21 04:58:50 marty Exp $");
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/bus.h>
|
||||
@ -47,7 +47,7 @@ __KERNEL_RCSID(1, "$NetBSD: exynos_gpio.c,v 1.14 2015/12/19 21:42:31 marty Exp $
|
||||
#include <dev/gpio/gpiovar.h>
|
||||
|
||||
#include <arm/samsung/exynos_reg.h>
|
||||
#include <arm/samsung/exynos_io.h>
|
||||
#include <arm/samsung/exynos_var.h>
|
||||
#include <arm/samsung/exynos_intr.h>
|
||||
#include <arm/samsung/exynos_pinctrl.h>
|
||||
|
||||
@ -133,7 +133,7 @@ static void
|
||||
exynos_gpio_update_cfg_regs(struct exynos_gpio_bank *bank,
|
||||
const struct exynos_gpio_pin_cfg *ncfg)
|
||||
{
|
||||
bus_space_tag_t bst = &exynos_bs_tag;
|
||||
bus_space_tag_t bst = &armv7_generic_bs_tag;
|
||||
|
||||
if (bank->bank_cfg.cfg != ncfg->cfg) {
|
||||
bus_space_write_4(bst, bank->bank_bsh,
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: exynos_i2c.c,v 1.5 2015/12/21 00:52:50 marty Exp $ */
|
||||
/* $NetBSD: exynos_i2c.c,v 1.6 2015/12/21 04:58:50 marty Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2014 The NetBSD Foundation, Inc.
|
||||
@ -35,7 +35,7 @@
|
||||
#include "exynos_iic.h"
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__KERNEL_RCSID(0, "$NetBSD: exynos_i2c.c,v 1.5 2015/12/21 00:52:50 marty Exp $");
|
||||
__KERNEL_RCSID(0, "$NetBSD: exynos_i2c.c,v 1.6 2015/12/21 04:58:50 marty Exp $");
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/bus.h>
|
||||
@ -45,7 +45,6 @@ __KERNEL_RCSID(0, "$NetBSD: exynos_i2c.c,v 1.5 2015/12/21 00:52:50 marty Exp $")
|
||||
#include <sys/kmem.h>
|
||||
|
||||
#include <arm/samsung/exynos_reg.h>
|
||||
#include <arm/samsung/exynos_io.h>
|
||||
#include <arm/samsung/exynos_intr.h>
|
||||
|
||||
#include <sys/gpio.h>
|
||||
|
||||
@ -1,204 +0,0 @@
|
||||
/* $NetBSD: exynos_io.c,v 1.8 2014/09/05 08:01:05 skrll Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 2014 The NetBSD Foundation, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This code is derived from software contributed to The NetBSD Foundation
|
||||
* by Matt Thomas of 3am Software Foundry.
|
||||
*
|
||||
* This code is derived from software contributed to The NetBSD Foundation
|
||||
* by Reinoud Zandijk
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
|
||||
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "locators.h"
|
||||
#include "opt_exynos.h"
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__KERNEL_RCSID(1, "$NetBSD: exynos_io.c,v 1.8 2014/09/05 08:01:05 skrll Exp $");
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/bus.h>
|
||||
#include <sys/cpu.h>
|
||||
#include <sys/device.h>
|
||||
#include <sys/intr.h>
|
||||
#include <sys/systm.h>
|
||||
|
||||
#include <arm/locore.h>
|
||||
#include <arm/mainbus/mainbus.h>
|
||||
|
||||
#include <arm/samsung/exynos_io.h>
|
||||
|
||||
#if 0
|
||||
#include <arm/samsung/exynos_reg.h>
|
||||
#endif
|
||||
#include <arm/samsung/exynos_var.h>
|
||||
|
||||
|
||||
static int exyo_match(device_t, cfdata_t, void *);
|
||||
static void exyo_attach(device_t, device_t, void *);
|
||||
|
||||
static struct exyo_softc {
|
||||
device_t sc_dev;
|
||||
bus_space_tag_t sc_bst;
|
||||
bus_space_tag_t sc_a4x_bst;
|
||||
bus_space_handle_t sc_bsh;
|
||||
bus_dma_tag_t sc_dmat;
|
||||
bus_dma_tag_t sc_coherent_dmat;
|
||||
} exyo_sc;
|
||||
|
||||
CFATTACH_DECL_NEW(exyo_io, 0, exyo_match, exyo_attach, NULL, NULL);
|
||||
|
||||
/* there can only be one */
|
||||
static int
|
||||
exyo_match(device_t parent, cfdata_t cf, void *aux)
|
||||
{
|
||||
if (exyo_sc.sc_dev != NULL)
|
||||
return 0;
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
||||
static int
|
||||
exyo_print(void *aux, const char *pnp)
|
||||
{
|
||||
const struct exyo_attach_args * const exyo = aux;
|
||||
|
||||
if (exyo->exyo_loc.loc_port != EXYOCF_PORT_DEFAULT)
|
||||
aprint_normal(" port %d", exyo->exyo_loc.loc_port);
|
||||
|
||||
return QUIET;
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
exyo_device_register(device_t self, void *aux)
|
||||
{
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
exyo_device_register_post_config(device_t self, void *aux)
|
||||
{
|
||||
}
|
||||
|
||||
static int
|
||||
exyo_find(device_t parent, cfdata_t cf, const int *ldesc, void *aux)
|
||||
{
|
||||
const struct exyo_attach_args * const exyo = aux;
|
||||
const struct exyo_locators * const loc = &exyo->exyo_loc;
|
||||
const int port = cf->cf_loc[EXYOCF_PORT];
|
||||
|
||||
if (strcmp(cf->cf_name, loc->loc_name)
|
||||
|| (port != EXYOCF_PORT_DEFAULT && port != loc->loc_port))
|
||||
return 0;
|
||||
|
||||
return config_match(parent, cf, aux);
|
||||
}
|
||||
|
||||
|
||||
#if !defined(EXYNOS4) && !defined(EXYNOS5)
|
||||
#error Must define a SoC
|
||||
#endif
|
||||
static void
|
||||
exyo_attach(device_t parent, device_t self, void *aux)
|
||||
{
|
||||
const struct exyo_locators *l = NULL;
|
||||
struct exyo_softc * const sc = &exyo_sc;
|
||||
prop_dictionary_t dict = device_properties(self);
|
||||
size_t nl = 0;
|
||||
|
||||
sc->sc_dev = self;
|
||||
sc->sc_bst = &exynos_bs_tag;
|
||||
sc->sc_a4x_bst = &exynos_a4x_bs_tag;
|
||||
sc->sc_bsh = exynos_core_bsh;
|
||||
sc->sc_dmat = &exynos_bus_dma_tag;
|
||||
sc->sc_coherent_dmat = &exynos_coherent_bus_dma_tag;
|
||||
|
||||
const uint16_t product_id = EXYNOS_PRODUCT_ID(exynos_soc_id);
|
||||
aprint_naive(": Exynos %x\n", product_id);
|
||||
aprint_normal(": Exynos %x\n", product_id);
|
||||
|
||||
/* add sysctl nodes */
|
||||
exynos_sysctl_cpufreq_init();
|
||||
|
||||
/* add all children */
|
||||
#if defined(EXYNOS4)
|
||||
if (IS_EXYNOS4_P()) {
|
||||
l = exynos4_locinfo.locators;
|
||||
nl = exynos4_locinfo.nlocators;
|
||||
}
|
||||
#endif
|
||||
#if defined(EXYNOS5)
|
||||
if (IS_EXYNOS5_P()) {
|
||||
l = exynos5_locinfo.locators;
|
||||
nl = exynos5_locinfo.nlocators;
|
||||
}
|
||||
#endif
|
||||
KASSERT(l != NULL);
|
||||
KASSERT(nl > 0);
|
||||
|
||||
for (const struct exyo_locators *loc = l; loc < l + nl; loc++) {
|
||||
char prop_name[31];
|
||||
bool skip;
|
||||
|
||||
if (loc->loc_port == EXYOCF_PORT_DEFAULT) {
|
||||
snprintf(prop_name, sizeof(prop_name),
|
||||
"no-%s", loc->loc_name);
|
||||
} else {
|
||||
snprintf(prop_name, sizeof(prop_name),
|
||||
"no-%s-%d", loc->loc_name, loc->loc_port);
|
||||
}
|
||||
if (prop_dictionary_get_bool(dict, prop_name, &skip) && skip)
|
||||
continue;
|
||||
|
||||
struct exyo_attach_args exyo = {
|
||||
.exyo_loc = *loc,
|
||||
.exyo_core_bst = sc->sc_bst,
|
||||
.exyo_core_a4x_bst = sc->sc_a4x_bst,
|
||||
.exyo_core_bsh = sc->sc_bsh,
|
||||
.exyo_dmat = sc->sc_dmat,
|
||||
.exyo_coherent_dmat = sc->sc_coherent_dmat,
|
||||
};
|
||||
cfdata_t cf = config_search_ia(exyo_find,
|
||||
sc->sc_dev, "exyo", &exyo);
|
||||
if (cf == NULL) {
|
||||
#ifdef EXYO_REQUIRED
|
||||
if (loc->loc_flags & EXYO_REQUIRED)
|
||||
panic("%s: failed to find %s!", __func__,
|
||||
loc->loc_name);
|
||||
#endif
|
||||
if (loc->loc_port == EXYOCF_PORT_DEFAULT) {
|
||||
aprint_verbose_dev(self, "%s not found\n",
|
||||
loc->loc_name);
|
||||
} else {
|
||||
aprint_verbose_dev(self, "%s%d not found\n",
|
||||
loc->loc_name, loc->loc_port);
|
||||
}
|
||||
continue;
|
||||
}
|
||||
config_attach(sc->sc_dev, cf, &exyo, exyo_print);
|
||||
}
|
||||
}
|
||||
@ -1,57 +0,0 @@
|
||||
/* $NetBSD: exynos_io.h,v 1.6 2014/09/28 18:59:43 reinoud Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 2014 The NetBSD Foundation, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This code is derived from software contributed to The NetBSD Foundation
|
||||
* by Nick Hudson
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
|
||||
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _ARM_SAMSUMG_EXYNOS_IO_H_
|
||||
#define _ARM_SAMSUNG_EXYNOS_IO_H_
|
||||
|
||||
#include "opt_exynos.h"
|
||||
#include "locators.h"
|
||||
|
||||
#include <arm/samsung/exynos_var.h>
|
||||
|
||||
|
||||
struct exyo_locinfo {
|
||||
const struct exyo_locators *locators;
|
||||
size_t nlocators;
|
||||
};
|
||||
|
||||
extern const struct exyo_locinfo exynos4_locinfo;
|
||||
extern const struct exyo_locinfo exynos4_i2c_locinfo;
|
||||
extern const struct exyo_locinfo exynos5_locinfo;
|
||||
extern const struct exyo_locinfo exynos5_i2c_locinfo;
|
||||
|
||||
/* XXXNH needed? */
|
||||
#define NOPORT EXYOCF_PORT_DEFAULT
|
||||
#define NOINTR EXYOCF_INTR_DEFAULT
|
||||
#define EANY EXYO_ALL
|
||||
#define REQ EXYO_REQUIRED
|
||||
|
||||
#endif /* _ARM_SAMSUNG_EXYNOS_IO_H_ */
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: exynos_pinctrl.c,v 1.2 2015/12/21 00:54:35 marty Exp $ */
|
||||
/* $NetBSD: exynos_pinctrl.c,v 1.3 2015/12/21 04:58:50 marty Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 2015 The NetBSD Foundation, Inc.
|
||||
@ -34,7 +34,7 @@
|
||||
#include "gpio.h"
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__KERNEL_RCSID(1, "$NetBSD: exynos_pinctrl.c,v 1.2 2015/12/21 00:54:35 marty Exp $");
|
||||
__KERNEL_RCSID(1, "$NetBSD: exynos_pinctrl.c,v 1.3 2015/12/21 04:58:50 marty Exp $");
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/bus.h>
|
||||
@ -47,7 +47,7 @@ __KERNEL_RCSID(1, "$NetBSD: exynos_pinctrl.c,v 1.2 2015/12/21 00:54:35 marty Exp
|
||||
#include <dev/gpio/gpiovar.h>
|
||||
|
||||
#include <arm/samsung/exynos_reg.h>
|
||||
#include <arm/samsung/exynos_io.h>
|
||||
#include <arm/samsung/exynos_var.h>
|
||||
#include <arm/samsung/exynos_intr.h>
|
||||
#include <arm/samsung/exynos_pinctrl.h>
|
||||
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: exynos_rtc.c,v 1.1 2015/12/21 00:52:50 marty Exp $ */
|
||||
/* $NetBSD: exynos_rtc.c,v 1.2 2015/12/21 04:58:50 marty Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 2015 The NetBSD Foundation, Inc.
|
||||
@ -34,7 +34,7 @@
|
||||
#include "gpio.h"
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__KERNEL_RCSID(1, "$NetBSD: exynos_rtc.c,v 1.1 2015/12/21 00:52:50 marty Exp $");
|
||||
__KERNEL_RCSID(1, "$NetBSD: exynos_rtc.c,v 1.2 2015/12/21 04:58:50 marty Exp $");
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/bus.h>
|
||||
@ -47,7 +47,6 @@ __KERNEL_RCSID(1, "$NetBSD: exynos_rtc.c,v 1.1 2015/12/21 00:52:50 marty Exp $")
|
||||
#include <dev/clock_subr.h>
|
||||
|
||||
#include <arm/samsung/exynos_reg.h>
|
||||
#include <arm/samsung/exynos_io.h>
|
||||
#include <arm/samsung/exynos_intr.h>
|
||||
|
||||
#include <dev/fdt/fdtvar.h>
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: exynos_soc.c,v 1.30 2015/12/12 21:57:40 marty Exp $ */
|
||||
/* $NetBSD: exynos_soc.c,v 1.31 2015/12/21 04:58:50 marty Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 2014 The NetBSD Foundation, Inc.
|
||||
@ -34,7 +34,7 @@
|
||||
#define _ARM32_BUS_DMA_PRIVATE
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__KERNEL_RCSID(1, "$NetBSD: exynos_soc.c,v 1.30 2015/12/12 21:57:40 marty Exp $");
|
||||
__KERNEL_RCSID(1, "$NetBSD: exynos_soc.c,v 1.31 2015/12/21 04:58:50 marty Exp $");
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/bus.h>
|
||||
@ -343,7 +343,7 @@ exynos_get_cpufreq(void)
|
||||
uint32_t regval;
|
||||
uint32_t freq;
|
||||
|
||||
regval = bus_space_read_4(&exynos_bs_tag, exynos_cmu_apll_bsh,
|
||||
regval = bus_space_read_4(&armv7_generic_bs_tag, exynos_cmu_apll_bsh,
|
||||
PLL_CON0_OFFSET);
|
||||
freq = PLL_FREQ(EXYNOS_F_IN_FREQ, regval);
|
||||
|
||||
@ -369,7 +369,7 @@ exynos_set_cpufreq(const struct cpu_freq *freqreq)
|
||||
|
||||
/* enable PPL and write config */
|
||||
regval |= PLL_CON0_ENABLE;
|
||||
bus_space_write_4(&exynos_bs_tag, exynos_cmu_apll_bsh, PLL_CON0_OFFSET,
|
||||
bus_space_write_4(&armv7_generic_bs_tag, exynos_cmu_apll_bsh, PLL_CON0_OFFSET,
|
||||
regval);
|
||||
|
||||
/* update our cycle counter i.e. our CPU frequency for all CPUs */
|
||||
@ -443,7 +443,7 @@ sysctl_cpufreq_current(SYSCTLFN_ARGS)
|
||||
#ifdef VERBOSE_INIT_ARM
|
||||
#define DUMP_PLL(v, var) \
|
||||
reg = EXYNOS##v##_CMU_##var + PLL_CON0_OFFSET;\
|
||||
regval = bus_space_read_4(&exynos_bs_tag, exynos_cmu_bsh, reg); \
|
||||
regval = bus_space_read_4(&armv7_generic_bs_tag, exynos_cmu_bsh, reg); \
|
||||
freq = PLL_FREQ(EXYNOS_F_IN_FREQ, regval); \
|
||||
printf("%8s at %d Mhz\n", #var, freq/(1000*1000));
|
||||
|
||||
@ -553,14 +553,14 @@ exynos_bootstrap(vaddr_t iobase, vaddr_t uartbase)
|
||||
#endif
|
||||
|
||||
/* map in the exynos io registers */
|
||||
error = bus_space_map(&exynos_bs_tag, EXYNOS_CORE_PBASE,
|
||||
error = bus_space_map(&armv7_generic_bs_tag, EXYNOS_CORE_PBASE,
|
||||
core_size, 0, &exynos_core_bsh);
|
||||
if (error)
|
||||
panic("%s: failed to map in Exynos SFR registers: %d",
|
||||
__func__, error);
|
||||
KASSERT(exynos_core_bsh == iobase);
|
||||
|
||||
error = bus_space_map(&exynos_bs_tag, audiocore_pbase,
|
||||
error = bus_space_map(&armv7_generic_bs_tag, audiocore_pbase,
|
||||
audiocore_size, 0, &exynos_audiocore_bsh);
|
||||
if (error)
|
||||
panic("%s: failed to map in Exynos audio SFR registers: %d",
|
||||
@ -568,27 +568,27 @@ exynos_bootstrap(vaddr_t iobase, vaddr_t uartbase)
|
||||
KASSERT(exynos_audiocore_bsh == audiocore_vbase);
|
||||
|
||||
/* map in commonly used subregions and common used register banks */
|
||||
error = bus_space_subregion(&exynos_bs_tag, exynos_core_bsh,
|
||||
error = bus_space_subregion(&armv7_generic_bs_tag, exynos_core_bsh,
|
||||
exynos_wdt_offset, EXYNOS_BLOCK_SIZE, &exynos_wdt_bsh);
|
||||
if (error)
|
||||
panic("%s: failed to subregion wdt registers: %d",
|
||||
__func__, error);
|
||||
|
||||
error = bus_space_subregion(&exynos_bs_tag, exynos_core_bsh,
|
||||
error = bus_space_subregion(&armv7_generic_bs_tag, exynos_core_bsh,
|
||||
exynos_pmu_offset, EXYNOS_BLOCK_SIZE, &exynos_pmu_bsh);
|
||||
if (error)
|
||||
panic("%s: failed to subregion pmu registers: %d",
|
||||
__func__, error);
|
||||
|
||||
exynos_cmu_bsh = exynos_core_bsh;
|
||||
bus_space_subregion(&exynos_bs_tag, exynos_core_bsh,
|
||||
bus_space_subregion(&armv7_generic_bs_tag, exynos_core_bsh,
|
||||
exynos_sysreg_offset, EXYNOS_BLOCK_SIZE,
|
||||
&exynos_sysreg_bsh);
|
||||
if (error)
|
||||
panic("%s: failed to subregion sysreg registers: %d",
|
||||
__func__, error);
|
||||
|
||||
error = bus_space_subregion(&exynos_bs_tag, exynos_cmu_bsh,
|
||||
error = bus_space_subregion(&armv7_generic_bs_tag, exynos_cmu_bsh,
|
||||
exynos_cmu_apll_offset, 0xfff, &exynos_cmu_apll_bsh);
|
||||
if (error)
|
||||
panic("%s: failed to subregion cmu apll registers: %d",
|
||||
@ -613,7 +613,7 @@ exynos_device_register(device_t self, void *aux)
|
||||
* bus space used for the armcore registers (which armperiph uses).
|
||||
*/
|
||||
struct mainbus_attach_args * const mb = aux;
|
||||
mb->mb_iot = &exynos_bs_tag;
|
||||
mb->mb_iot = &armv7_generic_bs_tag;
|
||||
return;
|
||||
}
|
||||
if (device_is_a(self, "armgic")
|
||||
@ -666,10 +666,10 @@ exynos_device_register(device_t self, void *aux)
|
||||
* The global timer is dependent on the MCT running.
|
||||
*/
|
||||
bus_size_t o = EXYNOS5_MCT_OFFSET + MCT_G_TCON;
|
||||
uint32_t v = bus_space_read_4(&exynos_bs_tag, exynos_core_bsh,
|
||||
uint32_t v = bus_space_read_4(&armv7_generic_bs_tag, exynos_core_bsh,
|
||||
o);
|
||||
v |= G_TCON_START;
|
||||
bus_space_write_4(&exynos_bs_tag, exynos_core_bsh, o, v);
|
||||
bus_space_write_4(&armv7_generic_bs_tag, exynos_core_bsh, o, v);
|
||||
#endif
|
||||
/*
|
||||
* The frequencies of the timers are the reference
|
||||
@ -679,15 +679,12 @@ exynos_device_register(device_t self, void *aux)
|
||||
"frequency", EXYNOS_F_IN_FREQ);
|
||||
return;
|
||||
}
|
||||
|
||||
exyo_device_register(self, aux);
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
exynos_device_register_post_config(device_t self, void *aux)
|
||||
{
|
||||
exyo_device_register_post_config(self, aux);
|
||||
}
|
||||
|
||||
void
|
||||
@ -714,23 +711,23 @@ exynos_usb2_set_isolation(bool on)
|
||||
if (IS_EXYNOS5_P() || IS_EXYNOS4410_P()) {
|
||||
/* set usbhost mode */
|
||||
regval = on ? 0 : USB20_PHY_HOST_LINK_EN;
|
||||
bus_space_write_4(&exynos_bs_tag, exynos_sysreg_bsh,
|
||||
bus_space_write_4(&armv7_generic_bs_tag, exynos_sysreg_bsh,
|
||||
EXYNOS5_SYSREG_USB20_PHY_TYPE, regval);
|
||||
reg = EXYNOS_PMU_USBHOST_PHY_CTRL;
|
||||
}
|
||||
|
||||
/* do enable PHY */
|
||||
en_mask = PMU_PHY_ENABLE;
|
||||
regval = bus_space_read_4(&exynos_bs_tag, exynos_pmu_bsh, reg);
|
||||
regval = bus_space_read_4(&armv7_generic_bs_tag, exynos_pmu_bsh, reg);
|
||||
regval = on ? regval & ~en_mask : regval | en_mask;
|
||||
|
||||
bus_space_write_4(&exynos_bs_tag, exynos_pmu_bsh,
|
||||
bus_space_write_4(&armv7_generic_bs_tag, exynos_pmu_bsh,
|
||||
reg, regval);
|
||||
|
||||
if (IS_EXYNOS4X12_P()) {
|
||||
bus_space_write_4(&exynos_bs_tag, exynos_pmu_bsh,
|
||||
bus_space_write_4(&armv7_generic_bs_tag, exynos_pmu_bsh,
|
||||
EXYNOS_PMU_USB_HSIC_1_PHY_CTRL, regval);
|
||||
bus_space_write_4(&exynos_bs_tag, exynos_pmu_bsh,
|
||||
bus_space_write_4(&armv7_generic_bs_tag, exynos_pmu_bsh,
|
||||
EXYNOS_PMU_USB_HSIC_2_PHY_CTRL, regval);
|
||||
}
|
||||
}
|
||||
@ -744,50 +741,50 @@ exynos4_usb2phy_enable(bus_space_handle_t usb2phy_bsh)
|
||||
|
||||
/* write clock value */
|
||||
clkreg = FSEL_CLKSEL_24M;
|
||||
bus_space_write_4(&exynos_bs_tag, usb2phy_bsh,
|
||||
bus_space_write_4(&armv7_generic_bs_tag, usb2phy_bsh,
|
||||
USB_PHYCLK, clkreg);
|
||||
|
||||
/* set device and host to normal */
|
||||
phypwr = bus_space_read_4(&exynos_bs_tag, usb2phy_bsh,
|
||||
phypwr = bus_space_read_4(&armv7_generic_bs_tag, usb2phy_bsh,
|
||||
USB_PHYPWR);
|
||||
|
||||
/* enable analog, enable otg, unsleep phy0 (host) */
|
||||
phypwr &= ~PHYPWR_NORMAL_MASK_PHY0;
|
||||
bus_space_write_4(&exynos_bs_tag, usb2phy_bsh,
|
||||
bus_space_write_4(&armv7_generic_bs_tag, usb2phy_bsh,
|
||||
USB_PHYPWR, phypwr);
|
||||
|
||||
if (IS_EXYNOS4X12_P()) {
|
||||
/* enable hsic0 (host), enable hsic1 and phy1 (otg) */
|
||||
phypwr = bus_space_read_4(&exynos_bs_tag, usb2phy_bsh,
|
||||
phypwr = bus_space_read_4(&armv7_generic_bs_tag, usb2phy_bsh,
|
||||
USB_PHYPWR);
|
||||
phypwr &= ~(PHYPWR_NORMAL_MASK_HSIC0 |
|
||||
PHYPWR_NORMAL_MASK_HSIC1 |
|
||||
PHYPWR_NORMAL_MASK_PHY1);
|
||||
bus_space_write_4(&exynos_bs_tag, usb2phy_bsh,
|
||||
bus_space_write_4(&armv7_generic_bs_tag, usb2phy_bsh,
|
||||
USB_PHYPWR, phypwr);
|
||||
}
|
||||
|
||||
/* reset both phy and link of device */
|
||||
rstcon = bus_space_read_4(&exynos_bs_tag, usb2phy_bsh,
|
||||
rstcon = bus_space_read_4(&armv7_generic_bs_tag, usb2phy_bsh,
|
||||
USB_RSTCON);
|
||||
rstcon |= RSTCON_DEVPHY_SWRST;
|
||||
bus_space_write_4(&exynos_bs_tag, usb2phy_bsh,
|
||||
bus_space_write_4(&armv7_generic_bs_tag, usb2phy_bsh,
|
||||
USB_RSTCON, rstcon);
|
||||
DELAY(10000);
|
||||
rstcon &= ~RSTCON_DEVPHY_SWRST;
|
||||
bus_space_write_4(&exynos_bs_tag, usb2phy_bsh,
|
||||
bus_space_write_4(&armv7_generic_bs_tag, usb2phy_bsh,
|
||||
USB_RSTCON, rstcon);
|
||||
|
||||
if (IS_EXYNOS4X12_P()) {
|
||||
/* reset both phy and link of host */
|
||||
rstcon = bus_space_read_4(&exynos_bs_tag, usb2phy_bsh,
|
||||
rstcon = bus_space_read_4(&armv7_generic_bs_tag, usb2phy_bsh,
|
||||
USB_RSTCON);
|
||||
rstcon |= RSTCON_HOSTPHY_SWRST | RSTCON_HOSTPHYLINK_SWRST;
|
||||
bus_space_write_4(&exynos_bs_tag, usb2phy_bsh,
|
||||
bus_space_write_4(&armv7_generic_bs_tag, usb2phy_bsh,
|
||||
USB_RSTCON, rstcon);
|
||||
DELAY(10000);
|
||||
rstcon &= ~(RSTCON_HOSTPHY_SWRST | RSTCON_HOSTPHYLINK_SWRST);
|
||||
bus_space_write_4(&exynos_bs_tag, usb2phy_bsh,
|
||||
bus_space_write_4(&armv7_generic_bs_tag, usb2phy_bsh,
|
||||
USB_RSTCON, rstcon);
|
||||
}
|
||||
|
||||
@ -806,7 +803,7 @@ exynos5410_usb2phy_enable(bus_space_handle_t usb2phy_bsh)
|
||||
uint32_t ehcictrl, ohcictrl;
|
||||
|
||||
/* host configuration: */
|
||||
phyhost = bus_space_read_4(&exynos_bs_tag, usb2phy_bsh,
|
||||
phyhost = bus_space_read_4(&armv7_generic_bs_tag, usb2phy_bsh,
|
||||
USB_PHY_HOST_CTRL0);
|
||||
|
||||
/* host phy reference clock; assumption its 24 MHz now */
|
||||
@ -825,12 +822,12 @@ exynos5410_usb2phy_enable(bus_space_handle_t usb2phy_bsh)
|
||||
phyhost |= HOST_CTRL0_LINK_SWRST | HOST_CTRL0_UTMI_SWRST |
|
||||
HOST_CTRL0_COMMONON_N;
|
||||
/* do the reset */
|
||||
bus_space_write_4(&exynos_bs_tag, usb2phy_bsh, USB_PHY_HOST_CTRL0,
|
||||
bus_space_write_4(&armv7_generic_bs_tag, usb2phy_bsh, USB_PHY_HOST_CTRL0,
|
||||
phyhost);
|
||||
DELAY(10000);
|
||||
|
||||
phyhost &= ~(HOST_CTRL0_LINK_SWRST | HOST_CTRL0_UTMI_SWRST);
|
||||
bus_space_write_4(&exynos_bs_tag, usb2phy_bsh, USB_PHY_HOST_CTRL0,
|
||||
bus_space_write_4(&armv7_generic_bs_tag, usb2phy_bsh, USB_PHY_HOST_CTRL0,
|
||||
phyhost);
|
||||
|
||||
/* HSIC control */
|
||||
@ -839,22 +836,22 @@ exynos5410_usb2phy_enable(bus_space_handle_t usb2phy_bsh)
|
||||
__SHIFTIN(HSIC_CTRL_REFCLKSEL_DEFAULT, HSIC_CTRL_REFCLKSEL_MASK) |
|
||||
HSIC_CTRL_PHY_SWRST;
|
||||
|
||||
bus_space_write_4(&exynos_bs_tag, usb2phy_bsh, USB_PHY_HSIC_CTRL1,
|
||||
bus_space_write_4(&armv7_generic_bs_tag, usb2phy_bsh, USB_PHY_HSIC_CTRL1,
|
||||
phyhsic);
|
||||
bus_space_write_4(&exynos_bs_tag, usb2phy_bsh, USB_PHY_HSIC_CTRL2,
|
||||
bus_space_write_4(&armv7_generic_bs_tag, usb2phy_bsh, USB_PHY_HSIC_CTRL2,
|
||||
phyhsic);
|
||||
DELAY(10);
|
||||
|
||||
phyhsic &= ~HSIC_CTRL_PHY_SWRST;
|
||||
bus_space_write_4(&exynos_bs_tag, usb2phy_bsh, USB_PHY_HSIC_CTRL1,
|
||||
bus_space_write_4(&armv7_generic_bs_tag, usb2phy_bsh, USB_PHY_HSIC_CTRL1,
|
||||
phyhsic);
|
||||
bus_space_write_4(&exynos_bs_tag, usb2phy_bsh, USB_PHY_HSIC_CTRL2,
|
||||
bus_space_write_4(&armv7_generic_bs_tag, usb2phy_bsh, USB_PHY_HSIC_CTRL2,
|
||||
phyhsic);
|
||||
DELAY(80);
|
||||
|
||||
#if 0
|
||||
/* otg configuration: */
|
||||
phyotg = bus_space_read_4(&exynos_bs_tag, usb2phy_bsh,
|
||||
phyotg = bus_space_read_4(&armv7_generic_bs_tag, usb2phy_bsh,
|
||||
USB_PHY_OTG_SYS);
|
||||
|
||||
/* otg phy refrence clock: assumption its 24 Mhz now */
|
||||
@ -871,29 +868,29 @@ exynos5410_usb2phy_enable(bus_space_handle_t usb2phy_bsh)
|
||||
OTG_SYS_OTGDISABLE | OTG_SYS_REFCLKSEL_MASK;
|
||||
|
||||
/* do the reset */
|
||||
bus_space_write_4(&exynos_bs_tag, usb2phy_bsh,
|
||||
bus_space_write_4(&armv7_generic_bs_tag, usb2phy_bsh,
|
||||
USB_PHY_OTG_SYS, phyotg);
|
||||
DELAY(10000);
|
||||
phyotg &= ~(OTG_SYS_PHY0_SWRST | OTG_SYS_LINK_SWRST_UOTG |
|
||||
OTG_SYS_PHYLINK_SWRST);
|
||||
bus_space_write_4(&exynos_bs_tag, usb2phy_bsh,
|
||||
bus_space_write_4(&armv7_generic_bs_tag, usb2phy_bsh,
|
||||
USB_PHY_OTG_SYS, phyotg);
|
||||
#endif
|
||||
|
||||
/* enable EHCI DMA burst: */
|
||||
ehcictrl = bus_space_read_4(&exynos_bs_tag, usb2phy_bsh,
|
||||
ehcictrl = bus_space_read_4(&armv7_generic_bs_tag, usb2phy_bsh,
|
||||
USB_PHY_HOST_EHCICTRL);
|
||||
ehcictrl |= HOST_EHCICTRL_ENA_INCRXALIGN |
|
||||
HOST_EHCICTRL_ENA_INCR4 | HOST_EHCICTRL_ENA_INCR8 |
|
||||
HOST_EHCICTRL_ENA_INCR16;
|
||||
bus_space_write_4(&exynos_bs_tag, usb2phy_bsh,
|
||||
bus_space_write_4(&armv7_generic_bs_tag, usb2phy_bsh,
|
||||
USB_PHY_HOST_EHCICTRL, ehcictrl);
|
||||
|
||||
/* Set OHCI suspend */
|
||||
ohcictrl = bus_space_read_4(&exynos_bs_tag, usb2phy_bsh,
|
||||
ohcictrl = bus_space_read_4(&armv7_generic_bs_tag, usb2phy_bsh,
|
||||
USB_PHY_HOST_OHCICTRL);
|
||||
ohcictrl |= HOST_OHCICTRL_SUSPLGCY;
|
||||
bus_space_write_4(&exynos_bs_tag, usb2phy_bsh,
|
||||
bus_space_write_4(&armv7_generic_bs_tag, usb2phy_bsh,
|
||||
USB_PHY_HOST_OHCICTRL, ohcictrl);
|
||||
}
|
||||
|
||||
|
||||
@ -1,417 +0,0 @@
|
||||
/* $NetBSD: exynos_space.c,v 1.2 2015/02/25 13:52:42 joerg Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 2012 The NetBSD Foundation, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This code is derived from software contributed to The NetBSD Foundation
|
||||
* by Nick Hudson
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
|
||||
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__KERNEL_RCSID(0, "$NetBSD: exynos_space.c,v 1.2 2015/02/25 13:52:42 joerg Exp $");
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
|
||||
#include <uvm/uvm_extern.h>
|
||||
|
||||
#include <sys/bus.h>
|
||||
|
||||
/* Prototypes for all the bus_space structure functions */
|
||||
bs_protos(exynos);
|
||||
bs_protos(exynos_a4x);
|
||||
bs_protos(a4x);
|
||||
bs_protos(bs_notimpl);
|
||||
bs_protos(generic);
|
||||
bs_protos(generic_armv4);
|
||||
|
||||
#if __ARMEB__
|
||||
#define NSWAP(n) n ## _swap
|
||||
#else
|
||||
#define NSWAP(n) n
|
||||
#endif
|
||||
|
||||
struct bus_space exynos_bs_tag = {
|
||||
/* cookie */
|
||||
(void *) 0,
|
||||
|
||||
/* mapping/unmapping */
|
||||
exynos_bs_map,
|
||||
exynos_bs_unmap,
|
||||
exynos_bs_subregion,
|
||||
|
||||
/* allocation/deallocation */
|
||||
exynos_bs_alloc, /* not implemented */
|
||||
exynos_bs_free, /* not implemented */
|
||||
|
||||
/* get kernel virtual address */
|
||||
exynos_bs_vaddr,
|
||||
|
||||
/* mmap */
|
||||
exynos_bs_mmap,
|
||||
|
||||
/* barrier */
|
||||
exynos_bs_barrier,
|
||||
|
||||
/* read (single) */
|
||||
generic_bs_r_1,
|
||||
NSWAP(generic_armv4_bs_r_2),
|
||||
NSWAP(generic_bs_r_4),
|
||||
bs_notimpl_bs_r_8,
|
||||
|
||||
/* read multiple */
|
||||
generic_bs_rm_1,
|
||||
NSWAP(generic_armv4_bs_rm_2),
|
||||
NSWAP(generic_bs_rm_4),
|
||||
bs_notimpl_bs_rm_8,
|
||||
|
||||
/* read region */
|
||||
generic_bs_rr_1,
|
||||
NSWAP(generic_armv4_bs_rr_2),
|
||||
NSWAP(generic_bs_rr_4),
|
||||
bs_notimpl_bs_rr_8,
|
||||
|
||||
/* write (single) */
|
||||
generic_bs_w_1,
|
||||
NSWAP(generic_armv4_bs_w_2),
|
||||
NSWAP(generic_bs_w_4),
|
||||
bs_notimpl_bs_w_8,
|
||||
|
||||
/* write multiple */
|
||||
generic_bs_wm_1,
|
||||
NSWAP(generic_armv4_bs_wm_2),
|
||||
NSWAP(generic_bs_wm_4),
|
||||
bs_notimpl_bs_wm_8,
|
||||
|
||||
/* write region */
|
||||
generic_bs_wr_1,
|
||||
NSWAP(generic_armv4_bs_wr_2),
|
||||
NSWAP(generic_bs_wr_4),
|
||||
bs_notimpl_bs_wr_8,
|
||||
|
||||
/* set multiple */
|
||||
bs_notimpl_bs_sm_1,
|
||||
bs_notimpl_bs_sm_2,
|
||||
bs_notimpl_bs_sm_4,
|
||||
bs_notimpl_bs_sm_8,
|
||||
|
||||
/* set region */
|
||||
generic_bs_sr_1,
|
||||
NSWAP(generic_armv4_bs_sr_2),
|
||||
bs_notimpl_bs_sr_4,
|
||||
bs_notimpl_bs_sr_8,
|
||||
|
||||
/* copy */
|
||||
bs_notimpl_bs_c_1,
|
||||
generic_armv4_bs_c_2,
|
||||
bs_notimpl_bs_c_4,
|
||||
bs_notimpl_bs_c_8,
|
||||
|
||||
#ifdef __BUS_SPACE_HAS_STREAM_METHODS
|
||||
/* read (single) */
|
||||
generic_bs_r_1,
|
||||
NSWAP(generic_armv4_bs_r_2),
|
||||
NSWAP(generic_bs_r_4),
|
||||
bs_notimpl_bs_r_8,
|
||||
|
||||
/* read multiple */
|
||||
generic_bs_rm_1,
|
||||
NSWAP(generic_armv4_bs_rm_2),
|
||||
NSWAP(generic_bs_rm_4),
|
||||
bs_notimpl_bs_rm_8,
|
||||
|
||||
/* read region */
|
||||
generic_bs_rr_1,
|
||||
NSWAP(generic_armv4_bs_rr_2),
|
||||
NSWAP(generic_bs_rr_4),
|
||||
bs_notimpl_bs_rr_8,
|
||||
|
||||
/* write (single) */
|
||||
generic_bs_w_1,
|
||||
NSWAP(generic_armv4_bs_w_2),
|
||||
NSWAP(generic_bs_w_4),
|
||||
bs_notimpl_bs_w_8,
|
||||
|
||||
/* write multiple */
|
||||
generic_bs_wm_1,
|
||||
NSWAP(generic_armv4_bs_wm_2),
|
||||
NSWAP(generic_bs_wm_4),
|
||||
bs_notimpl_bs_wm_8,
|
||||
|
||||
/* write region */
|
||||
generic_bs_wr_1,
|
||||
NSWAP(generic_armv4_bs_wr_2),
|
||||
NSWAP(generic_bs_wr_4),
|
||||
bs_notimpl_bs_wr_8,
|
||||
#endif
|
||||
};
|
||||
|
||||
struct bus_space exynos_a4x_bs_tag = {
|
||||
/* cookie */
|
||||
(void *) 0,
|
||||
|
||||
/* mapping/unmapping */
|
||||
exynos_bs_map,
|
||||
exynos_bs_unmap,
|
||||
exynos_a4x_bs_subregion,
|
||||
|
||||
/* allocation/deallocation */
|
||||
exynos_bs_alloc, /* not implemented */
|
||||
exynos_bs_free, /* not implemented */
|
||||
|
||||
/* get kernel virtual address */
|
||||
exynos_bs_vaddr,
|
||||
|
||||
/* mmap */
|
||||
exynos_a4x_bs_mmap,
|
||||
|
||||
/* barrier */
|
||||
exynos_bs_barrier,
|
||||
|
||||
/* read (single) */
|
||||
a4x_bs_r_1,
|
||||
NSWAP(a4x_bs_r_2),
|
||||
NSWAP(a4x_bs_r_4),
|
||||
bs_notimpl_bs_r_8,
|
||||
|
||||
/* read multiple */
|
||||
a4x_bs_rm_1,
|
||||
NSWAP(a4x_bs_rm_2),
|
||||
NSWAP(a4x_bs_rm_4),
|
||||
bs_notimpl_bs_rm_8,
|
||||
|
||||
/* read region */
|
||||
bs_notimpl_bs_rr_1,
|
||||
bs_notimpl_bs_rr_2,
|
||||
bs_notimpl_bs_rr_4,
|
||||
bs_notimpl_bs_rr_8,
|
||||
|
||||
/* write (single) */
|
||||
a4x_bs_w_1,
|
||||
NSWAP(a4x_bs_w_2),
|
||||
NSWAP(a4x_bs_w_4),
|
||||
bs_notimpl_bs_w_8,
|
||||
|
||||
/* write multiple */
|
||||
a4x_bs_wm_1,
|
||||
NSWAP(a4x_bs_wm_2),
|
||||
NSWAP(a4x_bs_wm_4),
|
||||
bs_notimpl_bs_wm_8,
|
||||
|
||||
/* write region */
|
||||
bs_notimpl_bs_wr_1,
|
||||
bs_notimpl_bs_wr_2,
|
||||
bs_notimpl_bs_wr_4,
|
||||
bs_notimpl_bs_wr_8,
|
||||
|
||||
/* set multiple */
|
||||
bs_notimpl_bs_sm_1,
|
||||
bs_notimpl_bs_sm_2,
|
||||
bs_notimpl_bs_sm_4,
|
||||
bs_notimpl_bs_sm_8,
|
||||
|
||||
/* set region */
|
||||
bs_notimpl_bs_sr_1,
|
||||
bs_notimpl_bs_sr_2,
|
||||
bs_notimpl_bs_sr_4,
|
||||
bs_notimpl_bs_sr_8,
|
||||
|
||||
/* copy */
|
||||
bs_notimpl_bs_c_1,
|
||||
bs_notimpl_bs_c_2,
|
||||
bs_notimpl_bs_c_4,
|
||||
bs_notimpl_bs_c_8,
|
||||
|
||||
#ifdef __BUS_SPACE_HAS_STREAM_METHODS
|
||||
/* read (single) */
|
||||
a4x_bs_r_1,
|
||||
NSWAP(a4x_bs_r_2),
|
||||
NSWAP(a4x_bs_r_4),
|
||||
bs_notimpl_bs_r_8,
|
||||
|
||||
/* read multiple */
|
||||
a4x_bs_rm_1,
|
||||
NSWAP(a4x_bs_rm_2),
|
||||
NSWAP(a4x_bs_rm_4),
|
||||
bs_notimpl_bs_rm_8,
|
||||
|
||||
/* read region */
|
||||
a4x_bs_rr_1,
|
||||
NSWAP(a4x_bs_rr_2),
|
||||
NSWAP(a4x_bs_rr_4),
|
||||
bs_notimpl_bs_rr_8,
|
||||
|
||||
/* write (single) */
|
||||
a4x_bs_w_1,
|
||||
NSWAP(a4x_bs_w_2),
|
||||
NSWAP(a4x_bs_w_4),
|
||||
bs_notimpl_bs_w_8,
|
||||
|
||||
/* write multiple */
|
||||
a4x_bs_wm_1,
|
||||
NSWAP(a4x_bs_wm_2),
|
||||
NSWAP(a4x_bs_wm_4),
|
||||
bs_notimpl_bs_wm_8,
|
||||
|
||||
/* write region */
|
||||
a4x_bs_wr_1,
|
||||
NSWAP(a4x_bs_wr_2),
|
||||
NSWAP(a4x_bs_wr_4),
|
||||
bs_notimpl_bs_wr_8,
|
||||
#endif
|
||||
};
|
||||
|
||||
int
|
||||
exynos_bs_map(void *t, bus_addr_t bpa, bus_size_t size, int flag,
|
||||
bus_space_handle_t *bshp)
|
||||
{
|
||||
u_long startpa, endpa, pa;
|
||||
const struct pmap_devmap *pd;
|
||||
vaddr_t va;
|
||||
|
||||
if ((pd = pmap_devmap_find_pa(bpa, size)) != NULL) {
|
||||
/* Device was statically mapped. */
|
||||
*bshp = pd->pd_va + (bpa - pd->pd_pa);
|
||||
return 0;
|
||||
}
|
||||
|
||||
startpa = trunc_page(bpa);
|
||||
endpa = round_page(bpa + size);
|
||||
|
||||
/* XXX use extent manager to check duplicate mapping */
|
||||
|
||||
va = uvm_km_alloc(kernel_map, endpa - startpa, 0,
|
||||
UVM_KMF_VAONLY | UVM_KMF_NOWAIT | UVM_KMF_COLORMATCH);
|
||||
if (!va)
|
||||
return ENOMEM;
|
||||
|
||||
*bshp = (bus_space_handle_t)(va + (bpa - startpa));
|
||||
|
||||
const int pmapflags =
|
||||
(flag & (BUS_SPACE_MAP_CACHEABLE|BUS_SPACE_MAP_PREFETCHABLE))
|
||||
? 0
|
||||
: PMAP_NOCACHE;
|
||||
for (pa = startpa; pa < endpa; pa += PAGE_SIZE, va += PAGE_SIZE) {
|
||||
pmap_kenter_pa(va, pa, VM_PROT_READ | VM_PROT_WRITE, pmapflags);
|
||||
}
|
||||
pmap_update(pmap_kernel());
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void
|
||||
exynos_bs_unmap(void *t, bus_space_handle_t bsh, bus_size_t size)
|
||||
{
|
||||
vaddr_t va;
|
||||
vsize_t sz;
|
||||
|
||||
if (pmap_devmap_find_va(bsh, size) != NULL) {
|
||||
/* Device was statically mapped; nothing to do. */
|
||||
return;
|
||||
}
|
||||
|
||||
va = trunc_page(bsh);
|
||||
sz = round_page(bsh + size) - va;
|
||||
|
||||
pmap_kremove(va, sz);
|
||||
pmap_update(pmap_kernel());
|
||||
uvm_km_free(kernel_map, va, sz, UVM_KMF_VAONLY);
|
||||
}
|
||||
|
||||
|
||||
int
|
||||
exynos_bs_subregion(void *t, bus_space_handle_t bsh, bus_size_t offset,
|
||||
bus_size_t size, bus_space_handle_t *nbshp)
|
||||
{
|
||||
|
||||
*nbshp = bsh + offset;
|
||||
return (0);
|
||||
}
|
||||
|
||||
int
|
||||
exynos_a4x_bs_subregion(void *t, bus_space_handle_t bsh, bus_size_t offset,
|
||||
bus_size_t size, bus_space_handle_t *nbshp)
|
||||
{
|
||||
|
||||
*nbshp = bsh + 4 * offset;
|
||||
return (0);
|
||||
}
|
||||
|
||||
void
|
||||
exynos_bs_barrier(void *t, bus_space_handle_t bsh, bus_size_t offset,
|
||||
bus_size_t len, int flags)
|
||||
{
|
||||
flags &= BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE;
|
||||
|
||||
if (flags)
|
||||
arm_dsb();
|
||||
}
|
||||
|
||||
void *
|
||||
exynos_bs_vaddr(void *t, bus_space_handle_t bsh)
|
||||
{
|
||||
|
||||
return (void *)bsh;
|
||||
}
|
||||
|
||||
paddr_t
|
||||
exynos_bs_mmap(void *t, bus_addr_t bpa, off_t offset, int prot, int flags)
|
||||
{
|
||||
paddr_t bus_flags = 0;
|
||||
|
||||
if (flags & BUS_SPACE_MAP_PREFETCHABLE)
|
||||
bus_flags |= ARM32_MMAP_WRITECOMBINE;
|
||||
|
||||
return (arm_btop(bpa + offset) | bus_flags);
|
||||
}
|
||||
|
||||
paddr_t
|
||||
exynos_a4x_bs_mmap(void *t, bus_addr_t bpa, off_t offset, int prot, int flags)
|
||||
{
|
||||
paddr_t bus_flags = 0;
|
||||
|
||||
if (flags & BUS_SPACE_MAP_PREFETCHABLE)
|
||||
bus_flags |= ARM32_MMAP_WRITECOMBINE;
|
||||
|
||||
return (arm_btop(bpa + 4 * offset) | bus_flags);
|
||||
}
|
||||
|
||||
int
|
||||
exynos_bs_alloc(void *t, bus_addr_t rstart, bus_addr_t rend,
|
||||
bus_size_t size, bus_size_t alignment, bus_size_t boundary, int flags,
|
||||
bus_addr_t *bpap, bus_space_handle_t *bshp)
|
||||
{
|
||||
|
||||
panic("%s(): not implemented\n", __func__);
|
||||
}
|
||||
|
||||
void
|
||||
exynos_bs_free(void *t, bus_space_handle_t bsh, bus_size_t size)
|
||||
{
|
||||
|
||||
panic("%s(): not implemented\n", __func__);
|
||||
}
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: exynos_usb.c,v 1.14 2015/12/21 03:34:34 marty Exp $ */
|
||||
/* $NetBSD: exynos_usb.c,v 1.15 2015/12/21 04:58:50 marty Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 2014 The NetBSD Foundation, Inc.
|
||||
@ -35,7 +35,7 @@
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
|
||||
__KERNEL_RCSID(1, "$NetBSD: exynos_usb.c,v 1.14 2015/12/21 03:34:34 marty Exp $");
|
||||
__KERNEL_RCSID(1, "$NetBSD: exynos_usb.c,v 1.15 2015/12/21 04:58:50 marty Exp $");
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
@ -65,7 +65,6 @@ __KERNEL_RCSID(1, "$NetBSD: exynos_usb.c,v 1.14 2015/12/21 03:34:34 marty Exp $"
|
||||
|
||||
#include <arm/samsung/exynos_reg.h>
|
||||
#include <arm/samsung/exynos_var.h>
|
||||
#include <arm/samsung/exynos_io.h>
|
||||
|
||||
#include <dev/fdt/fdtvar.h>
|
||||
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: exynos_wdt.c,v 1.8 2015/12/15 23:15:53 marty Exp $ */
|
||||
/* $NetBSD: exynos_wdt.c,v 1.9 2015/12/21 04:58:50 marty Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 2012 The NetBSD Foundation, Inc.
|
||||
@ -32,7 +32,7 @@
|
||||
#include "exynos_wdt.h"
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__KERNEL_RCSID(0, "$NetBSD: exynos_wdt.c,v 1.8 2015/12/15 23:15:53 marty Exp $");
|
||||
__KERNEL_RCSID(0, "$NetBSD: exynos_wdt.c,v 1.9 2015/12/21 04:58:50 marty Exp $");
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/bus.h>
|
||||
@ -44,7 +44,6 @@ __KERNEL_RCSID(0, "$NetBSD: exynos_wdt.c,v 1.8 2015/12/15 23:15:53 marty Exp $")
|
||||
|
||||
#include <dev/sysmon/sysmonvar.h>
|
||||
|
||||
#include <arm/samsung/exynos_io.h>
|
||||
#include <arm/samsung/exynos_reg.h>
|
||||
#include <arm/samsung/exynos_var.h>
|
||||
|
||||
@ -281,7 +280,7 @@ exynos_wdt_attach(device_t parent, device_t self, void *aux)
|
||||
void
|
||||
exynos_wdt_reset(void)
|
||||
{
|
||||
bus_space_tag_t bst = &exynos_bs_tag;
|
||||
bus_space_tag_t bst = &armv7_generic_bs_tag;
|
||||
bus_space_handle_t bsh = exynos_wdt_bsh;
|
||||
|
||||
(void) splhigh();
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
# $NetBSD: files.exynos,v 1.16 2015/12/21 03:34:34 marty Exp $
|
||||
# $NetBSD: files.exynos,v 1.17 2015/12/21 04:58:50 marty Exp $
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||||
#
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||||
# Configuration info for Samsung Exynos SoC ARM Peripherals
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||||
#
|
||||
@ -16,8 +16,7 @@ file arch/arm/arm32/armv7_generic_space.c
|
||||
file arch/arm/arm/bus_space_a4x.S
|
||||
|
||||
file arch/arm/samsung/exynos_soc.c
|
||||
file arch/arm/samsung/exynos_space.c
|
||||
#file arch/arm/samsung/exynos_dma.c
|
||||
#file arch/arm/samsung/exynos_space.c
|
||||
file arch/arm/samsung/exynos_smc.S arm_trustzone_firmware
|
||||
|
||||
# Console parameters
|
||||
@ -49,13 +48,6 @@ device exynosfdt : bus_space_generic, fdtbus
|
||||
attach exynosfdt at mainbus with exynos_fdt
|
||||
file arch/arm/samsung/exynos_fdt.c exynos_fdt
|
||||
|
||||
# SoC I/O attach point
|
||||
device exyo { [port=-1], [intr=-1] } : bus_space_generic
|
||||
attach exyo at mainbus with exyo_io
|
||||
file arch/arm/samsung/exynos_io.c exyo_io
|
||||
file arch/arm/samsung/exynos4_loc.c exyo_io & exynos4
|
||||
file arch/arm/samsung/exynos5_loc.c exyo_io & exynos5
|
||||
|
||||
# Interrupt combiner
|
||||
device exyointr
|
||||
attach exyointr at fdt with exynos_intr
|
||||
@ -79,7 +71,7 @@ file arch/arm/samsung/mct.c exyo_mct
|
||||
# Watchdog
|
||||
device exyowdt : sysmon_wdog
|
||||
attach exyowdt at fdt with exynos_wdt
|
||||
file arch/arm/samsung/exynos_wdt.c exynos_wdt | exyo_io needs-flag
|
||||
file arch/arm/samsung/exynos_wdt.c exynos_wdt needs-flag
|
||||
|
||||
# UARTs
|
||||
device sscom { } : bus_space_generic
|
||||
@ -92,13 +84,13 @@ defparam opt_sscom.h SSCOM_FREQ
|
||||
# PINCTL
|
||||
device exyopctl : gpiobus
|
||||
attach exyopctl at fdt with exynos_pinctrl
|
||||
file arch/arm/samsung/exynos_pinctrl.c exynos_pinctl | exyo_io needs-flag
|
||||
file arch/arm/samsung/exynos_gpio.c exynos_pinctl | exyo_io needs-flag
|
||||
file arch/arm/samsung/exynos_pinctrl.c exynos_pinctrl needs-flag
|
||||
file arch/arm/samsung/exynos_gpio.c exynos_pinctrl needs-flag
|
||||
|
||||
# GPIO
|
||||
#device exyogpio : gpiobus
|
||||
#attach exyogpio at fdt with exynos_gpio
|
||||
#file arch/arm/samsung/exynos_gpio.c exynos_gpio | exyo_io needs-flag
|
||||
#file arch/arm/samsung/exynos_gpio.c exynos_gpio needs-flag
|
||||
|
||||
# USB2 Host Controller (EHCI/OHCI)
|
||||
device exyousb { } : fdtbus
|
||||
@ -110,7 +102,7 @@ file arch/arm/samsung/exynos_usb.c exyo_usb
|
||||
# I2C support, bitbanging trough GPIO
|
||||
device exyoi2c: i2cbus, i2c_bitbang
|
||||
attach exyoi2c at fdt with exynos_i2c
|
||||
file arch/arm/samsung/exynos_i2c.c exynos_iic | exyo_io needs-flag
|
||||
file arch/arm/samsung/exynos_i2c.c exynos_i2c needs-flag
|
||||
|
||||
file arch/arm/samsung/exynos5422_dma.c
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
#
|
||||
# $NetBSD: EXYNOS,v 1.5 2015/12/21 03:34:34 marty Exp $
|
||||
# $NetBSD: EXYNOS,v 1.6 2015/12/21 04:58:50 marty Exp $
|
||||
#
|
||||
# ODROID-XU -- ODROID-XU4 Exynos5422 based kernel
|
||||
#
|
||||
@ -213,9 +213,6 @@ fregulator* at fdt?
|
||||
exyointr0 at fdt?
|
||||
gic* at fdt?
|
||||
|
||||
# Exynos SoC
|
||||
exyo0 at mainbus?
|
||||
|
||||
# Clock controller
|
||||
exy5422clk0 at fdt? # Exynos5422 clock controller
|
||||
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: exynos_machdep.c,v 1.6 2015/12/20 05:25:01 marty Exp $ */
|
||||
/* $NetBSD: exynos_machdep.c,v 1.7 2015/12/21 04:58:50 marty Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2014 The NetBSD Foundation, Inc.
|
||||
@ -31,7 +31,7 @@
|
||||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__KERNEL_RCSID(0, "$NetBSD: exynos_machdep.c,v 1.6 2015/12/20 05:25:01 marty Exp $");
|
||||
__KERNEL_RCSID(0, "$NetBSD: exynos_machdep.c,v 1.7 2015/12/21 04:58:50 marty Exp $");
|
||||
|
||||
#include "opt_evbarm_boardtype.h"
|
||||
#include "opt_exynos.h"
|
||||
@ -81,7 +81,6 @@ __KERNEL_RCSID(0, "$NetBSD: exynos_machdep.c,v 1.6 2015/12/20 05:25:01 marty Exp
|
||||
#include <arm/arm32/machdep.h>
|
||||
#include <arm/mainbus/mainbus.h>
|
||||
|
||||
#include <arm/samsung/exynos4_reg.h>
|
||||
#include <arm/samsung/exynos5_reg.h>
|
||||
#include <arm/samsung/exynos_var.h>
|
||||
|
||||
@ -450,7 +449,7 @@ consinit(void)
|
||||
consinit_called = true;
|
||||
|
||||
#if NSSCOM > 0
|
||||
bus_space_tag_t bst = &exynos_bs_tag;
|
||||
bus_space_tag_t bst = &armv7_generic_bs_tag;
|
||||
bus_addr_t iobase = armreg_tpidruro_read();
|
||||
bus_space_handle_t bsh = EXYNOS_IOPHYSTOVIRT(iobase);
|
||||
u_int i;
|
||||
@ -553,7 +552,7 @@ void
|
||||
exynos_init_clkout_for_usb(void)
|
||||
{
|
||||
/* Select XUSBXTI as source for CLKOUT */
|
||||
bus_space_write_4(&exynos_bs_tag, exynos_pmu_bsh,
|
||||
bus_space_write_4(&armv7_generic_bs_tag, exynos_pmu_bsh,
|
||||
EXYNOS_PMU_DEBUG_CLKOUT, 0x1000);
|
||||
}
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user