From 4a8f937fe5322227d320098c1cc371cf8b6bd39d Mon Sep 17 00:00:00 2001
From: maxv <maxv@NetBSD.org>
Date: Fri, 4 Sep 2020 17:05:09 +0000
Subject: [PATCH] Add a few more CPUID flags.

---
 sys/arch/x86/include/specialreg.h | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/sys/arch/x86/include/specialreg.h b/sys/arch/x86/include/specialreg.h
index 60fd0d1ed6e9..beb3f9a2e8d1 100644
--- a/sys/arch/x86/include/specialreg.h
+++ b/sys/arch/x86/include/specialreg.h
@@ -1,4 +1,4 @@
-/*	$NetBSD: specialreg.h,v 1.171 2020/08/05 15:40:46 maxv Exp $	*/
+/*	$NetBSD: specialreg.h,v 1.172 2020/09/04 17:05:09 maxv Exp $	*/
 
 /*
  * Copyright (c) 2014-2020 The NetBSD Foundation, Inc.
@@ -759,6 +759,11 @@
 #define CPUID_CAPEX_VIRT_SSBD	__BIT(25)	/* Virt Spec Control SSBD */
 #define CPUID_CAPEX_SSB_NO	__BIT(26)	/* SSBD not required */
 
+/* %ecx */
+#define CPUID_CAPEX_PerfTscSize	__BITS(17,16)
+#define CPUID_CAPEX_ApicIdSize	__BITS(15,12)
+#define CPUID_CAPEX_NC		__BITS(7,0)
+
 #define CPUID_CAPEX_FLAGS	"\20"					 \
 	"\1CLZERO"	"\2IRPERF"	"\3XSAVEERPTR"			 \
 	"\5RDPRU"			"\7B6"				 \
@@ -767,6 +772,9 @@
 	"\21IBRS_ALWAYSON" "\22STIBP_ALWAYSON" "\23PREFER_IBRS"	"\24B19" \
 	"\31SSBD"	"\32VIRT_SSBD"	"\33SSB_NO"
 
+/* AMD Fn8000_000a %eax (SVM Revision) */
+#define CPUID_AMD_SVM_REV		__BITS(7,0)
+
 /* AMD Fn8000_000a %edx features (SVM features) */
 #define CPUID_AMD_SVM_NP		0x00000001
 #define CPUID_AMD_SVM_LbrVirt		0x00000002