mips/cavium: Take advantage of Octeon's guaranteed r/rw ordering.
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riastradh
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/* $NetBSD: membar_ops.S,v 1.12 2022/04/09 23:32:51 riastradh Exp $ */
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/* $NetBSD: membar_ops.S,v 1.13 2022/04/21 12:06:31 riastradh Exp $ */
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/*-
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* Copyright (c) 2006, 2007 The NetBSD Foundation, Inc.
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@ -38,44 +38,80 @@ LEAF(_membar_sync)
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j ra
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BDSYNC
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END(_membar_sync)
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ATOMIC_OP_ALIAS(membar_sync,_membar_sync)
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STRONG_ALIAS(_membar_enter,_membar_sync)
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ATOMIC_OP_ALIAS(membar_enter,_membar_sync)
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#ifdef __OCTEON__
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/*
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* cnMIPS guarantees load-before-load/store ordering without any
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* barriers. So the only barriers we need are store-before-load (sync)
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* and store-before-store (syncw, i.e., sync 4). See Table 2-32
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* `Execution Ordering Rules' on p. 104 of Cavium OCTEON III CN78XX
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* Hardware Reference Manual, CN78XX-HM-0.99E, September 2014:
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*
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* First Operation DLD [load instruction to a physical
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* address that is L2/DRAM]
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* Second Operation Any
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* Execution Ordering Comments
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*
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* The second operation cannot appear to execute before
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* the first (DLD) operation, regardless of the presence
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* or absence of SYNC* instructions.
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*
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* Note: I'm not sure if this applies to earlier cnMIPS -- can't find
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* it in the Cavium Networks OCTEON Plus CN50XX Hardware Reference
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* Manual CN50XX-HM-0.99E, July 2008. Experimentally, on an erlite3
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* (Cavium Octeon CN5020-500), I can easily detect reordering of
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* store-before-store and store-before-load, but I haven't been able to
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* detect any reordering of load-before-load or load-before-store.
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*
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* Note: On early cnMIPS (CN3xxx), there is an erratum which sometimes
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* requires issuing two syncw's in a row. I don't know the details --
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* don't have documentation -- and in Linux it is only used for I/O
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* purposes.
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*
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* Currently we don't build kernels that work on both Octeon and
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* non-Octeon MIPS CPUs, so none of this is done with binary patching.
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* For userlands we could use a separate shared library on Octeon with
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* ld.so.conf to override the symbols with cheaper definitions, but we
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* don't do that now.
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*/
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LEAF(_membar_acquire)
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j ra
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nop
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END(_membar_acquire)
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ATOMIC_OP_ALIAS(membar_acquire,_membar_acquire)
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STRONG_ALIAS(_membar_consumer,_membar_acquire)
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ATOMIC_OP_ALIAS(membar_consumer,_membar_acquire)
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LEAF(_membar_release)
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/*
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* syncw is documented as ordering store-before-store in
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*
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* Cavium OCTEON III CN78XX Hardware Reference Manual,
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* CN78XX-HM-0.99E, September 2014.
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*
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* It's unclear from the documentation the architecture
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* guarantees load-before-store ordering without barriers, but
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* this code assumes it does. If that assumption is wrong, we
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* can only use syncw for membar_producer -- membar_release has
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* to use the full sync.
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*/
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j ra
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syncw
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END(_membar_release)
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#endif
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ATOMIC_OP_ALIAS(membar_sync,_membar_sync)
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ATOMIC_OP_ALIAS(membar_acquire,_membar_sync)
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STRONG_ALIAS(_membar_acquire,_membar_sync)
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ATOMIC_OP_ALIAS(membar_enter,_membar_sync)
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STRONG_ALIAS(_membar_enter,_membar_sync)
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#ifdef __OCTEON__
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ATOMIC_OP_ALIAS(membar_exit,_membar_release)
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STRONG_ALIAS(_membar_exit,_membar_release)
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ATOMIC_OP_ALIAS(membar_release,_membar_release)
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ATOMIC_OP_ALIAS(membar_producer,_membar_release)
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STRONG_ALIAS(_membar_exit,_membar_release)
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ATOMIC_OP_ALIAS(membar_exit,_membar_release)
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STRONG_ALIAS(_membar_producer,_membar_release)
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#else
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ATOMIC_OP_ALIAS(membar_exit,_membar_sync)
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STRONG_ALIAS(_membar_exit,_membar_sync)
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ATOMIC_OP_ALIAS(membar_release,_membar_sync)
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ATOMIC_OP_ALIAS(membar_producer,_membar_release)
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#else /* !__OCTEON__ */
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STRONG_ALIAS(_membar_acquire,_membar_sync)
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ATOMIC_OP_ALIAS(membar_acquire,_membar_sync)
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STRONG_ALIAS(_membar_release,_membar_sync)
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ATOMIC_OP_ALIAS(membar_producer,_membar_sync)
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STRONG_ALIAS(_membar_producer,_membar_sync)
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#endif
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ATOMIC_OP_ALIAS(membar_consumer,_membar_sync)
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ATOMIC_OP_ALIAS(membar_release,_membar_sync)
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STRONG_ALIAS(_membar_exit,_membar_sync)
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ATOMIC_OP_ALIAS(membar_exit,_membar_sync)
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STRONG_ALIAS(_membar_consumer,_membar_sync)
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ATOMIC_OP_ALIAS(membar_consumer,_membar_sync)
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STRONG_ALIAS(_membar_producer,_membar_sync)
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ATOMIC_OP_ALIAS(membar_producer,_membar_sync)
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#endif
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@ -1,4 +1,4 @@
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/* $NetBSD: asm.h,v 1.70 2022/04/09 14:09:32 riastradh Exp $ */
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/* $NetBSD: asm.h,v 1.71 2022/04/21 12:06:31 riastradh Exp $ */
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/*
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* Copyright (c) 1992, 1993
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@ -574,12 +574,21 @@ _C_LABEL(x):
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/* compiler define */
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#if defined(__OCTEON__)
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/* early cnMIPS have erratum which means 2 */
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#define LLSCSYNC sync 4; sync 4
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/*
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* See common/lib/libc/arch/mips/atomic/membar_ops.S for notes on
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* Octeon memory ordering guarantees and barriers.
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*
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* cnMIPS also has a quirk where the store buffer can get clogged and
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* we need to apply a plunger to it _after_ releasing a lock or else
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* other CPUs may spin for hundreds of thousands of cycles before they
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* see the lock is released. So we also have the quirky SYNC_PLUNGER
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* barrier as syncw.
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*/
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#define LLSCSYNC /* nothing */
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#define BDSYNC sync
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#define BDSYNC_ACQ sync
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#define SYNC_ACQ sync
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#define SYNC_REL sync
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#define BDSYNC_ACQ nop
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#define SYNC_ACQ /* nothing */
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#define SYNC_REL sync 4
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#define BDSYNC_PLUNGER sync 4
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#define SYNC_PLUNGER sync 4
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#elif __mips >= 3 || !defined(__mips_o32)
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