Intel i82557 driver is now split into bus and chip bits.
This commit is contained in:
thorpej
parent
495319c367
commit
4a0270a264
@ -1,4 +1,4 @@
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# $NetBSD: files.pci,v 1.55 1999/06/01 18:29:50 thorpej Exp $
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# $NetBSD: files.pci,v 1.56 1999/06/20 16:35:40 thorpej Exp $
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#
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# Config file and device description for machine-independent PCI code.
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# Included by ports that need it. Requires that the SCSI files be
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@ -98,9 +98,8 @@ attach cy at pci with cy_pci
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file dev/pci/cy_pci.c cy_pci
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# Intel EtherExpress PRO 10/100B
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device fxp: ether, ifnet, arp, mii
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attach fxp at pci
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file dev/pci/if_fxp.c fxp
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attach fxp at pci with fxp_pci
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file dev/pci/if_fxp_pci.c fxp_pci
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# NE2000-compatible PCI Ethernet cards
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attach ne at pci with ne_pci: rtl80x9
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1830
sys/dev/pci/if_fxp.c
1830
sys/dev/pci/if_fxp.c
File diff suppressed because it is too large
Load Diff
224
sys/dev/pci/if_fxp_pci.c
Normal file
224
sys/dev/pci/if_fxp_pci.c
Normal file
@ -0,0 +1,224 @@
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/* $NetBSD: if_fxp_pci.c,v 1.1 1999/06/20 16:35:40 thorpej Exp $ */
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/*-
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* Copyright (c) 1997, 1998, 1999 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
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* NASA Ames Research Center.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* PCI bus front-end for the Intel i82557 fast Ethernet controller
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* driver. Works with Intel Etherexpress Pro 10+, 100B, 100+ cards.
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*/
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#include "opt_inet.h"
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#include "opt_ns.h"
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#include "bpfilter.h"
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#include "rnd.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/mbuf.h>
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#include <sys/malloc.h>
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#include <sys/kernel.h>
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#include <sys/socket.h>
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#include <sys/ioctl.h>
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#include <sys/errno.h>
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#include <sys/device.h>
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#if NRND > 0
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#include <sys/rnd.h>
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#endif
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#include <net/if.h>
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#include <net/if_dl.h>
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#include <net/if_media.h>
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#include <net/if_ether.h>
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#if NBPFILTER > 0
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#include <net/bpf.h>
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#endif
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#ifdef INET
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#include <netinet/in.h>
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#include <netinet/if_inarp.h>
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#endif
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#ifdef NS
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#include <netns/ns.h>
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#include <netns/ns_if.h>
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#endif
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#include <machine/bus.h>
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#include <machine/intr.h>
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#include <dev/mii/miivar.h>
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#include <dev/ic/i82557reg.h>
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#include <dev/ic/i82557var.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcidevs.h>
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int fxp_pci_match __P((struct device *, struct cfdata *, void *));
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void fxp_pci_attach __P((struct device *, struct device *, void *));
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struct cfattach fxp_pci_ca = {
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sizeof(struct fxp_softc), fxp_pci_match, fxp_pci_attach
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};
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int
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fxp_pci_match(parent, match, aux)
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struct device *parent;
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struct cfdata *match;
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void *aux;
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{
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struct pci_attach_args *pa = aux;
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if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL)
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return (0);
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switch (PCI_PRODUCT(pa->pa_id)) {
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case PCI_PRODUCT_INTEL_82557:
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return (1);
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}
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return (0);
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}
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void
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fxp_pci_attach(parent, self, aux)
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struct device *parent, *self;
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void *aux;
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{
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struct fxp_softc *sc = (struct fxp_softc *)self;
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struct pci_attach_args *pa = aux;
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pci_chipset_tag_t pc = pa->pa_pc;
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pci_intr_handle_t ih;
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const char *intrstr = NULL;
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bus_space_tag_t iot, memt;
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bus_space_handle_t ioh, memh;
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int ioh_valid, memh_valid;
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bus_addr_t addr;
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bus_size_t size;
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int flags;
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/*
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* Map control/status registers.
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*/
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ioh_valid = (pci_mapreg_map(pa, FXP_PCI_IOBA,
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PCI_MAPREG_TYPE_IO, 0,
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&iot, &ioh, NULL, NULL) == 0);
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/*
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* Version 2.1 of the PCI spec, page 196, "Address Maps":
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*
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* Prefetchable
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*
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* Set to one if there are no side effects on reads, the
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* device returns all bytes regardless of the byte enables,
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* and host bridges can merge processor writes into this
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* range without causing errors. Bit must be set to zero
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* otherwise.
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*
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* The 82557 incorrectly sets the "prefetchable" bit, resulting
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* in errors on systems which will do merged reads and writes.
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* These errors manifest themselves as all-bits-set when reading
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* from the EEPROM or other < 4 byte registers.
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*
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* We must work around this problem by always forcing the mapping
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* for memory space to be uncacheable. On systems which cannot
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* create an uncacheable mapping (because the firmware mapped it
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* into only cacheable/prefetchable space due to the "prefetchable"
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* bit), we can fall back onto i/o mapped access.
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*/
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memh_valid = 0;
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memt = pa->pa_memt;
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if (((pa->pa_flags & PCI_FLAGS_MEM_ENABLED) != 0) &&
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pci_mapreg_info(pa->pa_pc, pa->pa_tag, FXP_PCI_MMBA,
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PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT,
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&addr, &size, &flags) == 0) {
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flags &= ~BUS_SPACE_MAP_CACHEABLE;
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if (bus_space_map(memt, addr, size, flags, &memh) == 0)
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memh_valid = 1;
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}
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if (memh_valid) {
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sc->sc_st = memt;
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sc->sc_sh = memh;
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} else if (ioh_valid) {
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sc->sc_st = iot;
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sc->sc_sh = ioh;
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} else {
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printf(": unable to map device registers\n");
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return;
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}
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sc->sc_dmat = pa->pa_dmat;
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/*
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* XXX Perhaps report '557, '558, '559 based on revision?
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*/
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printf(": Intel i82557 Ethernet, rev %d\n",
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PCI_REVISION(pa->pa_class));
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/* Make sure bus-mastering is enabled. */
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pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG,
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pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) |
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PCI_COMMAND_MASTER_ENABLE);
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/*
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* Map and establish our interrupt.
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*/
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if (pci_intr_map(pc, pa->pa_intrtag, pa->pa_intrpin,
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pa->pa_intrline, &ih)) {
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printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname);
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return;
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}
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intrstr = pci_intr_string(pc, ih);
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sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, fxp_intr, sc);
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if (sc->sc_ih == NULL) {
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printf("%s: couldn't establish interrupt",
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sc->sc_dev.dv_xname);
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if (intrstr != NULL)
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printf(" at %s", intrstr);
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printf("\n");
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return;
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}
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printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr);
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/* Finish off the attach. */
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fxp_attach(sc);
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}
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@ -1,398 +0,0 @@
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/* $NetBSD: if_fxpreg.h,v 1.9 1998/08/25 01:08:16 thorpej Exp $ */
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/*-
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* Copyright (c) 1998 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
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* NASA Ames Research Center.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
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||||
* 3. All advertising materials mentioning features or use of this software
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||||
* must display the following acknowledgement:
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||||
* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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||||
* 4. Neither the name of The NetBSD Foundation nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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||||
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Copyright (c) 1995, David Greenman
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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||||
* are met:
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||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice unmodified, this list of conditions, and the following
|
||||
* disclaimer.
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||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* Id: if_fxpreg.h,v 1.11 1997/09/29 11:27:42 davidg Exp
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*/
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#define FXP_VENDORID_INTEL 0x8086
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#define FXP_DEVICEID_i82557 0x1229
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#define FXP_PCI_MMBA 0x10
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#define FXP_PCI_IOBA 0x14
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/*
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* Control/status registers.
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*/
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#define FXP_CSR_SCB_RUSCUS 0 /* scb_rus/scb_cus (1 byte) */
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#define FXP_CSR_SCB_STATACK 1 /* scb_statack (1 byte) */
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#define FXP_CSR_SCB_COMMAND 2 /* scb_command (1 byte) */
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#define FXP_CSR_SCB_INTRCNTL 3 /* scb_intrcntl (1 byte) */
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#define FXP_CSR_SCB_GENERAL 4 /* scb_general (4 bytes) */
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#define FXP_CSR_PORT 8 /* port (4 bytes) */
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#define FXP_CSR_FLASHCONTROL 12 /* flash control (2 bytes) */
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#define FXP_CSR_EEPROMCONTROL 14 /* eeprom control (2 bytes) */
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#define FXP_CSR_MDICONTROL 16 /* mdi control (4 bytes) */
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/*
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* FOR REFERENCE ONLY, the old definition of FXP_CSR_SCB_RUSCUS:
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*
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* volatile u_int8_t :2,
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* scb_rus:4,
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* scb_cus:2;
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*/
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#define FXP_PORT_SOFTWARE_RESET 0
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#define FXP_PORT_SELFTEST 1
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#define FXP_PORT_SELECTIVE_RESET 2
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#define FXP_PORT_DUMP 3
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#define FXP_SCB_RUS_IDLE 0
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#define FXP_SCB_RUS_SUSPENDED 1
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#define FXP_SCB_RUS_NORESOURCES 2
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#define FXP_SCB_RUS_READY 4
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#define FXP_SCB_RUS_SUSP_NORBDS 9
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#define FXP_SCB_RUS_NORES_NORBDS 10
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#define FXP_SCB_RUS_READY_NORBDS 12
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#define FXP_SCB_CUS_IDLE 0
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#define FXP_SCB_CUS_SUSPENDED 1
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#define FXP_SCB_CUS_ACTIVE 2
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#define FXP_SCB_STATACK_SWI 0x04
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#define FXP_SCB_STATACK_MDI 0x08
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#define FXP_SCB_STATACK_RNR 0x10
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#define FXP_SCB_STATACK_CNA 0x20
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#define FXP_SCB_STATACK_FR 0x40
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#define FXP_SCB_STATACK_CXTNO 0x80
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#define FXP_SCB_COMMAND_CU_NOP 0x00
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#define FXP_SCB_COMMAND_CU_START 0x10
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#define FXP_SCB_COMMAND_CU_RESUME 0x20
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#define FXP_SCB_COMMAND_CU_DUMP_ADR 0x40
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#define FXP_SCB_COMMAND_CU_DUMP 0x50
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#define FXP_SCB_COMMAND_CU_BASE 0x60
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#define FXP_SCB_COMMAND_CU_DUMPRESET 0x70
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#define FXP_SCB_COMMAND_RU_NOP 0
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#define FXP_SCB_COMMAND_RU_START 1
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#define FXP_SCB_COMMAND_RU_RESUME 2
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#define FXP_SCB_COMMAND_RU_ABORT 4
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#define FXP_SCB_COMMAND_RU_LOADHDS 5
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#define FXP_SCB_COMMAND_RU_BASE 6
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#define FXP_SCB_COMMAND_RU_RBDRESUME 7
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/*
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* Software-use only part of the command block.
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*/
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struct fxp_cb_soft {
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void *next; /* pointer to next command block */
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struct mbuf *mb_head; /* pointer to data for this command */
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bus_dmamap_t dmamap; /* our DMA map */
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};
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/*
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* Command block definitions
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*/
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struct fxp_cb_nop {
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struct fxp_cb_soft cb_soft;
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volatile u_int16_t cb_status;
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volatile u_int16_t cb_command;
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volatile u_int32_t link_addr;
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};
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struct fxp_cb_ias {
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struct fxp_cb_soft cb_soft;
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volatile u_int16_t cb_status;
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volatile u_int16_t cb_command;
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volatile u_int32_t link_addr;
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volatile u_int8_t macaddr[6];
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};
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/* I hate bit-fields :-( */
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struct fxp_cb_config {
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struct fxp_cb_soft cb_soft;
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volatile u_int16_t cb_status;
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volatile u_int16_t cb_command;
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volatile u_int32_t link_addr;
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volatile u_int8_t byte_count:6,
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:2;
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volatile u_int8_t rx_fifo_limit:4,
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tx_fifo_limit:3,
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:1;
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volatile u_int8_t adaptive_ifs;
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volatile u_int8_t :8;
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volatile u_int8_t rx_dma_bytecount:7,
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:1;
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volatile u_int8_t tx_dma_bytecount:7,
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dma_bce:1;
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volatile u_int8_t late_scb:1,
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:1,
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tno_int:1,
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ci_int:1,
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:3,
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save_bf:1;
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volatile u_int8_t disc_short_rx:1,
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underrun_retry:2,
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:5;
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||||
volatile u_int8_t mediatype:1,
|
||||
:7;
|
||||
volatile u_int8_t :8;
|
||||
volatile u_int8_t :3,
|
||||
nsai:1,
|
||||
preamble_length:2,
|
||||
loopback:2;
|
||||
volatile u_int8_t linear_priority:3,
|
||||
:5;
|
||||
volatile u_int8_t linear_pri_mode:1,
|
||||
:3,
|
||||
interfrm_spacing:4;
|
||||
volatile u_int8_t :8;
|
||||
volatile u_int8_t :8;
|
||||
volatile u_int8_t promiscuous:1,
|
||||
bcast_disable:1,
|
||||
:5,
|
||||
crscdt:1;
|
||||
volatile u_int8_t :8;
|
||||
volatile u_int8_t :8;
|
||||
volatile u_int8_t stripping:1,
|
||||
padding:1,
|
||||
rcv_crc_xfer:1,
|
||||
:5;
|
||||
volatile u_int8_t :6,
|
||||
force_fdx:1,
|
||||
fdx_pin_en:1;
|
||||
volatile u_int8_t :6,
|
||||
multi_ia:1,
|
||||
:1;
|
||||
volatile u_int8_t :3,
|
||||
mc_all:1,
|
||||
:4;
|
||||
};
|
||||
|
||||
/*
|
||||
* Size of the hardware portion of a given transmit descriptor, including
|
||||
* the DMA segment array.
|
||||
*/
|
||||
#define FXP_MCSDESCSIZE \
|
||||
(sizeof(struct fxp_cb_mcs) - offsetof(struct fxp_cb_mcs, cb_status))
|
||||
|
||||
#define MAXMCADDR 80
|
||||
struct fxp_cb_mcs {
|
||||
struct fxp_cb_soft cb_soft;
|
||||
volatile u_int16_t cb_status;
|
||||
volatile u_int16_t cb_command;
|
||||
volatile u_int32_t link_addr;
|
||||
volatile u_int16_t mc_cnt;
|
||||
volatile u_int8_t mc_addr[MAXMCADDR][6];
|
||||
};
|
||||
|
||||
/*
|
||||
* Number of DMA segments in a TxCB. The TxCB must map to a
|
||||
* contiguous region from the DMA engine's perspective. Since
|
||||
* we allocate memory conforming to those contraints, we can
|
||||
* arbitrarily choose the number of segments.
|
||||
*/
|
||||
#define FXP_NTXSEG 32
|
||||
|
||||
struct fxp_tbd {
|
||||
volatile u_int32_t tb_addr;
|
||||
volatile u_int32_t tb_size;
|
||||
};
|
||||
struct fxp_cb_tx {
|
||||
struct fxp_cb_soft cb_soft;
|
||||
volatile u_int16_t cb_status;
|
||||
volatile u_int16_t cb_command;
|
||||
volatile u_int32_t link_addr;
|
||||
volatile u_int32_t tbd_array_addr;
|
||||
volatile u_int16_t byte_count;
|
||||
volatile u_int8_t tx_threshold;
|
||||
volatile u_int8_t tbd_number;
|
||||
/*
|
||||
* The following isn't actually part of the TxCB, but we
|
||||
* allocate it here for convenience.
|
||||
*/
|
||||
volatile struct fxp_tbd tbd[FXP_NTXSEG];
|
||||
};
|
||||
|
||||
/*
|
||||
* Offset of the hardware portion of a given transmit descriptor from the
|
||||
* base of the control data DMA mapping.
|
||||
*/
|
||||
#define FXP_TXDESCOFF(sc, txd) \
|
||||
(FXP_CDOFF(fcd_txcbs[0]) + \
|
||||
(((u_long)(txd)) - ((u_long)&(sc)->control_data->fcd_txcbs[0])) + \
|
||||
offsetof(struct fxp_cb_tx, cb_status))
|
||||
|
||||
/*
|
||||
* Size of the hardware portion of a given transmit descriptor, including
|
||||
* the DMA segment array.
|
||||
*/
|
||||
#define FXP_TXDESCSIZE \
|
||||
(sizeof(struct fxp_cb_tx) - offsetof(struct fxp_cb_tx, cb_status))
|
||||
|
||||
/*
|
||||
* Control Block (CB) definitions
|
||||
*/
|
||||
|
||||
/* status */
|
||||
#define FXP_CB_STATUS_OK 0x2000
|
||||
#define FXP_CB_STATUS_C 0x8000
|
||||
/* commands */
|
||||
#define FXP_CB_COMMAND_NOP 0x0
|
||||
#define FXP_CB_COMMAND_IAS 0x1
|
||||
#define FXP_CB_COMMAND_CONFIG 0x2
|
||||
#define FXP_CB_COMMAND_MCAS 0x3
|
||||
#define FXP_CB_COMMAND_XMIT 0x4
|
||||
#define FXP_CB_COMMAND_RESRV 0x5
|
||||
#define FXP_CB_COMMAND_DUMP 0x6
|
||||
#define FXP_CB_COMMAND_DIAG 0x7
|
||||
/* command flags */
|
||||
#define FXP_CB_COMMAND_SF 0x0008 /* simple/flexible mode */
|
||||
#define FXP_CB_COMMAND_I 0x2000 /* generate interrupt on completion */
|
||||
#define FXP_CB_COMMAND_S 0x4000 /* suspend on completion */
|
||||
#define FXP_CB_COMMAND_EL 0x8000 /* end of list */
|
||||
|
||||
/*
|
||||
* RFA definitions
|
||||
* NOTE! The RFA will NOT be aligned on a 4-byte boundary in the DMA
|
||||
* area! To prevent EGCS from optimizing the copy of link_addr and
|
||||
* rbd_addr (which would cause an unaligned access fault on RISC systems),
|
||||
* we must make them an array of bytes!
|
||||
*/
|
||||
|
||||
struct fxp_rfa {
|
||||
volatile u_int16_t rfa_status;
|
||||
volatile u_int16_t rfa_control;
|
||||
volatile u_int8_t link_addr[4];
|
||||
volatile u_int8_t rbd_addr[4];
|
||||
volatile u_int16_t actual_size;
|
||||
volatile u_int16_t size;
|
||||
};
|
||||
#define FXP_RFA_STATUS_RCOL 0x0001 /* receive collision */
|
||||
#define FXP_RFA_STATUS_IAMATCH 0x0002 /* 0 = matches station address */
|
||||
#define FXP_RFA_STATUS_S4 0x0010 /* receive error from PHY */
|
||||
#define FXP_RFA_STATUS_TL 0x0020 /* type/length */
|
||||
#define FXP_RFA_STATUS_FTS 0x0080 /* frame too short */
|
||||
#define FXP_RFA_STATUS_OVERRUN 0x0100 /* DMA overrun */
|
||||
#define FXP_RFA_STATUS_RNR 0x0200 /* no resources */
|
||||
#define FXP_RFA_STATUS_ALIGN 0x0400 /* alignment error */
|
||||
#define FXP_RFA_STATUS_CRC 0x0800 /* CRC error */
|
||||
#define FXP_RFA_STATUS_OK 0x2000 /* packet received okay */
|
||||
#define FXP_RFA_STATUS_C 0x8000 /* packet reception complete */
|
||||
#define FXP_RFA_CONTROL_SF 0x08 /* simple/flexible memory mode */
|
||||
#define FXP_RFA_CONTROL_H 0x10 /* header RFD */
|
||||
#define FXP_RFA_CONTROL_S 0x4000 /* suspend after reception */
|
||||
#define FXP_RFA_CONTROL_EL 0x8000 /* end of list */
|
||||
|
||||
/*
|
||||
* Statistics dump area definitions
|
||||
*/
|
||||
struct fxp_stats {
|
||||
volatile u_int32_t tx_good;
|
||||
volatile u_int32_t tx_maxcols;
|
||||
volatile u_int32_t tx_latecols;
|
||||
volatile u_int32_t tx_underruns;
|
||||
volatile u_int32_t tx_lostcrs;
|
||||
volatile u_int32_t tx_deffered;
|
||||
volatile u_int32_t tx_single_collisions;
|
||||
volatile u_int32_t tx_multiple_collisions;
|
||||
volatile u_int32_t tx_total_collisions;
|
||||
volatile u_int32_t rx_good;
|
||||
volatile u_int32_t rx_crc_errors;
|
||||
volatile u_int32_t rx_alignment_errors;
|
||||
volatile u_int32_t rx_rnr_errors;
|
||||
volatile u_int32_t rx_overrun_errors;
|
||||
volatile u_int32_t rx_cdt_errors;
|
||||
volatile u_int32_t rx_shortframes;
|
||||
volatile u_int32_t completion_status;
|
||||
};
|
||||
#define FXP_STATS_DUMP_COMPLETE 0xa005
|
||||
#define FXP_STATS_DR_COMPLETE 0xa007
|
||||
|
||||
/*
|
||||
* Serial EEPROM control register bits
|
||||
*/
|
||||
/* shift clock */
|
||||
#define FXP_EEPROM_EESK 0x01
|
||||
/* chip select */
|
||||
#define FXP_EEPROM_EECS 0x02
|
||||
/* data in */
|
||||
#define FXP_EEPROM_EEDI 0x04
|
||||
/* data out */
|
||||
#define FXP_EEPROM_EEDO 0x08
|
||||
|
||||
/*
|
||||
* Serial EEPROM opcodes, including start bit
|
||||
*/
|
||||
#define FXP_EEPROM_OPC_ERASE 0x4
|
||||
#define FXP_EEPROM_OPC_WRITE 0x5
|
||||
#define FXP_EEPROM_OPC_READ 0x6
|
||||
|
||||
/*
|
||||
* Management Data Interface opcodes
|
||||
*/
|
||||
#define FXP_MDI_WRITE 0x1
|
||||
#define FXP_MDI_READ 0x2
|
||||
|
||||
/*
|
||||
* PHY device types
|
||||
*/
|
||||
#define FXP_PHY_NONE 0
|
||||
#define FXP_PHY_82553A 1
|
||||
#define FXP_PHY_82553C 2
|
||||
#define FXP_PHY_82503 3
|
||||
#define FXP_PHY_DP83840 4
|
||||
#define FXP_PHY_80C240 5
|
||||
#define FXP_PHY_80C24 6
|
||||
#define FXP_PHY_82555 7
|
||||
#define FXP_PHY_DP83840A 10
|
||||
@ -1,194 +0,0 @@
|
||||
/* $NetBSD: if_fxpvar.h,v 1.9 1999/02/18 01:23:41 thorpej Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 1997, 1998 The NetBSD Foundation, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This code is derived from software contributed to The NetBSD Foundation
|
||||
* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
|
||||
* NASA Ames Research Center.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed by the NetBSD
|
||||
* Foundation, Inc. and its contributors.
|
||||
* 4. Neither the name of The NetBSD Foundation nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
|
||||
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (c) 1995, David Greenman
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice unmodified, this list of conditions, and the following
|
||||
* disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* Id: if_fxpvar.h,v 1.4 1997/11/29 08:11:01 davidg Exp
|
||||
*/
|
||||
|
||||
/*
|
||||
* Misc. defintions for the Intel EtherExpress Pro/100B PCI Fast
|
||||
* Ethernet driver
|
||||
*/
|
||||
|
||||
/*
|
||||
* Number of transmit control blocks. This determines the number
|
||||
* of transmit buffers that can be chained in the CB list. This
|
||||
* must be a power of two.
|
||||
*/
|
||||
#define FXP_NTXCB 128
|
||||
|
||||
/*
|
||||
* TxCB list index mask. This is used to do list wrap-around.
|
||||
*/
|
||||
#define FXP_TXCB_MASK (FXP_NTXCB - 1)
|
||||
|
||||
/*
|
||||
* Number of receive frame area buffers. These are large, so
|
||||
* choose wisely.
|
||||
*/
|
||||
#define FXP_NRFABUFS 64
|
||||
|
||||
/*
|
||||
* Maximum number of seconds that the reciever can be idle before we
|
||||
* assume it's dead and attempt to reset it by reprogramming the
|
||||
* multicast filter. This is part of a work-around for a bug in the
|
||||
* NIC. See fxp_stats_update().
|
||||
*/
|
||||
#define FXP_MAX_RX_IDLE 15
|
||||
|
||||
/*
|
||||
* Misc. DMA'd data structures are allocated in a single clump, that
|
||||
* maps to a single DMA segment, to make several things easier (computing
|
||||
* offsets, setting up DMA maps, etc.)
|
||||
*/
|
||||
struct fxp_control_data {
|
||||
/*
|
||||
* The transmit control blocks. The first if these
|
||||
* is also used as the config CB.
|
||||
*/
|
||||
struct fxp_cb_tx fcd_txcbs[FXP_NTXCB];
|
||||
|
||||
/*
|
||||
* The multicast setup CB.
|
||||
*/
|
||||
struct fxp_cb_mcs fcd_mcscb;
|
||||
|
||||
/*
|
||||
* The NIC statistics.
|
||||
*/
|
||||
struct fxp_stats fcd_stats;
|
||||
};
|
||||
|
||||
#define FXP_CDOFF(x) offsetof(struct fxp_control_data, x)
|
||||
|
||||
/*
|
||||
* Receive buffer descriptor (software only). This is the analog of
|
||||
* the software portion of the fxp_cb_tx.
|
||||
*/
|
||||
struct fxp_rxdesc {
|
||||
struct fxp_rxdesc *fr_next; /* next in the chain */
|
||||
struct mbuf *fr_mbhead; /* pointer to mbuf chain */
|
||||
bus_dmamap_t fr_dmamap; /* our DMA map */
|
||||
};
|
||||
|
||||
struct fxp_softc {
|
||||
struct device sc_dev; /* generic device structures */
|
||||
void *sc_ih; /* interrupt handler cookie */
|
||||
bus_space_tag_t sc_st; /* bus space tag */
|
||||
bus_space_handle_t sc_sh; /* bus space handle */
|
||||
bus_dma_tag_t sc_dmat; /* bus dma tag */
|
||||
struct ethercom sc_ethercom; /* ethernet common part */
|
||||
#define sc_if sc_ethercom.ec_if
|
||||
|
||||
/*
|
||||
* We create a single DMA map that maps all data structure
|
||||
* overhead, except for RFAs, which are mapped by the
|
||||
* fxp_rxdesc DMA map on a per-mbuf basis.
|
||||
*/
|
||||
bus_dmamap_t sc_dmamap;
|
||||
#define sc_cddma sc_dmamap->dm_segs[0].ds_addr
|
||||
|
||||
/*
|
||||
* These DMA maps map transmit and recieve buffers.
|
||||
*/
|
||||
bus_dmamap_t sc_tx_dmamaps[FXP_NTXCB];
|
||||
bus_dmamap_t sc_rx_dmamaps[FXP_NRFABUFS];
|
||||
|
||||
/*
|
||||
* Control data - TxCBs, stats, etc.
|
||||
*/
|
||||
struct fxp_control_data *control_data;
|
||||
|
||||
struct fxp_rxdesc *sc_rxdescs; /* receive buffer descriptors */
|
||||
struct mii_data sc_mii; /* MII media information */
|
||||
struct fxp_cb_tx *cbl_first; /* first active TxCB in list */
|
||||
struct fxp_cb_tx *cbl_last; /* last active TxCB in list */
|
||||
int tx_queued; /* # of active TxCB's */
|
||||
int need_mcsetup; /* multicast filter needs programming */
|
||||
struct fxp_rxdesc *rfa_head; /* first mbuf in receive frame area */
|
||||
struct fxp_rxdesc *rfa_tail; /* last mbuf in receive frame area */
|
||||
int rx_idle_secs; /* # of seconds RX has been idle */
|
||||
int all_mcasts; /* receive all multicasts */
|
||||
int promisc_mode; /* promiscuous mode enabled */
|
||||
int phy_primary_addr; /* address of primary PHY */
|
||||
int phy_primary_device; /* device type of primary PHY */
|
||||
int phy_10Mbps_only; /* PHY is 10Mbps-only device */
|
||||
#if NRND > 0
|
||||
rndsource_element_t rnd_source; /* random source */
|
||||
#endif
|
||||
};
|
||||
|
||||
/* Macros to ease CSR access. */
|
||||
#define CSR_READ_1(sc, reg) \
|
||||
bus_space_read_1((sc)->sc_st, (sc)->sc_sh, (reg))
|
||||
#define CSR_READ_2(sc, reg) \
|
||||
bus_space_read_2((sc)->sc_st, (sc)->sc_sh, (reg))
|
||||
#define CSR_READ_4(sc, reg) \
|
||||
bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
|
||||
#define CSR_WRITE_1(sc, reg, val) \
|
||||
bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val))
|
||||
#define CSR_WRITE_2(sc, reg, val) \
|
||||
bus_space_write_2((sc)->sc_st, (sc)->sc_sh, (reg), (val))
|
||||
#define CSR_WRITE_4(sc, reg, val) \
|
||||
bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
|
||||
Loading…
Reference in New Issue
Block a user