Do not call printf() from a CPU that is spinning up; defer the probe
messages to cpu_attach() where the boot processor takes care of them. This also necessitates a slight change in the way the FPU name is stored.
This commit is contained in:
pk
parent
4e7849055a
commit
49035b27c8
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@ -1,4 +1,4 @@
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/* $NetBSD: cache.c,v 1.46 1999/01/24 10:11:23 pk Exp $ */
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/* $NetBSD: cache.c,v 1.47 1999/02/27 13:11:22 pk Exp $ */
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/*
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* Copyright (c) 1996
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@ -101,8 +101,6 @@ sun4_cache_enable()
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lduba(AC_SYSENABLE, ASI_CONTROL) | SYSEN_CACHE);
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CACHEINFO.c_enabled = 1;
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printf("cache enabled\n");
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#ifdef notyet
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if (cpuinfo.flags & SUN4_IOCACHE) {
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stba(AC_SYSENABLE, ASI_CONTROL,
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@ -133,8 +131,6 @@ ms1_cache_enable()
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sta(SRMMU_PCR, ASI_SRMMU, pcr | MS1_PCR_DCE | MS1_PCR_ICE);
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CACHEINFO.c_enabled = CACHEINFO.dc_enabled = 1;
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printf("cache enabled\n");
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}
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void
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@ -174,7 +170,6 @@ viking_cache_enable()
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cpuinfo.flags |= CPUFLG_CACHEPAGETABLES; /* Ok to cache PTEs */
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CACHEINFO.ec_enabled = 1;
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}
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printf("cache enabled\n");
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}
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void
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@ -208,6 +203,7 @@ hypersparc_cache_enable()
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pcr |= HYPERSPARC_PCR_CE;
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if (CACHEINFO.c_vactype == VAC_WRITEBACK)
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pcr |= HYPERSPARC_PCR_CM;
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sta(SRMMU_PCR, ASI_SRMMU, pcr);
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CACHEINFO.c_enabled = 1;
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@ -221,8 +217,6 @@ hypersparc_cache_enable()
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*/
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v = HYPERSPARC_ICCR_ICE | (ncpu == 1 ? HYPERSPARC_ICCR_FTD : 0);
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wrasr(v, HYPERSPARC_ASRNUM_ICCR);
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printf("cache enabled\n");
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}
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@ -255,7 +249,6 @@ swift_cache_enable()
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sta(i, ASI_DCACHETAG, 0);
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CACHEINFO.c_enabled = 1;
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printf("cache enabled\n");
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}
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void
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@ -283,7 +276,6 @@ cypress_cache_enable()
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pcr |= CYPRESS_PCR_CM;
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sta(SRMMU_PCR, ASI_SRMMU, pcr);
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CACHEINFO.c_enabled = 1;
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printf("cache enabled\n");
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}
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void
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@ -320,7 +312,6 @@ turbosparc_cache_enable()
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printf("DVMA coherent ");
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CACHEINFO.c_enabled = 1;
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printf("cache enabled\n");
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}
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#endif
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@ -1,4 +1,4 @@
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/* $NetBSD: cpu.c,v 1.87 1999/02/14 12:48:01 pk Exp $ */
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/* $NetBSD: cpu.c,v 1.88 1999/02/27 13:11:21 pk Exp $ */
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/*
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* Copyright (c) 1996
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@ -107,7 +107,7 @@ struct cfattach cpu_ca = {
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sizeof(struct cpu_softc), cpu_match, cpu_attach
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};
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static char *fsrtoname __P((int, int, int, char *));
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static char *fsrtoname __P((int, int, int));
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void cache_print __P((struct cpu_softc *));
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void cpu_setup __P((struct cpu_softc *));
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void cpu_spinup __P((struct cpu_softc *));
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@ -303,6 +303,10 @@ static int cpu_number;
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if (cpi->master) {
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cpu_setup(sc);
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sprintf(cpu_model, "%s @ %s MHz, %s FPU",
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cpi->cpu_name, clockfreq(cpi->hz), cpi->fpu_name);
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printf(": %s\n", cpu_model);
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cache_print(sc);
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return;
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}
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@ -313,6 +317,10 @@ static int cpu_number;
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/* Now start this CPU */
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cpu_spinup(sc);
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printf(": %s @ %s MHz, %s FPU\n", cpi->cpu_name,
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clockfreq(cpi->hz), cpi->fpu_name);
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cache_print(sc);
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if (cpu_number == ncpu) {
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/* Install MP cache flush functions on boot cpu */
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@ -339,34 +347,16 @@ void
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cpu_setup(sc)
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struct cpu_softc *sc;
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{
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char *fpuname;
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char fpbuf[40];
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if (cpuinfo.hotfix)
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(*cpuinfo.hotfix)(&cpuinfo);
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/* Initialize FPU */
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fpu_init(&cpuinfo);
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fpuname = cpuinfo.fpupresent
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? fsrtoname(cpuinfo.cpu_impl, cpuinfo.cpu_vers,
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cpuinfo.fpuvers, fpbuf)
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: "no";
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printf(": %s @ %s MHz, %s FPU\n", cpuinfo.cpu_name,
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clockfreq(cpuinfo.hz), fpuname);
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if (cpuinfo.cacheinfo.c_totalsize != 0)
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cache_print(sc);
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/* Enable the cache */
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cpuinfo.cache_enable();
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if (cpuinfo.master) {
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sprintf(cpu_model, "%s @ %s MHz, %s FPU",
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cpuinfo.cpu_name,
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clockfreq(cpuinfo.hz), fpuname);
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}
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cpu_hatched = 1;
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#if 0
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/* Flush cache line */
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@ -465,6 +455,7 @@ fpu_init(sc)
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struct cpu_info *sc;
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{
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struct fpstate fpstate;
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int fpuvers;
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/*
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* Get the FSR and clear any exceptions. If we do not unload
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@ -479,11 +470,20 @@ fpu_init(sc)
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/* 7 is reserved for "none" */
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fpstate.fs_fsr = 7 << FSR_VER_SHIFT;
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savefpstate(&fpstate);
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sc->fpuvers =
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sc->fpuvers = fpuvers =
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(fpstate.fs_fsr >> FSR_VER_SHIFT) & (FSR_VER >> FSR_VER_SHIFT);
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if (sc->fpuvers != 7)
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sc->fpupresent = 1;
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if (fpuvers == 7) {
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sc->fpu_name = "no";
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return;
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}
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sc->fpupresent = 1;
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sc->fpu_name = fsrtoname(sc->cpu_impl, sc->cpu_vers, fpuvers);
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if (sc->fpu_name == NULL) {
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sprintf(sc->fpu_namebuf, "version 0x%x", fpuvers);
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sc->fpu_name = sc->fpu_namebuf;
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}
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}
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void
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@ -492,12 +492,17 @@ cache_print(sc)
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{
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struct cacheinfo *ci = &sc->sc_cpuinfo->cacheinfo;
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printf("%s:", sc->sc_dv.dv_xname);
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printf("%s: ", sc->sc_dv.dv_xname);
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if (ci->c_totalsize == 0) {
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printf("no cache\n");
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return;
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}
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if (ci->c_split) {
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char *sep = "";
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printf("%s", (ci->c_physical ? " physical " : " "));
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printf("%s", (ci->c_physical ? "physical " : ""));
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if (ci->ic_totalsize > 0) {
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printf("%s%dK instruction (%d b/l)", sep,
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ci->ic_totalsize/1024, ci->ic_linesize);
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@ -509,11 +514,11 @@ cache_print(sc)
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}
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} else if (ci->c_physical) {
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/* combined, physical */
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printf(" physical %dK combined cache (%d bytes/line)",
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printf("physical %dK combined cache (%d bytes/line)",
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ci->c_totalsize/1024, ci->c_linesize);
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} else {
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/* combined, virtual */
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printf(" %dK byte write-%s, %d bytes/line, %cw flush",
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printf("%dK byte write-%s, %d bytes/line, %cw flush",
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ci->c_totalsize/1024,
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(ci->c_vactype == VAC_WRITETHROUGH) ? "through" : "back",
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ci->c_linesize,
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@ -525,6 +530,9 @@ cache_print(sc)
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ci->ec_totalsize/1024, ci->ec_linesize);
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}
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printf(": ");
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if (ci->c_enabled)
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printf("cache enabled");
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printf("\n");
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}
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@ -1109,6 +1117,7 @@ cpumatch_hypersparc(sc, mp, node)
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int node;
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{
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sc->cpu_type = CPUTYP_HS_MBUS;/*XXX*/
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sc->flags |= CPUFLG_CACHE_MANDATORY;
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if (node == 0)
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sta(0, ASI_HICACHECLR, 0);
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printf("warning: hypersparc support still under construction\n");
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@ -1485,17 +1494,16 @@ static struct info fpu_types[] = {
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};
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static char *
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fsrtoname(impl, vers, fver, buf)
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register int impl, vers, fver;
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char *buf;
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fsrtoname(impl, vers, fver)
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int impl, vers, fver;
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{
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register struct info *p;
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struct info *p;
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for (p = fpu_types; p->valid; p++)
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for (p = fpu_types; p->valid; p++) {
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if (p->iu_impl == impl &&
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(p->iu_vers == vers || p->iu_vers == ANY) &&
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(p->fpu_vers == fver))
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return (p->name);
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sprintf(buf, "version 0x%x", fver);
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return (buf);
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}
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return (NULL);
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}
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@ -1,4 +1,4 @@
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/* $NetBSD: cpuvar.h,v 1.20 1998/10/24 08:12:55 pk Exp $ */
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/* $NetBSD: cpuvar.h,v 1.21 1999/02/27 13:11:21 pk Exp $ */
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/*
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* Copyright (c) 1996 The NetBSD Foundation, Inc.
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@ -178,6 +178,8 @@ struct cpu_info {
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/* FPU information */
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int fpupresent; /* true if FPU is present */
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int fpuvers; /* FPU revision */
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char *fpu_name; /* FPU model */
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char fpu_namebuf[32];/* Buffer for FPU name, if necessary */
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/* various flags to workaround anomalies in chips */
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int flags; /* see CPUFLG_xxx, below */
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