clean up some more confusion between (ws)displays and CRTCs.
Now palette initialization no longer stomps over the port table, which gives us a fighting chance to intentionally enable the right outputs. How on earth did this ever work?
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macallan
parent
ebfcd7f4ed
commit
48a7caff44
@ -1,4 +1,4 @@
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/* $NetBSD: radeonfb.c,v 1.69 2012/12/30 09:45:05 macallan Exp $ */
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/* $NetBSD: radeonfb.c,v 1.70 2012/12/31 10:31:19 macallan Exp $ */
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/*-
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* Copyright (c) 2006 Itronix Inc.
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@ -70,7 +70,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: radeonfb.c,v 1.69 2012/12/30 09:45:05 macallan Exp $");
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__KERNEL_RCSID(0, "$NetBSD: radeonfb.c,v 1.70 2012/12/31 10:31:19 macallan Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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@ -131,7 +131,7 @@ static void radeonfb_modeswitch(struct radeonfb_display *);
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static void radeonfb_setcrtc(struct radeonfb_display *, int);
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static void radeonfb_init_misc(struct radeonfb_softc *);
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static void radeonfb_set_fbloc(struct radeonfb_softc *);
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static void radeonfb_init_palette(struct radeonfb_softc *, int);
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static void radeonfb_init_palette(struct radeonfb_display *);
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static void radeonfb_r300cg_workaround(struct radeonfb_softc *);
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static int radeonfb_isblank(struct radeonfb_display *);
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@ -645,9 +645,6 @@ radeonfb_attach(device_t parent, device_t dev, void *aux)
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radeonfb_init_misc(sc);
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radeonfb_init_palette(sc, 0);
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if (HAS_CRTC2(sc))
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radeonfb_init_palette(sc, 1);
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/* program the DAC wirings */
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for (i = 0; i < (HAS_CRTC2(sc) ? 2 : 1); i++) {
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@ -668,7 +665,7 @@ radeonfb_attach(device_t parent, device_t dev, void *aux)
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i ? 0 : RADEON_CRT2_DISP1_SEL,
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~RADEON_CRT2_DISP1_SEL);
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/* we're using CRTC2 for the 2nd port */
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if (sc->sc_ports[i].rp_number == 99) {
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if (sc->sc_ports[i].rp_number == 1) {
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PATCH32(sc, RADEON_DISP_OUTPUT_CNTL,
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RADEON_DISP_DAC2_SOURCE_CRTC2,
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~RADEON_DISP_DAC2_SOURCE_MASK);
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@ -676,9 +673,13 @@ radeonfb_attach(device_t parent, device_t dev, void *aux)
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break;
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}
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DPRINTF(("%s: port %d tmds type %d\n", __func__, i,
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sc->sc_ports[i].rp_tmds_type));
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switch (sc->sc_ports[i].rp_tmds_type) {
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case RADEON_TMDS_INT:
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/* point FP0 at the CRTC this port uses */
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DPRINTF(("%s: plugging internal TMDS into CRTC %d\n",
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__func__, sc->sc_ports[i].rp_number));
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if (IS_R300(sc)) {
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PATCH32(sc, RADEON_FP_GEN_CNTL,
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sc->sc_ports[i].rp_number ?
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@ -973,16 +974,13 @@ radeonfb_attach(device_t parent, device_t dev, void *aux)
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radeonfb_set_backlight(dp, dp->rd_bl_level);
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}
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/*
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* if we have console output via firmware like on sparc64 it may
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* interfere with DAC programming so program the palette again
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* here after we took over
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*/
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radeonfb_init_palette(sc, 0);
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for (i = i; i < RADEON_NDISPLAYS; i++)
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radeonfb_init_palette(&sc->sc_displays[i]);
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if (HAS_CRTC2(sc)) {
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radeonfb_init_palette(sc, 1);
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CLR32(sc, RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_DISP_DIS);
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}
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CLR32(sc, RADEON_CRTC_EXT_CNTL, RADEON_CRTC_DISPLAY_DIS);
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SET32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_FPON);
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pmf_event_register(dev, PMFE_DISPLAY_BRIGHTNESS_UP,
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@ -1121,7 +1119,7 @@ radeonfb_ioctl(void *v, void *vs,
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radeonfb_map(sc);
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radeonfb_engine_init(dp);
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glyphcache_wipe(&dp->rd_gc);
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radeonfb_init_palette(sc, dp == &sc->sc_displays[0] ? 0 : 1);
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radeonfb_init_palette(dp);
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radeonfb_modeswitch(dp);
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vcons_redraw_screen(dp->rd_vd.active);
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} else {
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@ -1754,7 +1752,7 @@ nobios:
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sc->sc_ports[1].rp_ddc_type = RADEON_DDC_VGA;
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sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY;
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sc->sc_ports[1].rp_conn_type = RADEON_CONN_CRT;
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sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_EXT;
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sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_UNKNOWN;
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sc->sc_ports[1].rp_number = 0;
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}
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}
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@ -2535,10 +2533,12 @@ radeonfb_init_misc(struct radeonfb_softc *sc)
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* This loads a linear color map for true color.
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*/
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void
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radeonfb_init_palette(struct radeonfb_softc *sc, int crtc)
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radeonfb_init_palette(struct radeonfb_display *dp)
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{
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int i;
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struct radeonfb_softc *sc = dp->rd_softc;
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int i, cc;
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uint32_t vclk;
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int crtc;
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#define DAC_WIDTH ((1 << 10) - 1)
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#define CLUT_WIDTH ((1 << 8) - 1)
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@ -2547,50 +2547,57 @@ radeonfb_init_palette(struct radeonfb_softc *sc, int crtc)
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vclk = GETPLL(sc, RADEON_VCLK_ECP_CNTL);
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PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk & ~RADEON_PIXCLK_DAC_ALWAYS_ONb);
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if (crtc)
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SET32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL);
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else
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CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL);
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/* initialize the palette for every CRTC used by this display */
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for (cc = 0; cc < dp->rd_ncrtcs; cc++) {
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crtc = dp->rd_crtcs[cc].rc_number;
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PUT32(sc, RADEON_PALETTE_INDEX, 0);
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if (sc->sc_displays[crtc].rd_bpp == 0)
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sc->sc_displays[crtc].rd_bpp = RADEONFB_DEFAULT_DEPTH;
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if (crtc)
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SET32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL);
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else
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CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL);
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if (sc->sc_displays[crtc].rd_bpp == 8) {
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/* ANSI palette */
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int j = 0;
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uint32_t tmp, r, g, b;
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PUT32(sc, RADEON_PALETTE_INDEX, 0);
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for (i = 0; i <= CLUT_WIDTH; ++i) {
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tmp = i & 0xe0;
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/*
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* replicate bits so 0xe0 maps to a red value of 0xff
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* in order to make white look actually white
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*/
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tmp |= (tmp >> 3) | (tmp >> 6);
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r = tmp;
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if (dp->rd_bpp == 0)
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dp->rd_bpp = RADEONFB_DEFAULT_DEPTH;
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tmp = (i & 0x1c) << 3;
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tmp |= (tmp >> 3) | (tmp >> 6);
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g = tmp;
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if (dp->rd_bpp == 8) {
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/* ANSI palette */
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int j = 0;
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uint32_t tmp, r, g, b;
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tmp = (i & 0x03) << 6;
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tmp |= tmp >> 2;
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tmp |= tmp >> 4;
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b = tmp;
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PUT32(sc, RADEON_PALETTE_30_DATA,
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(r << 22) |
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(g << 12) |
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(b << 2));
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j += 3;
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}
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} else {
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/* linear ramp */
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for (i = 0; i <= CLUT_WIDTH; ++i) {
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PUT32(sc, RADEON_PALETTE_30_DATA,
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(CLUT_COLOR(i) << 10) |
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(CLUT_COLOR(i) << 20) |
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(CLUT_COLOR(i)));
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for (i = 0; i <= CLUT_WIDTH; ++i) {
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tmp = i & 0xe0;
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/*
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* replicate bits so 0xe0 maps to a red value of 0xff
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* in order to make white look actually white
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*/
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tmp |= (tmp >> 3) | (tmp >> 6);
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r = tmp;
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tmp = (i & 0x1c) << 3;
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tmp |= (tmp >> 3) | (tmp >> 6);
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g = tmp;
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tmp = (i & 0x03) << 6;
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tmp |= tmp >> 2;
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tmp |= tmp >> 4;
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b = tmp;
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PUT32(sc, RADEON_PALETTE_30_DATA,
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(r << 22) |
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(g << 12) |
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(b << 2));
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j += 3;
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}
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} else {
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/* linear ramp */
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for (i = 0; i <= CLUT_WIDTH; ++i) {
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PUT32(sc, RADEON_PALETTE_30_DATA,
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(CLUT_COLOR(i) << 10) |
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(CLUT_COLOR(i) << 20) |
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(CLUT_COLOR(i)));
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}
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}
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}
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