Implement workaround for:
arm11 Errata 364296:Possible Cache Data Corruption with Hit-Under-Miss Remove hack in userret which is redundant with workaround. workaround code from <imre.deak@teleca.com>
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matt
parent
eb096a3c19
commit
4886aa3da7
@ -1,4 +1,4 @@
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/* $NetBSD: ast.c,v 1.14 2008/04/27 18:58:43 matt Exp $ */
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/* $NetBSD: ast.c,v 1.15 2008/07/22 07:07:23 matt Exp $ */
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/*
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* Copyright (c) 1994,1995 Mark Brinicombe
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@ -41,7 +41,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: ast.c,v 1.14 2008/04/27 18:58:43 matt Exp $");
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__KERNEL_RCSID(0, "$NetBSD: ast.c,v 1.15 2008/07/22 07:07:23 matt Exp $");
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#include "opt_ddb.h"
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@ -74,23 +74,8 @@ void ast(struct trapframe *);
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void
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userret(struct lwp *l)
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{
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#ifdef CPU_ARM11
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struct cpu_info * const ci = curcpu();
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#endif
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/* Invoke MI userret code */
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mi_userret(l);
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#ifdef CPU_ARM11
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/*
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* This is a hack to work around an unknown cache bug on the ARM11
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* Before returning we clean the data cache.
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*/
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if (ci->ci_arm_cputype == CPU_ID_ARM1136JS
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|| ci->ci_arm_cputype == CPU_ID_ARM1136JSR1) {
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__asm("mcr\tp15, 0, %0, c7, c10, 0" :: "r"(0));
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}
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#endif
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}
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@ -120,7 +105,7 @@ ast(struct trapframe *tf)
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#ifdef DEBUG
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if (l == NULL)
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panic("ast: no curlwp!");
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if (&l->l_addr->u_pcb == 0)
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if (&l->l_addr->u_pcb == NULL)
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panic("ast: no pcb!");
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#endif
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@ -1,4 +1,4 @@
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/* $NetBSD: cpufunc.c,v 1.85 2008/07/13 09:12:14 chris Exp $ */
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/* $NetBSD: cpufunc.c,v 1.86 2008/07/22 07:07:23 matt Exp $ */
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/*
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* arm7tdmi support code Copyright (c) 2001 John Fremlin
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@ -47,7 +47,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.85 2008/07/13 09:12:14 chris Exp $");
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__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.86 2008/07/22 07:07:23 matt Exp $");
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#include "opt_compat_netbsd.h"
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#include "opt_cpuoptions.h"
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@ -2367,7 +2367,10 @@ void
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arm1136_setup(char *args)
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{
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int cpuctrl, cpuctrl_wax;
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uint32_t auxctrl, auxctrl_wax;
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uint32_t tmp, tmp2;
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uint32_t sbz=0;
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uint32_t cpuid;
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#if defined(PROCESS_ID_IS_CURCPU)
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/* set curcpu() */
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@ -2377,6 +2380,8 @@ arm1136_setup(char *args)
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__asm("mcr\tp15, 0, %0, c13, c0, 4" : : "r"(&lwp0));
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#endif
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cpuid = cpu_id();
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cpuctrl =
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CPU_CONTROL_MMU_ENABLE |
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CPU_CONTROL_DC_ENABLE |
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@ -2412,6 +2417,22 @@ arm1136_setup(char *args)
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if (vector_page == ARM_VECTORS_HIGH)
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cpuctrl |= CPU_CONTROL_VECRELOC;
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auxctrl = 0;
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auxctrl_wax = ~0;
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/* This options enables the workaround for the 364296 ARM1136
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* r0pX errata (possible cache data corruption with
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* hit-under-miss enabled). It sets the undocumented bit 31 in
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* the auxiliary control register and the FI bit in the control
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* register, thus disabling hit-under-miss without putting the
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* processor into full low interrupt latency mode. ARM11MPCore
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* is not affected.
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*/
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if ((cpuid & CPU_ID_CPU_MASK) == CPU_ID_ARM1136JS) { /* ARM1136JSr0pX */
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cpuctrl |= CPU_CONTROL_FI_ENABLE;
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auxctrl = ARM11R0_AUXCTL_PFI;
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auxctrl_wax = ~ARM11R0_AUXCTL_PFI;
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}
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/* Clear out the cache */
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cpu_idcache_wbinv_all();
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@ -2422,6 +2443,14 @@ arm1136_setup(char *args)
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curcpu()->ci_ctrl = cpuctrl;
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cpu_control(~cpuctrl_wax, cpuctrl);
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__asm volatile ("mrc p15, 0, %0, c1, c0, 1\n\t"
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"bic %1, %0, %2\n\t"
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"eor %1, %0, %3\n\t"
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"teq %0, %1\n\t"
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"mcrne p15, 0, %1, c1, c0, 1\n\t"
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: "=r"(tmp), "=r"(tmp2) :
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"r"(~auxctrl_wax), "r"(auxctrl));
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/* And again. */
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cpu_idcache_wbinv_all();
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}
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@ -1,4 +1,4 @@
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/* $NetBSD: armreg.h,v 1.38 2008/04/27 18:58:44 matt Exp $ */
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/* $NetBSD: armreg.h,v 1.39 2008/07/22 07:07:23 matt Exp $ */
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/*
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* Copyright (c) 1998, 2001 Ben Harris
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@ -292,9 +292,18 @@
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#define CPU_CONTROL_V4COMPAT 0x00008000 /* L4: ARMv4 compat LDR R15 etc */
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#define CPU_CONTROL_UNAL_ENABLE 0x00040000 /* U: unaligned data access */
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#define CPU_CONTROL_XP_ENABLE 0x00080000 /* XP: extended page table */
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#define CPU_CONTROL_FI_ENABLE 0x00200000 /* FI: Low interrupt latency */
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#define CPU_CONTROL_IDC_ENABLE CPU_CONTROL_DC_ENABLE
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/* ARM11r0 Auxillary Control Register (CP15 register 1, opcode2 1) */
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#define ARM11R0_AUXCTL_PFI 0x80000000 /* PFI: partial FI mode. */
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/* This is an undocumented flag
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* used to work around a cache bug
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* in r0 steppings. See errata
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* 364296.
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*/
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/* XScale Auxillary Control Register (CP15 register 1, opcode2 1) */
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#define XSCALE_AUXCTL_K 0x00000001 /* dis. write buffer coalescing */
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#define XSCALE_AUXCTL_P 0x00000002 /* ECC protect page table access */
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