More changes to the "new" ncr interrupt driven scsi driver (from M. Pfaller)
Bring back the old polled driver until a kernel built with the interrupt driven one is stable enough for production use.
This commit is contained in:
phil
parent
32b3e66891
commit
47ff5d6b3d
File diff suppressed because it is too large
Load Diff
1721
sys/arch/pc532/dev/ncr5380.c
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1721
sys/arch/pc532/dev/ncr5380.c
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File diff suppressed because it is too large
Load Diff
241
sys/arch/pc532/dev/ncr5380reg.h
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241
sys/arch/pc532/dev/ncr5380reg.h
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/* $NetBSD: ncr5380reg.h,v 1.1 1995/08/25 07:30:36 phil Exp $ */
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/*
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* Copyright (c) 1995 Leo Weppelman.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
|
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Leo Weppelman.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _NCR5380REG_H
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#define _NCR5380REG_H
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/*
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* NCR5380 common interface definitions.
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*/
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/*
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* Register numbers: (first argument to GET/SET_5380_REG )
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*/
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#define NCR5380_DATA 0 /* Data register */
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#define NCR5380_ICOM 1 /* Initiator command register */
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#define NCR5380_MODE 2 /* Mode register */
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#define NCR5380_TCOM 3 /* Target command register */
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#define NCR5380_IDSTAT 4 /* Bus status register */
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#define NCR5380_DMSTAT 5 /* DMA status register */
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#define NCR5380_TRCV 6 /* Target receive register */
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#define NCR5380_IRCV 7 /* Initiator receive register */
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/*
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* Definitions for Initiator command register.
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*/
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#define SC_A_RST 0x80 /* RW - Assert RST */
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#define SC_TEST 0x40 /* W - Test mode */
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#define SC_AIP 0x40 /* R - Arbitration in progress */
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#define SC_LA 0x20 /* R - Lost arbitration */
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#define SC_A_ACK 0x10 /* RW - Assert ACK */
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#define SC_A_BSY 0x08 /* RW - Assert BSY */
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#define SC_A_SEL 0x04 /* RW - Assert SEL */
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#define SC_A_ATN 0x02 /* RW - Assert ATN */
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#define SC_ADTB 0x01 /* RW - Assert Data To Bus */
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/*
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* Definitions for mode register
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*/
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#define SC_B_DMA 0x80 /* RW - Block mode DMA (not on TT!) */
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#define SC_T_MODE 0x40 /* RW - Target mode */
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#define SC_E_PAR 0x20 /* RW - Enable parity check */
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#define SC_E_PARI 0x10 /* RW - Enable parity interrupt */
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#define SC_E_EOPI 0x08 /* RW - Enable End Of Process Interrupt */
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#define SC_MON_BSY 0x04 /* RW - Monitor BSY */
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#define SC_M_DMA 0x02 /* RW - Set DMA mode */
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#define SC_ARBIT 0x01 /* RW - Arbitrate */
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/*
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* Definitions for tcom register
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*/
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#define SC_LBS 0x80 /* RW - Last Byte Send (not on TT!) */
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#define SC_A_REQ 0x08 /* RW - Assert REQ */
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#define SC_A_MSG 0x04 /* RW - Assert MSG */
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#define SC_A_CD 0x02 /* RW - Assert C/D */
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#define SC_A_IO 0x01 /* RW - Assert I/O */
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/*
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* Definitions for idstat register
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*/
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#define SC_S_RST 0x80 /* R - RST is set */
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#define SC_S_BSY 0x40 /* R - BSY is set */
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#define SC_S_REQ 0x20 /* R - REQ is set */
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#define SC_S_MSG 0x10 /* R - MSG is set */
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#define SC_S_CD 0x08 /* R - C/D is set */
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#define SC_S_IO 0x04 /* R - I/O is set */
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#define SC_S_SEL 0x02 /* R - SEL is set */
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#define SC_S_PAR 0x01 /* R - Parity bit */
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/*
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* Definitions for dmastat register
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*/
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#define SC_END_DMA 0x80 /* R - End of DMA */
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#define SC_DMA_REQ 0x40 /* R - DMA request */
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#define SC_PAR_ERR 0x20 /* R - Parity error */
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#define SC_IRQ_SET 0x10 /* R - IRQ is active */
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#define SC_PHS_MTCH 0x08 /* R - Phase Match */
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#define SC_BSY_ERR 0x04 /* R - Busy error */
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#define SC_ATN_STAT 0x02 /* R - State of ATN line */
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#define SC_ACK_STAT 0x01 /* R - State of ACK line */
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#define SC_S_SEND 0x00 /* W - Start DMA output */
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#define SC_CLINT { /* Clear interrupts */ \
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int i = GET_5380_REG(NCR5380_IRCV); \
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}
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/*
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* Definition of SCSI-bus phases. The values are determined by signals
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* on the SCSI-bus. DO NOT CHANGE!
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* The values must be used to index the pointers in SCSI-PARMS.
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*/
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#define NR_PHASE 8
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#define PH_DATAOUT 0
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#define PH_DATAIN 1
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#define PH_CMD 2
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#define PH_STATUS 3
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#define PH_RES1 4
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#define PH_RES2 5
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#define PH_MSGOUT 6
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#define PH_MSGIN 7
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#define PH_OUT(phase) (!(phase & 1)) /* TRUE if output phase */
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#define PH_IN(phase) (phase & 1) /* TRUE if input phase */
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/*
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* Id of Host-adapter
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*/
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#define SC_HOST_ID 0x80
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/*
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* Base setting for 5380 mode register
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*/
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#define IMODE_BASE SC_E_PAR
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/*
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* SCSI completion status codes, should move to sys/scsi/????
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*/
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#define SCSMASK 0x1e /* status code mask */
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#define SCSGOOD 0x00 /* good status */
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#define SCSCHKC 0x02 /* check condition */
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#define SCSBUSY 0x08 /* busy status */
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#define SCSCMET 0x04 /* condition met / good */
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/*
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* Return values of check_intr()
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*/
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#define INTR_SPURIOUS 0
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#define INTR_RESEL 2
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#define INTR_DMA 3
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struct ncr_softc {
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struct device sc_dev;
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struct scsi_link sc_link;
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};
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/*
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* Max. number of dma-chains per request
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*/
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#define MAXDMAIO (MAXPHYS/NBPG + 1)
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/*
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* Some requests are not contiguous in physical memory. We need to break them
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* up into contiguous parts for DMA.
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*/
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struct dma_chain {
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u_int dm_count;
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u_long dm_addr;
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};
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/*
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* Define our issue, free and disconnect queue's.
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*/
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typedef struct req_q {
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struct req_q *next; /* next in free, issue or discon queue */
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struct req_q *link; /* next linked command to execute */
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struct scsi_xfer *xs; /* request from high-level driver */
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u_char dr_flag; /* driver state */
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u_char phase; /* current SCSI phase */
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u_char msgout; /* message to send when requested */
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u_char targ_id; /* target for command */
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u_char targ_lun; /* lun for command */
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u_char status; /* returned status byte */
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u_char message; /* returned message byte */
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struct dma_chain dm_chain[MAXDMAIO];
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struct dma_chain *dm_cur; /* current dma-request */
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struct dma_chain *dm_last; /* last dma-request */
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long xdata_len; /* length of transfer */
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u_char *xdata_ptr; /* physical address of transfer */
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struct scsi_generic xcmd; /* command to execute */
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} SC_REQ;
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/*
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* Values for dr_flag:
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*/
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#define DRIVER_IN_DMA 1 /* Non-polled DMA activated */
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#define DRIVER_AUTOSEN 2 /* Doing automatic sense */
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#define DRIVER_NOINT 4 /* We are booting: no interrupts */
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#define DRIVER_DMAOK 8 /* DMA can be used on this request */
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/* XXX: Should go to ncr5380var.h */
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static SC_REQ *issue_q = NULL; /* Commands waiting to be issued*/
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static SC_REQ *discon_q = NULL; /* Commands disconnected */
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static SC_REQ *connected = NULL; /* Command currently connected */
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/*
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* Function decls:
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*/
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static int transfer_pio __P((u_char *, u_char *, u_long *));
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static int wait_req_true __P((void));
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static int wait_req_false __P((void));
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static int scsi_select __P((SC_REQ *, int));
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static int handle_message __P((SC_REQ *, u_int));
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static int information_transfer __P((void));
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static void reselect __P((struct ncr_softc *));
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static int dma_ready __P((void));
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static void transfer_dma __P((SC_REQ *, u_int, int));
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static int check_autosense __P((SC_REQ *, int));
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static int reach_msg_out __P((struct ncr_softc *, u_long));
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static int check_intr __P((struct ncr_softc *));
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static void scsi_reset __P((struct ncr_softc *));
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static int scsi_dmaok __P((SC_REQ *));
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static void run_main __P((struct ncr_softc *));
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static void scsi_main __P((struct ncr_softc *));
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static void ncr_ctrl_intr __P((struct ncr_softc *));
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static void ncr_dma_intr __P((struct ncr_softc *));
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static void ncr_tprint __P((SC_REQ *, char *, ...));
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static void ncr_aprint __P((struct ncr_softc *, char *, ...));
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static void show_request __P((SC_REQ *, char *));
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static void show_phase __P((SC_REQ *, int));
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static void show_signals __P((void));
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#endif /* _NCR5380REG_H */
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145
sys/arch/pc532/dev/ncr_5380.h
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145
sys/arch/pc532/dev/ncr_5380.h
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@ -0,0 +1,145 @@
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/* $NetBSD: ncr_5380.h,v 1.4 1995/08/25 07:30:37 phil Exp $ */
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/*
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* Mach Operating System
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* Copyright (c) 1991,1990,1989 Carnegie Mellon University
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* All Rights Reserved.
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*
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* Permission to use, copy, modify and distribute this software and its
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* documentation is hereby granted, provided that both the copyright
|
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* notice and this permission notice appear in all copies of the
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* software, derivative works or modified versions, and any portions
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* thereof, and that both notices appear in supporting documentation.
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*
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* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS
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* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
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* ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
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*
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* Carnegie Mellon requests users of this software to return to
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*
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* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
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* School of Computer Science
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* Carnegie Mellon University
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* Pittsburgh PA 15213-3890
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*
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* any improvements or extensions that they make and grant Carnegie the
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* rights to redistribute these changes.
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*/
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/*
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* File: scsi_5380.h
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* Author: Alessandro Forin, Carnegie Mellon University
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* Date: 5/91
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*
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* Defines for the NCR 5380 (SCSI chip), aka Am5380
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*
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* Modified for the pc532 by Phil Nelson. 1/94
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*/
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/*
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* Register map
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*/
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typedef struct {
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volatile unsigned char sci_data; /* r: Current data */
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#define sci_odata sci_data /* w: Out data */
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volatile unsigned char sci_icmd; /* rw: Initiator command */
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volatile unsigned char sci_mode; /* rw: Mode */
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volatile unsigned char sci_tcmd; /* rw: Target command */
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volatile unsigned char sci_bus_csr; /* r: Bus Status */
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#define sci_sel_enb sci_bus_csr /* w: Select enable */
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volatile unsigned char sci_csr; /* r: Status */
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#define sci_dma_send sci_csr /* w: Start dma send data */
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volatile unsigned char sci_idata; /* r: Input data */
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#define sci_trecv sci_idata /* w: Start dma receive, target */
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volatile unsigned char sci_iack; /* r: Interrupt Acknowledge */
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#define sci_irecv sci_iack /* w: Start dma receive, initiator */
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} sci_regmap_t;
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/*
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* Initiator command register
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*/
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#define SCI_ICMD_DATA 0x01 /* rw: Assert data bus */
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#define SCI_ICMD_ATN 0x02 /* rw: Assert ATN signal */
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#define SCI_ICMD_SEL 0x04 /* rw: Assert SEL signal */
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#define SCI_ICMD_BSY 0x08 /* rw: Assert BSY signal */
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#define SCI_ICMD_ACK 0x10 /* rw: Assert ACK signal */
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#define SCI_ICMD_LST 0x20 /* r: Lost arbitration */
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#define SCI_ICMD_DIFF SCI_ICMD_LST /* w: Differential cable */
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#define SCI_ICMD_AIP 0x40 /* r: Arbitration in progress */
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#define SCI_ICMD_TEST SCI_ICMD_AIP /* w: Test mode */
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#define SCI_ICMD_RST 0x80 /* rw: Assert RST signal */
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/*
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* Mode register
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*/
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#define SCI_MODE_ARB 0x01 /* rw: Start arbitration */
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#define SCI_MODE_DMA 0x02 /* rw: Enable DMA xfers */
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#define SCI_MODE_MONBSY 0x04 /* rw: Monitor BSY signal */
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#define SCI_MODE_DMA_IE 0x08 /* rw: Enable DMA complete interrupt */
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#define SCI_MODE_PERR_IE 0x10 /* rw: Interrupt on parity errors */
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#define SCI_MODE_PAR_CHK 0x20 /* rw: Check parity */
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#define SCI_MODE_TARGET 0x40 /* rw: Target mode (Initiator if 0) */
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#define SCI_MODE_BLOCKDMA 0x80 /* rw: Block-mode DMA handshake (MBZ) */
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/*
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* Target command register
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*/
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#define SCI_TCMD_IO 0x01 /* rw: Assert I/O signal */
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#define SCI_TCMD_CD 0x02 /* rw: Assert C/D signal */
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#define SCI_TCMD_MSG 0x04 /* rw: Assert MSG signal */
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#define SCI_TCMD_PHASE_MASK 0x07 /* r: Mask for current bus phase */
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#define SCI_TCMD_REQ 0x08 /* rw: Assert REQ signal */
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#define SCI_TCMD_LAST_SENT 0x80 /* ro: Last byte was xferred
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* (not on 5380/1) */
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#define SCI_PHASE(x) SCSI_PHASE(x)
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/*
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* Current (SCSI) Bus status
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*/
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#define SCI_BUS_DBP 0x01 /* r: Data Bus parity */
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#define SCI_BUS_SEL 0x02 /* r: SEL signal */
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#define SCI_BUS_IO 0x04 /* r: I/O signal */
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#define SCI_BUS_CD 0x08 /* r: C/D signal */
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#define SCI_BUS_MSG 0x10 /* r: MSG signal */
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#define SCI_BUS_REQ 0x20 /* r: REQ signal */
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#define SCI_BUS_BSY 0x40 /* r: BSY signal */
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#define SCI_BUS_RST 0x80 /* r: RST signal */
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#define SCI_CUR_PHASE(x) SCSI_PHASE((x)>>2)
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/*
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* Bus and Status register
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||||
*/
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||||
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#define SCI_CSR_ACK 0x01 /* r: ACK signal */
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#define SCI_CSR_ATN 0x02 /* r: ATN signal */
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#define SCI_CSR_DISC 0x04 /* r: Disconnected (BSY==0) */
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#define SCI_CSR_PHASE_MATCH 0x08 /* r: Bus and SCI_TCMD match */
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#define SCI_CSR_INT 0x10 /* r: Interrupt request */
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#define SCI_CSR_PERR 0x20 /* r: Parity error */
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#define SCI_CSR_DREQ 0x40 /* r: DMA request */
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#define SCI_CSR_DONE 0x80 /* r: DMA count is zero */
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/* icu scsi chip switching */
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#define ICU_ADR 0xfffffe00
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#define ICU_IO (ICU_ADR+20)
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#define ICU_DIR (ICU_ADR+21)
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#define ICU_DATA (ICU_ADR+19)
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#define ICU_SCSI_BIT 0x80
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57
sys/arch/pc532/dev/ncr_defs.h
Normal file
57
sys/arch/pc532/dev/ncr_defs.h
Normal file
@ -0,0 +1,57 @@
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/* $NetBSD: ncr_defs.h,v 1.4 1995/08/25 07:30:39 phil Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (C) 1993 Allen K. Briggs, Chris P. Caputo,
|
||||
* Michael L. Finch, Bradley A. Grantham, and
|
||||
* Lawrence A. Kesteloot
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed by the Alice Group.
|
||||
* 4. The names of the Alice Group or any of its members may not be used
|
||||
* to endorse or promote products derived from this software without
|
||||
* specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE ALICE GROUP ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL THE ALICE GROUP BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _SCSI_DEFS_H
|
||||
#define _SCSI_DEFS_H
|
||||
|
||||
#define SCSI_PHASE_DATA_OUT 0x0
|
||||
#define SCSI_PHASE_DATA_IN 0x1
|
||||
#define SCSI_PHASE_CMD 0x2
|
||||
#define SCSI_PHASE_STATUS 0x3
|
||||
#define SCSI_PHASE_UNSPEC1 0x4
|
||||
#define SCSI_PHASE_UNSPEC2 0x5
|
||||
#define SCSI_PHASE_MESSAGE_OUT 0x6
|
||||
#define SCSI_PHASE_MESSAGE_IN 0x7
|
||||
|
||||
#define SCSI_PHASE(x) ((x)&0x7)
|
||||
|
||||
/* These should be fixed up. */
|
||||
|
||||
#define SCSI_RET_SUCCESS 0
|
||||
#define SCSI_RET_RETRY 1
|
||||
#define SCSI_RET_DEVICE_DOWN 2
|
||||
#define SCSI_RET_COMMAND_FAIL 3
|
||||
|
||||
#endif
|
||||
@ -1,8 +1,7 @@
|
||||
/* $NetBSD: ncrreg.h,v 1.1 1995/06/09 04:36:26 phil Exp $ */
|
||||
/* $NetBSD: ncrreg.h,v 1.2 1995/08/25 07:30:40 phil Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1995 Leo Weppelman.
|
||||
* PC532-Port by Matthias Pfaller.
|
||||
* Copyright (c) 1994 Matthias Pfaller.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
@ -15,7 +14,7 @@
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed by Leo Weppelman.
|
||||
* This product includes software developed by Matthias Pfaller.
|
||||
* 4. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission
|
||||
*
|
||||
@ -29,117 +28,35 @@
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* $Id: ncrreg.h,v 1.2 1995/08/25 07:30:40 phil Exp $
|
||||
*/
|
||||
|
||||
#ifndef _NCR5380REG_H
|
||||
#define _NCR5380REG_H
|
||||
#ifndef _NCRREG_H
|
||||
#define _NCRREG_H
|
||||
|
||||
#define PDMA_ADDRESS ((volatile u_char *) 0xffe00000)
|
||||
#define SCSI_5380 ((volatile struct scsi_5380 *) 0xffd00000)
|
||||
#define NCR5380 ((volatile struct ncr5380 *) 0xffd00000)
|
||||
|
||||
struct scsi_5380 {
|
||||
volatile u_char scsi_5380[8]; /* use only the odd bytes */
|
||||
struct ncr5380 {
|
||||
volatile u_char regs[8]; /* use only the odd bytes */
|
||||
};
|
||||
|
||||
#define scsi_data scsi_5380[0] /* Data register */
|
||||
#define scsi_icom scsi_5380[1] /* Initiator command register */
|
||||
#define scsi_mode scsi_5380[2] /* Mode register */
|
||||
#define scsi_tcom scsi_5380[3] /* Target command register */
|
||||
#define scsi_idstat scsi_5380[4] /* Bus status register */
|
||||
#define scsi_dmstat scsi_5380[5] /* DMA status register */
|
||||
#define scsi_trcv scsi_5380[6] /* Target receive register */
|
||||
#define scsi_ircv scsi_5380[7] /* Initiator receive register */
|
||||
#define ncr_data regs[0] /* Data register */
|
||||
#define ncr_icom regs[1] /* Initiator command register */
|
||||
#define ncr_mode regs[2] /* Mode register */
|
||||
#define ncr_tcom regs[3] /* Target command register */
|
||||
#define ncr_idstat regs[4] /* Bus status register */
|
||||
#define ncr_dmstat regs[5] /* DMA status register */
|
||||
#define ncr_trcv regs[6] /* Target receive register */
|
||||
#define ncr_ircv regs[7] /* Initiator receive register */
|
||||
|
||||
/*
|
||||
* Definitions for Initiator command register.
|
||||
*/
|
||||
#define SC_A_RST 0x80 /* RW - Assert RST */
|
||||
#define SC_TEST 0x40 /* W - Test mode */
|
||||
#define SC_AIP 0x40 /* R - Arbitration in progress */
|
||||
#define SC_LA 0x20 /* R - Lost arbitration */
|
||||
#define SC_A_ACK 0x10 /* RW - Assert ACK */
|
||||
#define SC_A_BSY 0x08 /* RW - Assert BSY */
|
||||
#define SC_A_SEL 0x04 /* RW - Assert SEL */
|
||||
#define SC_A_ATN 0x02 /* RW - Assert ATN */
|
||||
#define SC_ADTB 0x01 /* RW - Assert Data To Bus */
|
||||
#define GET_5380_REG(rnum) NCR5380->regs[rnum]
|
||||
#define SET_5380_REG(rnum,val) (NCR5380->regs[rnum] = val)
|
||||
#define scsi_ienable() intr_enable(IR_SCSI1)
|
||||
#define scsi_idisable() intr_disable(IR_SCSI1)
|
||||
#define scsi_clr_ipend() do { \
|
||||
int i = GET_5380_REG(NCR5380_IRCV); \
|
||||
} while (0)
|
||||
|
||||
/*
|
||||
* Definitions for mode register
|
||||
*/
|
||||
#define SC_B_DMA 0x80 /* RW - Block mode DMA (not on TT!) */
|
||||
#define SC_T_MODE 0x40 /* RW - Target mode */
|
||||
#define SC_E_PAR 0x20 /* RW - Enable parity check */
|
||||
#define SC_E_PARI 0x10 /* RW - Enable parity interrupt */
|
||||
#define SC_E_EOPI 0x08 /* RW - Enable End Of Process Interrupt */
|
||||
#define SC_MON_BSY 0x04 /* RW - Monitor BSY */
|
||||
#define SC_M_DMA 0x02 /* RW - Set DMA mode */
|
||||
#define SC_ARBIT 0x01 /* RW - Arbitrate */
|
||||
|
||||
/*
|
||||
* Definitions for tcom register
|
||||
*/
|
||||
#define SC_LBS 0x80 /* RW - Last Byte Send (not on TT!) */
|
||||
#define SC_A_REQ 0x08 /* RW - Assert REQ */
|
||||
#define SC_A_MSG 0x04 /* RW - Assert MSG */
|
||||
#define SC_A_CD 0x02 /* RW - Assert C/D */
|
||||
#define SC_A_IO 0x01 /* RW - Assert I/O */
|
||||
|
||||
/*
|
||||
* Definitions for idstat register
|
||||
*/
|
||||
#define SC_S_RST 0x80 /* R - RST is set */
|
||||
#define SC_S_BSY 0x40 /* R - BSY is set */
|
||||
#define SC_S_REQ 0x20 /* R - REQ is set */
|
||||
#define SC_S_MSG 0x10 /* R - MSG is set */
|
||||
#define SC_S_CD 0x08 /* R - C/D is set */
|
||||
#define SC_S_IO 0x04 /* R - I/O is set */
|
||||
#define SC_S_SEL 0x02 /* R - SEL is set */
|
||||
#define SC_S_PAR 0x01 /* R - Parity bit */
|
||||
|
||||
/*
|
||||
* Definitions for dmastat register
|
||||
*/
|
||||
#define SC_END_DMA 0x80 /* R - End of DMA */
|
||||
#define SC_DMA_REQ 0x40 /* R - DMA request */
|
||||
#define SC_PAR_ERR 0x20 /* R - Parity error */
|
||||
#define SC_IRQ_SET 0x10 /* R - IRQ is active */
|
||||
#define SC_PHS_MTCH 0x08 /* R - Phase Match */
|
||||
#define SC_BSY_ERR 0x04 /* R - Busy error */
|
||||
#define SC_ATN_STAT 0x02 /* R - State of ATN line */
|
||||
#define SC_ACK_STAT 0x01 /* R - State of ACK line */
|
||||
#define SC_S_SEND 0x00 /* W - Start DMA output */
|
||||
|
||||
#define SC_CLINT { /* Clear interrupts */ \
|
||||
int i = SCSI_5380->scsi_ircv; \
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Definition of SCSI-bus phases. The values are determined by signals
|
||||
* on the SCSI-bus. DO NOT CHANGE!
|
||||
* The values must be used to index the pointers in SCSI-PARMS.
|
||||
*/
|
||||
#define NR_PHASE 8
|
||||
#define PH_DATAOUT 0
|
||||
#define PH_DATAIN 1
|
||||
#define PH_CMD 2
|
||||
#define PH_STATUS 3
|
||||
#define PH_RES1 4
|
||||
#define PH_RES2 5
|
||||
#define PH_MSGOUT 6
|
||||
#define PH_MSGIN 7
|
||||
|
||||
#define PH_OUT(phase) (!(phase & 1)) /* TRUE if output phase */
|
||||
#define PH_IN(phase) (phase & 1) /* TRUE if input phase */
|
||||
|
||||
/*
|
||||
* Id of Host-adapter
|
||||
*/
|
||||
#define SC_HOST_ID 0x80
|
||||
|
||||
/*
|
||||
* Base setting for 5380 mode register
|
||||
*/
|
||||
#define IMODE_BASE SC_E_PAR
|
||||
|
||||
#endif /* _NCR5380REG_H */
|
||||
#endif /* _NCRREG_H */
|
||||
|
||||
953
sys/arch/pc532/dev/oldncr.c
Normal file
953
sys/arch/pc532/dev/oldncr.c
Normal file
@ -0,0 +1,953 @@
|
||||
/* $NetBSD: oldncr.c,v 1.1 1995/08/25 07:30:41 phil Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (C) 1993 Allen K. Briggs, Chris P. Caputo,
|
||||
* Michael L. Finch, Bradley A. Grantham, and
|
||||
* Lawrence A. Kesteloot
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed by the Alice Group.
|
||||
* 4. The names of the Alice Group or any of its members may not be used
|
||||
* to endorse or promote products derived from this software without
|
||||
* specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE ALICE GROUP ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL THE ALICE GROUP BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/* Modified for use with the pc532 by Phil Nelson, June 94. */
|
||||
|
||||
#define PSEUDO_DMA 1
|
||||
|
||||
static int ncr_debug=1;
|
||||
|
||||
#include <sys/types.h>
|
||||
#include <sys/malloc.h>
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
#include <sys/errno.h>
|
||||
#include <sys/buf.h>
|
||||
#include <sys/kernel.h>
|
||||
#include <sys/proc.h>
|
||||
#include <sys/user.h>
|
||||
#include <sys/device.h>
|
||||
#include <scsi/scsi_all.h>
|
||||
#include <scsi/scsi_debug.h>
|
||||
#include <scsi/scsiconf.h>
|
||||
|
||||
#include <machine/icu.h>
|
||||
|
||||
#include "ncr_defs.h"
|
||||
#include "ncr_5380.h"
|
||||
|
||||
#define NCR5380 DP8490
|
||||
|
||||
#define SCI_PHASE_DISC 0 /* sort of ... */
|
||||
#define SCI_CLR_INTR(regs) {register int temp = regs->sci_iack;}
|
||||
#define SCI_ACK(ptr,phase) (ptr)->sci_tcmd = (phase)
|
||||
#define SCSI_TIMEOUT_VAL 10000000
|
||||
#define WAIT_FOR_NOT_REQ(ptr) { \
|
||||
int scsi_timeout = SCSI_TIMEOUT_VAL; \
|
||||
while ( ((ptr)->sci_bus_csr & SCI_BUS_REQ) && \
|
||||
((ptr)->sci_bus_csr & SCI_BUS_REQ) && \
|
||||
((ptr)->sci_bus_csr & SCI_BUS_REQ) && \
|
||||
(--scsi_timeout) ); \
|
||||
if (!scsi_timeout) { \
|
||||
printf("scsi timeout--WAIT_FOR_NOT_REQ---ncr.c, \
|
||||
line %d.\n", __LINE__); \
|
||||
goto scsi_timeout_error; \
|
||||
} \
|
||||
}
|
||||
|
||||
#define WAIT_FOR_REQ(ptr) { \
|
||||
int scsi_timeout = SCSI_TIMEOUT_VAL; \
|
||||
while ( (((ptr)->sci_bus_csr & SCI_BUS_REQ) == 0) && \
|
||||
(((ptr)->sci_bus_csr & SCI_BUS_REQ) == 0) && \
|
||||
(((ptr)->sci_bus_csr & SCI_BUS_REQ) == 0) && \
|
||||
(--scsi_timeout) ); \
|
||||
if (!scsi_timeout) { \
|
||||
printf("scsi timeout--WAIT_FOR_REQ---ncr.c, \
|
||||
line %d.\n", __LINE__); \
|
||||
goto scsi_timeout_error; \
|
||||
} \
|
||||
}
|
||||
#define WAIT_FOR_BSY(ptr) { \
|
||||
int scsi_timeout = SCSI_TIMEOUT_VAL; \
|
||||
while ((((ptr)->sci_bus_csr & SCI_BUS_BSY) == 0) && \
|
||||
(((ptr)->sci_bus_csr & SCI_BUS_BSY) == 0) && \
|
||||
(((ptr)->sci_bus_csr & SCI_BUS_BSY) == 0) && \
|
||||
(--scsi_timeout) ); \
|
||||
if (!scsi_timeout) { \
|
||||
printf("scsi timeout--WAIT_FOR_BSY---ncr.c, \
|
||||
line %d.\n", __LINE__); \
|
||||
goto scsi_timeout_error; \
|
||||
} \
|
||||
}
|
||||
|
||||
#ifdef DDB
|
||||
int Debugger();
|
||||
#else
|
||||
#define Debugger() panic("Should call Debugger here (mac/dev/ncr.c).")
|
||||
#endif
|
||||
|
||||
typedef unsigned long int physaddr;
|
||||
typedef sci_regmap_t sci_padded_regmap_t;
|
||||
|
||||
#define NNCR5380 1
|
||||
|
||||
struct ncr5380_softc {
|
||||
struct device sc_dev;
|
||||
struct scsi_link sc_link;
|
||||
};
|
||||
|
||||
/* From the mapping of the pc532 address space. See pc532/machdep.c */
|
||||
static volatile sci_padded_regmap_t *ncr = (sci_regmap_t *) 0xffd00000;
|
||||
static volatile long *sci_4byte_addr= (long *) 0xffe00000;
|
||||
static volatile u_char *sci_1byte_addr=(u_char *) 0xffe00000;
|
||||
|
||||
static u_int ncr5380_minphys(struct buf *bp);
|
||||
static int ncr5380_scsi_cmd(struct scsi_xfer *xs);
|
||||
|
||||
static int ncr5380_show_scsi_cmd(struct scsi_xfer *xs);
|
||||
static int ncr5380_reset_target(int adapter, int target);
|
||||
static int ncr5380_poll(int adapter, int timeout);
|
||||
static int ncr5380_send_cmd(struct scsi_xfer *xs);
|
||||
|
||||
extern void ncr5380_intr(int adapter);
|
||||
extern void spinwait(int);
|
||||
|
||||
static int scsi_gen(int adapter, int id, int lun,
|
||||
struct scsi_generic *cmd, int cmdlen,
|
||||
void *databuf, int datalen);
|
||||
static int scsi_group0(int adapter, int id, int lun,
|
||||
int opcode, int addr, int len,
|
||||
int flags, caddr_t databuf, int datalen);
|
||||
|
||||
static char scsi_name[] = "ncr";
|
||||
|
||||
struct scsi_adapter ncr5380_switch = {
|
||||
ncr5380_scsi_cmd, /* scsi_cmd() */
|
||||
ncr5380_minphys, /* scsi_minphys() */
|
||||
0, /* open_target_lu() */
|
||||
0 /* close_target_lu() */
|
||||
};
|
||||
|
||||
/* This is copied from julian's bt driver */
|
||||
/* "so we have a default dev struct for our link struct." */
|
||||
struct scsi_device ncr_dev = {
|
||||
NULL, /* Use default error handler. */
|
||||
NULL, /* have a queue, served by this (?) */
|
||||
NULL, /* have no async handler. */
|
||||
NULL /* Use default "done" routine. */
|
||||
};
|
||||
|
||||
extern int matchbyname();
|
||||
static int ncrprobe();
|
||||
static void ncrattach();
|
||||
|
||||
struct cfdriver ncrcd =
|
||||
{ NULL, "ncr", ncrprobe, ncrattach,
|
||||
DV_DULL, sizeof(struct ncr5380_softc), NULL, 0 };
|
||||
|
||||
static int
|
||||
ncrprobe(parent, self, aux)
|
||||
struct device *parent, *self;
|
||||
void *aux;
|
||||
{
|
||||
/* int unit = cf->cf_unit; */
|
||||
struct ncr5380_softc *ncr5380 = (void *)self;
|
||||
|
||||
#if 0
|
||||
DELETE THIS ????
|
||||
if (unit >= NNCR5380) {
|
||||
printf("ncr5380attach: unit %d more than %d configured.\n",
|
||||
unit+1, NNCR5380);
|
||||
return 0;
|
||||
}
|
||||
ncr5380 = malloc(sizeof(struct ncr5380_data), M_TEMP, M_NOWAIT);
|
||||
if (!ncr5380) {
|
||||
printf("ncr5380attach: Can't malloc.\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
bzero(ncr5380, sizeof(*ncr5380));
|
||||
ncr5380data[unit] = ncr5380;
|
||||
#endif
|
||||
|
||||
/* If we call this, we need to add SPL_DP to the bio mask! */
|
||||
/* PL_bio |= SPL_DP; Not yet ... no interrupts */
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
static void
|
||||
ncrattach(parent, self, aux)
|
||||
struct device *parent, *self;
|
||||
void *aux;
|
||||
{
|
||||
register volatile sci_padded_regmap_t *regs = ncr;
|
||||
struct ncr5380_softc *ncr5380 = (void *)self;
|
||||
int r;
|
||||
|
||||
ncr5380->sc_link.adapter_softc = ncr5380;
|
||||
/* ncr5380->sc_link.scsibus = 0; */
|
||||
ncr5380->sc_link.adapter_target = 7;
|
||||
ncr5380->sc_link.adapter = &ncr5380_switch;
|
||||
ncr5380->sc_link.device = &ncr_dev;
|
||||
ncr5380->sc_link.openings = 1;
|
||||
|
||||
printf("\n");
|
||||
|
||||
config_found(self, &(ncr5380->sc_link), NULL);
|
||||
}
|
||||
|
||||
#define MIN_PHYS 65536 /*BARF!!!!*/
|
||||
static u_int
|
||||
ncr5380_minphys(struct buf *bp)
|
||||
{
|
||||
if (bp->b_bcount > MIN_PHYS) {
|
||||
printf("Uh-oh... ncr5380_minphys setting bp->b_bcount = %x.\n", MIN_PHYS);
|
||||
bp->b_bcount = MIN_PHYS;
|
||||
}
|
||||
return (minphys(bp));
|
||||
}
|
||||
#undef MIN_PHYS
|
||||
|
||||
static int
|
||||
ncr5380_scsi_cmd(struct scsi_xfer *xs)
|
||||
{
|
||||
int flags, s, r;
|
||||
|
||||
flags = xs->flags;
|
||||
if (xs->bp) flags |= (SCSI_NOSLEEP);
|
||||
if ( flags & ITSDONE ) {
|
||||
printf("Already done?");
|
||||
xs->flags &= ~ITSDONE;
|
||||
}
|
||||
if ( ! ( flags & INUSE ) ) {
|
||||
printf("Not in use?");
|
||||
xs->flags |= INUSE;
|
||||
}
|
||||
|
||||
if ( flags & SCSI_RESET ) {
|
||||
printf("flags & SCSIRESET.\n");
|
||||
s = splbio();
|
||||
ncr5380_reset_target(xs->sc_link->scsibus,
|
||||
xs->sc_link->target);
|
||||
splx(s);
|
||||
return(COMPLETE);
|
||||
}
|
||||
|
||||
xs->resid = 0; /* Default value? */
|
||||
r = ncr5380_send_cmd(xs);
|
||||
xs->flags |= ITSDONE;
|
||||
scsi_done(xs);
|
||||
switch(r) {
|
||||
case COMPLETE: case SUCCESSFULLY_QUEUED:
|
||||
r = SUCCESSFULLY_QUEUED;
|
||||
if (xs->flags&SCSI_POLL)
|
||||
r = COMPLETE;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
return r;
|
||||
}
|
||||
|
||||
static int
|
||||
ncr5380_show_scsi_cmd(struct scsi_xfer *xs)
|
||||
{
|
||||
u_char *b = (u_char *) xs->cmd;
|
||||
int i = 0;
|
||||
|
||||
if ( ! ( xs->flags & SCSI_RESET ) ) {
|
||||
printf("ncr5380(%d:%d:%d)-",
|
||||
xs->sc_link->scsibus, xs->sc_link->target, xs->sc_link->lun);
|
||||
while (i < xs->cmdlen) {
|
||||
if (i) printf(",");
|
||||
printf("%x",b[i++]);
|
||||
}
|
||||
printf("-\n");
|
||||
} else {
|
||||
printf("ncr5380(%d:%d:%d)-RESET-\n",
|
||||
xs->sc_link->scsibus, xs->sc_link->target, xs->sc_link->lun);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Actual chip control.
|
||||
*/
|
||||
|
||||
void
|
||||
delay(int timeo)
|
||||
{
|
||||
int len;
|
||||
for (len=0;len<timeo*2;len++);
|
||||
}
|
||||
|
||||
#if 0
|
||||
extern void
|
||||
spinwait(int ms)
|
||||
{
|
||||
while (ms--)
|
||||
delay(500);
|
||||
}
|
||||
#endif
|
||||
|
||||
extern void
|
||||
ncr5380_intr(int adapter)
|
||||
{
|
||||
register volatile sci_padded_regmap_t *regs = ncr;
|
||||
|
||||
SCI_CLR_INTR(regs);
|
||||
regs->sci_mode = 0x00;
|
||||
}
|
||||
|
||||
extern int
|
||||
scsi_irq_intr(void)
|
||||
{
|
||||
register volatile sci_padded_regmap_t *regs = ncr;
|
||||
|
||||
/* if (regs->sci_csr != SCI_CSR_PHASE_MATCH)
|
||||
printf("scsi_irq_intr called (not just phase match -- "
|
||||
"csr = 0x%x, bus_csr = 0x%x).\n",
|
||||
regs->sci_csr, regs->sci_bus_csr);
|
||||
ncr5380_intr(0); */
|
||||
return 1;
|
||||
}
|
||||
|
||||
extern int
|
||||
scsi_drq_intr(void)
|
||||
{
|
||||
/* printf("scsi_drq_intr called.\n"); */
|
||||
/* ncr5380_intr(0); */
|
||||
return 1;
|
||||
}
|
||||
|
||||
static int
|
||||
ncr5380_reset_target(int adapter, int target)
|
||||
{
|
||||
register volatile sci_padded_regmap_t *regs = ncr;
|
||||
int dummy;
|
||||
|
||||
scsi_select_ctlr (DP8490);
|
||||
regs->sci_icmd = SCI_ICMD_TEST;
|
||||
regs->sci_icmd = SCI_ICMD_TEST | SCI_ICMD_RST;
|
||||
delay(2500);
|
||||
regs->sci_icmd = 0;
|
||||
|
||||
regs->sci_mode = 0;
|
||||
regs->sci_tcmd = SCI_PHASE_DISC;
|
||||
regs->sci_sel_enb = 0;
|
||||
|
||||
SCI_CLR_INTR(regs);
|
||||
SCI_CLR_INTR(regs);
|
||||
}
|
||||
|
||||
|
||||
static int
|
||||
ncr5380_send_cmd(struct scsi_xfer *xs)
|
||||
{
|
||||
int s, i, sense;
|
||||
|
||||
#if 0
|
||||
ncr5380_show_scsi_cmd(xs);
|
||||
#endif
|
||||
s = splbio();
|
||||
sense = scsi_gen( xs->sc_link->scsibus, xs->sc_link->target,
|
||||
xs->sc_link->lun, xs->cmd, xs->cmdlen,
|
||||
xs->data, xs->datalen );
|
||||
splx(s);
|
||||
switch (sense) {
|
||||
case 0x00:
|
||||
xs->error = XS_NOERROR;
|
||||
return (COMPLETE);
|
||||
case 0x02: /* Check condition */
|
||||
for (i = 10; i; i--) {
|
||||
s = splbio();
|
||||
sense = scsi_group0(xs->sc_link->scsibus,
|
||||
xs->sc_link->target,
|
||||
xs->sc_link->lun,
|
||||
0x3, 0x0,
|
||||
sizeof(struct scsi_sense_data),
|
||||
0, (caddr_t) &(xs->sense),
|
||||
sizeof(struct scsi_sense_data));
|
||||
splx(s);
|
||||
if (sense == 0) break;
|
||||
if (sense == 8
|
||||
&& (xs->flags & SCSI_NOSLEEP) == 0)
|
||||
tsleep((caddr_t)&lbolt, PRIBIO, "ncrbusy", 0);
|
||||
}
|
||||
if (!i)
|
||||
printf("ncr(%d:%d): Sense failed (dev busy)\n",
|
||||
xs->sc_link->target, xs->sc_link->lun);
|
||||
xs->error = XS_SENSE;
|
||||
return COMPLETE;
|
||||
case 0x08: /* Busy */
|
||||
xs->error = XS_BUSY;
|
||||
return COMPLETE;
|
||||
default:
|
||||
xs->error = XS_DRIVER_STUFFUP;
|
||||
return COMPLETE;
|
||||
}
|
||||
}
|
||||
|
||||
static int
|
||||
select_target(register volatile sci_padded_regmap_t *regs,
|
||||
u_char myid, u_char tid, int with_atn)
|
||||
{
|
||||
register u_char bid, icmd;
|
||||
int ret = SCSI_RET_RETRY;
|
||||
|
||||
if ((regs->sci_bus_csr & (SCI_BUS_BSY|SCI_BUS_SEL)) &&
|
||||
(regs->sci_bus_csr & (SCI_BUS_BSY|SCI_BUS_SEL)) &&
|
||||
(regs->sci_bus_csr & (SCI_BUS_BSY|SCI_BUS_SEL)))
|
||||
return ret;
|
||||
|
||||
/* for our purposes.. */
|
||||
myid = 1 << myid;
|
||||
tid = 1 << tid;
|
||||
|
||||
regs->sci_sel_enb = 0; /*myid; we don't want any interrupts. */
|
||||
regs->sci_tcmd = 0; /* get into a harmless state */
|
||||
regs->sci_mode = 0; /* get into a harmless state */
|
||||
|
||||
regs->sci_odata = myid;
|
||||
regs->sci_mode = SCI_MODE_ARB;
|
||||
/* regs->sci_mode |= SCI_MODE_ARB; */
|
||||
/* AIP might not set if BSY went true after we checked */
|
||||
for (bid = 0; bid < 20; bid++) /* 20usec circa */
|
||||
if (regs->sci_icmd & SCI_ICMD_AIP)
|
||||
break;
|
||||
if ((regs->sci_icmd & SCI_ICMD_AIP) == 0) {
|
||||
goto lost;
|
||||
}
|
||||
|
||||
spinwait(2); /* 2.2us arb delay */
|
||||
|
||||
if (regs->sci_icmd & SCI_ICMD_LST) {
|
||||
goto lost;
|
||||
}
|
||||
|
||||
regs->sci_mode &= ~SCI_MODE_PAR_CHK;
|
||||
bid = regs->sci_data;
|
||||
|
||||
if ((bid & ~myid) > myid) {
|
||||
goto lost;
|
||||
}
|
||||
if (regs->sci_icmd & SCI_ICMD_LST) {
|
||||
goto lost;
|
||||
}
|
||||
|
||||
/* Won arbitration, enter selection phase now */
|
||||
icmd = regs->sci_icmd & ~(SCI_ICMD_DIFF|SCI_ICMD_TEST);
|
||||
icmd |= (with_atn ? (SCI_ICMD_SEL|SCI_ICMD_ATN) : SCI_ICMD_SEL);
|
||||
icmd |= SCI_ICMD_BSY;
|
||||
regs->sci_icmd = icmd;
|
||||
|
||||
if (regs->sci_icmd & SCI_ICMD_LST) {
|
||||
goto nosel;
|
||||
}
|
||||
|
||||
/* XXX a target that violates specs might still drive the bus XXX */
|
||||
/* XXX should put our id out, and after the delay check nothi XXX */
|
||||
/* XXX ng else is out there. XXX */
|
||||
|
||||
delay(0);
|
||||
|
||||
regs->sci_tcmd = 0;
|
||||
regs->sci_odata = myid | tid;
|
||||
regs->sci_sel_enb = 0;
|
||||
|
||||
/* regs->sci_mode &= ~SCI_MODE_ARB; 2 deskew delays, too */
|
||||
regs->sci_mode = 0; /* 2 deskew delays, too */
|
||||
|
||||
icmd |= SCI_ICMD_DATA;
|
||||
icmd &= ~(SCI_ICMD_BSY);
|
||||
|
||||
regs->sci_icmd = icmd;
|
||||
|
||||
/* bus settle delay, 400ns */
|
||||
delay(2); /* too much (was 2) ? */
|
||||
|
||||
/* regs->sci_mode |= SCI_MODE_PAR_CHK; */
|
||||
|
||||
{
|
||||
register int timeo = 2500;/* 250 msecs in 100 usecs chunks */
|
||||
while ((regs->sci_bus_csr & SCI_BUS_BSY) == 0) {
|
||||
if (--timeo > 0) {
|
||||
delay(100);
|
||||
} else {
|
||||
goto nodev;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
icmd &= ~(SCI_ICMD_DATA|SCI_ICMD_SEL);
|
||||
regs->sci_icmd = icmd;
|
||||
/* regs->sci_sel_enb = myid;*/ /* looks like we should NOT have it */
|
||||
return SCSI_RET_SUCCESS;
|
||||
nodev:
|
||||
ret = SCSI_RET_DEVICE_DOWN;
|
||||
regs->sci_sel_enb = myid;
|
||||
nosel:
|
||||
icmd &= ~(SCI_ICMD_DATA|SCI_ICMD_SEL|SCI_ICMD_ATN);
|
||||
regs->sci_icmd = icmd;
|
||||
lost:
|
||||
regs->sci_mode = 0;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
sci_data_out(regs, phase, count, data)
|
||||
register sci_padded_regmap_t *regs;
|
||||
unsigned char *data;
|
||||
{
|
||||
register unsigned char icmd;
|
||||
register int cnt=0;
|
||||
|
||||
/* ..checks.. */
|
||||
|
||||
icmd = regs->sci_icmd & ~(SCI_ICMD_DIFF|SCI_ICMD_TEST);
|
||||
loop:
|
||||
if (SCI_CUR_PHASE(regs->sci_bus_csr) != phase)
|
||||
return cnt;
|
||||
|
||||
WAIT_FOR_REQ(regs);
|
||||
icmd |= SCI_ICMD_DATA;
|
||||
regs->sci_icmd = icmd;
|
||||
regs->sci_odata = *data++;
|
||||
icmd |= SCI_ICMD_ACK;
|
||||
regs->sci_icmd = icmd;
|
||||
|
||||
icmd &= ~(SCI_ICMD_DATA|SCI_ICMD_ACK);
|
||||
WAIT_FOR_NOT_REQ(regs);
|
||||
regs->sci_icmd = icmd;
|
||||
++cnt;
|
||||
if (--count > 0)
|
||||
goto loop;
|
||||
scsi_timeout_error:
|
||||
return cnt;
|
||||
}
|
||||
|
||||
sci_data_in(regs, phase, count, data)
|
||||
register sci_padded_regmap_t *regs;
|
||||
unsigned char *data;
|
||||
{
|
||||
register unsigned char icmd;
|
||||
register int cnt=0;
|
||||
|
||||
/* ..checks.. */
|
||||
|
||||
icmd = regs->sci_icmd & ~(SCI_ICMD_DIFF|SCI_ICMD_TEST);
|
||||
|
||||
loop:
|
||||
if (SCI_CUR_PHASE(regs->sci_bus_csr) != phase)
|
||||
return cnt;
|
||||
|
||||
WAIT_FOR_REQ(regs);
|
||||
*data++ = regs->sci_data;
|
||||
icmd |= SCI_ICMD_ACK;
|
||||
regs->sci_icmd = icmd;
|
||||
|
||||
icmd &= ~SCI_ICMD_ACK;
|
||||
WAIT_FOR_NOT_REQ(regs);
|
||||
regs->sci_icmd = icmd;
|
||||
++cnt;
|
||||
if (--count > 0)
|
||||
goto loop;
|
||||
|
||||
scsi_timeout_error:
|
||||
return cnt;
|
||||
}
|
||||
|
||||
static int
|
||||
command_transfer(register volatile sci_padded_regmap_t *regs,
|
||||
int maxlen, u_char *data, u_char *status, u_char *msg)
|
||||
{
|
||||
int xfer=0, phase;
|
||||
|
||||
/* printf("command_transfer called for 0x%x.\n", *data); */
|
||||
|
||||
regs->sci_icmd = 0;
|
||||
|
||||
while (1) {
|
||||
|
||||
WAIT_FOR_REQ(regs);
|
||||
|
||||
phase = SCI_CUR_PHASE(regs->sci_bus_csr);
|
||||
|
||||
switch (phase) {
|
||||
case SCSI_PHASE_CMD:
|
||||
SCI_ACK(regs,SCSI_PHASE_CMD);
|
||||
xfer += sci_data_out(regs, SCSI_PHASE_CMD,
|
||||
maxlen, data);
|
||||
return xfer;
|
||||
case SCSI_PHASE_DATA_IN:
|
||||
printf("Data in phase in command_transfer?\n");
|
||||
return 0;
|
||||
case SCSI_PHASE_DATA_OUT:
|
||||
printf("Data out phase in command_transfer?\n");
|
||||
return 0;
|
||||
case SCSI_PHASE_STATUS:
|
||||
SCI_ACK(regs,SCSI_PHASE_STATUS);
|
||||
printf("status in command_transfer.\n");
|
||||
sci_data_in(regs, SCSI_PHASE_STATUS,
|
||||
1, status);
|
||||
break;
|
||||
case SCSI_PHASE_MESSAGE_IN:
|
||||
SCI_ACK(regs,SCSI_PHASE_MESSAGE_IN);
|
||||
printf("msgin in command_transfer.\n");
|
||||
sci_data_in(regs, SCSI_PHASE_MESSAGE_IN,
|
||||
1, msg);
|
||||
break;
|
||||
case SCSI_PHASE_MESSAGE_OUT:
|
||||
SCI_ACK(regs,SCSI_PHASE_MESSAGE_OUT);
|
||||
sci_data_out(regs, SCSI_PHASE_MESSAGE_OUT,
|
||||
1, msg);
|
||||
break;
|
||||
default:
|
||||
printf("Unexpected phase 0x%x in "
|
||||
"command_transfer().\n", phase);
|
||||
scsi_timeout_error:
|
||||
return xfer;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static int
|
||||
data_transfer(register volatile sci_padded_regmap_t *regs,
|
||||
int maxlen, u_char *data, u_char *status, u_char *msg)
|
||||
{
|
||||
int retlen = 0, xfer, phase;
|
||||
|
||||
regs->sci_icmd = 0;
|
||||
|
||||
*status = 0;
|
||||
|
||||
while (1) {
|
||||
|
||||
WAIT_FOR_REQ(regs);
|
||||
|
||||
phase = SCI_CUR_PHASE(regs->sci_bus_csr);
|
||||
|
||||
switch (phase) {
|
||||
case SCSI_PHASE_CMD:
|
||||
printf("Command phase in data_transfer().\n");
|
||||
return retlen;
|
||||
case SCSI_PHASE_DATA_IN:
|
||||
SCI_ACK(regs,SCSI_PHASE_DATA_IN);
|
||||
#if PSEUDO_DMA
|
||||
xfer = sci_pdma_in(regs, SCSI_PHASE_DATA_IN,
|
||||
maxlen, data);
|
||||
#else
|
||||
xfer = sci_data_in(regs, SCSI_PHASE_DATA_IN,
|
||||
maxlen, data);
|
||||
#endif
|
||||
retlen += xfer;
|
||||
maxlen -= xfer;
|
||||
break;
|
||||
case SCSI_PHASE_DATA_OUT:
|
||||
SCI_ACK(regs,SCSI_PHASE_DATA_OUT);
|
||||
#if PSEUDO_DMA
|
||||
xfer = sci_pdma_out(regs, SCSI_PHASE_DATA_OUT,
|
||||
maxlen, data);
|
||||
#else
|
||||
xfer = sci_data_out(regs, SCSI_PHASE_DATA_OUT,
|
||||
maxlen, data);
|
||||
#endif
|
||||
retlen += xfer;
|
||||
maxlen -= xfer;
|
||||
break;
|
||||
case SCSI_PHASE_STATUS:
|
||||
SCI_ACK(regs,SCSI_PHASE_STATUS);
|
||||
sci_data_in(regs, SCSI_PHASE_STATUS,
|
||||
1, status);
|
||||
break;
|
||||
case SCSI_PHASE_MESSAGE_IN:
|
||||
SCI_ACK(regs,SCSI_PHASE_MESSAGE_IN);
|
||||
sci_data_in(regs, SCSI_PHASE_MESSAGE_IN,
|
||||
1, msg);
|
||||
if (*msg == 0) {
|
||||
return retlen;
|
||||
} else {
|
||||
printf( "message 0x%x in "
|
||||
"data_transfer.\n", *msg);
|
||||
}
|
||||
break;
|
||||
case SCSI_PHASE_MESSAGE_OUT:
|
||||
SCI_ACK(regs,SCSI_PHASE_MESSAGE_OUT);
|
||||
sci_data_out(regs, SCSI_PHASE_MESSAGE_OUT,
|
||||
1, msg);
|
||||
break;
|
||||
default:
|
||||
printf( "Unexpected phase 0x%x in "
|
||||
"data_transfer().\n", phase);
|
||||
scsi_timeout_error:
|
||||
return retlen;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static int
|
||||
scsi_request(register volatile sci_padded_regmap_t *regs,
|
||||
int target, int lun, u_char *cmd, int cmdlen,
|
||||
char *databuf, int datalen, int *sent, int *ret)
|
||||
{
|
||||
/* Returns 0 on success, -1 on internal error, or the status byte */
|
||||
int cmd_bytes_sent, r;
|
||||
u_char stat, msg, c;
|
||||
|
||||
*sent = 0;
|
||||
scsi_select_ctlr (DP8490);
|
||||
|
||||
if ( ( r = select_target(regs, 7, target, 1) ) != SCSI_RET_SUCCESS) {
|
||||
*ret = r;
|
||||
SCI_CLR_INTR(regs);
|
||||
switch (r) {
|
||||
case SCSI_RET_RETRY:
|
||||
return 0x08;
|
||||
default:
|
||||
printf("select_target(target %d, lun %d) failed(%d).\n",
|
||||
target, lun, r);
|
||||
case SCSI_RET_DEVICE_DOWN:
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
c = 0x80 | lun;
|
||||
|
||||
if ((cmd_bytes_sent = command_transfer(regs, cmdlen,
|
||||
(u_char *) cmd, &stat, &c))
|
||||
!= cmdlen) {
|
||||
SCI_CLR_INTR(regs);
|
||||
*ret = SCSI_RET_COMMAND_FAIL;
|
||||
printf("Data underrun sending CCB (%d bytes of %d, sent).\n",
|
||||
cmd_bytes_sent, cmdlen);
|
||||
return -1;
|
||||
}
|
||||
|
||||
*sent=data_transfer(regs, datalen, (u_char *)databuf,
|
||||
&stat, &msg);
|
||||
|
||||
*ret = 0;
|
||||
|
||||
return stat;
|
||||
}
|
||||
|
||||
static int
|
||||
scsi_gen(int adapter, int id, int lun, struct scsi_generic *cmd,
|
||||
int cmdlen, void *databuf, int datalen)
|
||||
{
|
||||
register volatile sci_padded_regmap_t *regs = ncr;
|
||||
int i,j,sent,ret;
|
||||
|
||||
cmd->bytes[0] |= ((u_char) lun << 5);
|
||||
|
||||
i = scsi_request(regs, id, lun, (u_char *) cmd, cmdlen,
|
||||
databuf, datalen, &sent, &ret);
|
||||
|
||||
return i;
|
||||
}
|
||||
|
||||
static int
|
||||
scsi_group0(int adapter, int id, int lun, int opcode, int addr, int len,
|
||||
int flags, caddr_t databuf, int datalen)
|
||||
{
|
||||
register volatile sci_padded_regmap_t *regs = ncr;
|
||||
unsigned char cmd[6];
|
||||
int i,j,sent,ret;
|
||||
|
||||
cmd[0] = opcode; /* Operation code */
|
||||
cmd[1] = (lun << 5) | ((addr >> 16) & 0x1F); /* Lun & MSB of addr */
|
||||
cmd[2] = (addr >> 8) & 0xFF; /* addr */
|
||||
cmd[3] = addr & 0xFF; /* LSB of addr */
|
||||
cmd[4] = len; /* Allocation length */
|
||||
cmd[5] = flags; /* Link/Flag */
|
||||
|
||||
i = scsi_request(regs, id, lun, cmd, 6, databuf, datalen, &sent, &ret);
|
||||
|
||||
return i;
|
||||
}
|
||||
|
||||
/* pseudo-dma action */
|
||||
|
||||
#if PSEUDO_DMA
|
||||
|
||||
#define TIMEOUT 1000000
|
||||
#define READY(poll) \
|
||||
i = TIMEOUT; \
|
||||
while ((regs->sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) \
|
||||
!=(SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) \
|
||||
if ( !(regs->sci_csr & SCI_CSR_PHASE_MATCH) \
|
||||
|| !(regs->sci_bus_csr & SCI_BUS_BSY) \
|
||||
|| (i-- < 0) ) { \
|
||||
printf("ncr.c: timeout counter = %d, len = %d count=%d (count-len %d).\n", \
|
||||
i, len,count,count-len); \
|
||||
printf("ncr_debug = %d, 1=out, 2=in",ncr_debug); \
|
||||
/*dump_regs();*/ \
|
||||
if (poll && !(regs->sci_csr & SCI_CSR_PHASE_MATCH)) { \
|
||||
regs->sci_icmd &= ~SCI_ICMD_DATA; \
|
||||
len--; \
|
||||
} else { \
|
||||
regs->sci_mode &= ~SCI_MODE_DMA; \
|
||||
} \
|
||||
return count-len; \
|
||||
}
|
||||
|
||||
#define W1 *byte_data = *data++
|
||||
#define W4 *long_data = *((long*)data)++
|
||||
|
||||
sci_pdma_out(regs, phase, count, data)
|
||||
register volatile sci_padded_regmap_t *regs;
|
||||
int phase;
|
||||
int count;
|
||||
u_char *data;
|
||||
{
|
||||
register volatile long *long_data = sci_4byte_addr;
|
||||
register volatile u_char *byte_data = sci_1byte_addr;
|
||||
register int len = count, i;
|
||||
|
||||
ncr_debug=1;
|
||||
|
||||
if (count < 128)
|
||||
return sci_data_out(regs, phase, count, data);
|
||||
|
||||
WAIT_FOR_BSY(regs);
|
||||
regs->sci_mode |= SCI_MODE_DMA;
|
||||
regs->sci_icmd |= SCI_ICMD_DATA;
|
||||
regs->sci_dma_send = 0;
|
||||
|
||||
while ( len >= 64 ) {
|
||||
READY(1); W1; READY(1); W1; READY(1); W1; READY(1); W1;
|
||||
READY(1);
|
||||
W4;W4;W4; W4;W4;W4;W4; W4;W4;W4;W4; W4;W4;W4;W4;
|
||||
len -= 64;
|
||||
}
|
||||
while (len) {
|
||||
READY(1);
|
||||
W1;
|
||||
len--;
|
||||
}
|
||||
i = TIMEOUT;
|
||||
while ( ((regs->sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH))
|
||||
== SCI_CSR_PHASE_MATCH) && --i);
|
||||
if (!i)
|
||||
printf("ncr.c:%d: timeout waiting for SCI_CSR_DREQ.\n", __LINE__);
|
||||
*byte_data = 0;
|
||||
scsi_timeout_error:
|
||||
regs->sci_mode &= ~SCI_MODE_DMA;
|
||||
return count-len;
|
||||
}
|
||||
|
||||
#undef W1
|
||||
#undef W4
|
||||
|
||||
#define R4 *((long *)data)++ = *long_data
|
||||
#define R1 *data++ = *byte_data
|
||||
|
||||
sci_pdma_in(regs, phase, count, data)
|
||||
register volatile sci_padded_regmap_t *regs;
|
||||
int phase;
|
||||
int count;
|
||||
u_char *data;
|
||||
{
|
||||
register volatile long *long_data = sci_4byte_addr;
|
||||
register volatile u_char *byte_data = sci_1byte_addr;
|
||||
register int len = count, i;
|
||||
|
||||
ncr_debug=2;
|
||||
if (count < 128)
|
||||
return sci_data_in(regs, phase, count, data);
|
||||
|
||||
/* printf("Called sci_pdma_in(0x%x, 0x%x, %d, 0x%x.\n", regs, phase, count, data); */
|
||||
|
||||
WAIT_FOR_BSY(regs);
|
||||
regs->sci_mode |= SCI_MODE_DMA;
|
||||
regs->sci_icmd |= SCI_ICMD_DATA;
|
||||
regs->sci_irecv = 0;
|
||||
|
||||
while (len >= 1024) {
|
||||
READY(0);
|
||||
R4;R4;R4;R4; R4;R4;R4;R4; R4;R4;R4;R4; R4;R4;R4;R4;
|
||||
R4;R4;R4;R4; R4;R4;R4;R4; R4;R4;R4;R4; R4;R4;R4;R4; /* 128 */
|
||||
READY(0);
|
||||
R4;R4;R4;R4; R4;R4;R4;R4; R4;R4;R4;R4; R4;R4;R4;R4;
|
||||
R4;R4;R4;R4; R4;R4;R4;R4; R4;R4;R4;R4; R4;R4;R4;R4; /* 256 */
|
||||
READY(0);
|
||||
R4;R4;R4;R4; R4;R4;R4;R4; R4;R4;R4;R4; R4;R4;R4;R4;
|
||||
R4;R4;R4;R4; R4;R4;R4;R4; R4;R4;R4;R4; R4;R4;R4;R4; /* 384 */
|
||||
READY(0);
|
||||
R4;R4;R4;R4; R4;R4;R4;R4; R4;R4;R4;R4; R4;R4;R4;R4;
|
||||
R4;R4;R4;R4; R4;R4;R4;R4; R4;R4;R4;R4; R4;R4;R4;R4; /* 512 */
|
||||
READY(0);
|
||||
R4;R4;R4;R4; R4;R4;R4;R4; R4;R4;R4;R4; R4;R4;R4;R4;
|
||||
R4;R4;R4;R4; R4;R4;R4;R4; R4;R4;R4;R4; R4;R4;R4;R4; /* 640 */
|
||||
READY(0);
|
||||
R4;R4;R4;R4; R4;R4;R4;R4; R4;R4;R4;R4; R4;R4;R4;R4;
|
||||
R4;R4;R4;R4; R4;R4;R4;R4; R4;R4;R4;R4; R4;R4;R4;R4; /* 768 */
|
||||
READY(0);
|
||||
R4;R4;R4;R4; R4;R4;R4;R4; R4;R4;R4;R4; R4;R4;R4;R4;
|
||||
R4;R4;R4;R4; R4;R4;R4;R4; R4;R4;R4;R4; R4;R4;R4;R4; /* 896 */
|
||||
READY(0);
|
||||
R4;R4;R4;R4; R4;R4;R4;R4; R4;R4;R4;R4; R4;R4;R4;R4;
|
||||
R4;R4;R4;R4; R4;R4;R4;R4; R4;R4;R4;R4; R4;R4;R4;R4; /*1024 */
|
||||
len -= 1024;
|
||||
}
|
||||
while (len >= 128) {
|
||||
READY(0);
|
||||
R4;R4;R4;R4; R4;R4;R4;R4; R4;R4;R4;R4; R4;R4;R4;R4;
|
||||
R4;R4;R4;R4; R4;R4;R4;R4; R4;R4;R4;R4; R4;R4;R4;R4; /* 128 */
|
||||
len -= 128;
|
||||
}
|
||||
while (len) {
|
||||
READY(0);
|
||||
R1;
|
||||
len--;
|
||||
}
|
||||
scsi_timeout_error:
|
||||
regs->sci_mode &= ~SCI_MODE_DMA;
|
||||
return count - len;
|
||||
}
|
||||
#undef R4
|
||||
#undef R1
|
||||
#endif
|
||||
|
||||
/* Some stuff from dp.c ... */
|
||||
|
||||
|
||||
#if 0
|
||||
/* Select a SCSI device.
|
||||
*/
|
||||
int scsi_select_ctlr (int ctlr)
|
||||
{
|
||||
/* May need other stuff here to syncronize between dp & aic. */
|
||||
|
||||
RD_ADR (u_char, ICU_IO) &= ~ICU_SCSI_BIT; /* i/o, not port */
|
||||
RD_ADR (u_char, ICU_DIR) &= ~ICU_SCSI_BIT; /* output */
|
||||
if (ctlr == NCR5380)
|
||||
RD_ADR (u_char, ICU_DATA) &= ~ICU_SCSI_BIT; /* select = 0 for 8490 */
|
||||
else
|
||||
RD_ADR (u_char, ICU_DATA) |= ICU_SCSI_BIT; /* select = 1 for AIC6250 */
|
||||
}
|
||||
#endif
|
||||
@ -1,6 +1,6 @@
|
||||
/* $NetBSD: scn.c,v 1.18 1995/06/09 04:36:30 phil Exp $ */
|
||||
/* $NetBSD: scn.c,v 1.19 1995/08/25 07:30:42 phil Exp $ */
|
||||
|
||||
/*-
|
||||
/*
|
||||
* Copyright (c) 1991 The Regents of the University of California.
|
||||
* All rights reserved.
|
||||
*
|
||||
@ -400,7 +400,7 @@ scnattach(parent, self, aux)
|
||||
|
||||
/* Set up the interrupts. */
|
||||
rs->uart->imr_int_bits
|
||||
|= (/*IMR_RX_INT | IMR_TX_INT |*/ IMR_BRK_INT) << (4*rs->a_or_b) | IMR_IP_INT;
|
||||
|= (/*IMR_RX_INT | IMR_TX_INT |*/ unit?IMR_BRK_INT:0) << (4*rs->a_or_b) | IMR_IP_INT;
|
||||
WR_ADR (u_char, rs->uart->imr_port, rs->uart->imr_int_bits);
|
||||
|
||||
splx(x);
|
||||
@ -640,7 +640,7 @@ scnintr(int line1)
|
||||
u_char rs_stat;
|
||||
u_char rs_ipcr;
|
||||
u_char ch;
|
||||
|
||||
|
||||
while (rs_work) {
|
||||
/* Loop to pick up ALL pending interrupts for device.
|
||||
*/
|
||||
@ -663,11 +663,22 @@ scnintr(int line1)
|
||||
rs0->lstatus = RD_ADR(u_char, rs0->stat_port);
|
||||
if (rs0->lstatus & SR_BREAK) {
|
||||
++rs0->break_interrupts;
|
||||
RD_ADR(u_char, rs0->recv_port); /* Toss zero character. */
|
||||
rs_stat &= ~IMR_RX_INT;
|
||||
}
|
||||
RD_ADR(u_char, rs0->recv_port); /* Toss zero character. */
|
||||
rs_stat &= ~IMR_RX_INT;
|
||||
WR_ADR (u_char, rs0->cmd_port, CMD_RESET_BRK);
|
||||
rs_work = TRUE;
|
||||
if (line1 == 1 && (rs0->lstatus & SR_BREAK)) {
|
||||
char c;
|
||||
printf("\r\nDo you wont a dump (y/n)? ");
|
||||
do
|
||||
c = cngetc();
|
||||
while (c != 'y' && c != 'n');
|
||||
printf("%c\r\n", c);
|
||||
if (c == 'y') {
|
||||
panic("Panic Button");
|
||||
}
|
||||
}
|
||||
}
|
||||
if (rs_stat & IMR_RX_INT && (tp0 != NULL)) {
|
||||
ch = RD_ADR(u_char, rs0->recv_port);
|
||||
@ -691,10 +702,10 @@ scnintr(int line1)
|
||||
rs1->lstatus = RD_ADR(u_char, rs1->stat_port);
|
||||
if (rs1->lstatus & SR_BREAK) {
|
||||
++rs1->break_interrupts;
|
||||
RD_ADR(u_char, rs1->recv_port); /* Toss zero character. */
|
||||
rs_stat &= ~IMR_RXB_INT;
|
||||
}
|
||||
RD_ADR(u_char, rs1->recv_port); /* Toss zero character. */
|
||||
WR_ADR (u_char, rs1->cmd_port, CMD_RESET_BRK);
|
||||
rs_stat &= ~IMR_RXB_INT;
|
||||
rs_work = TRUE;
|
||||
}
|
||||
if (rs_stat & IMR_RXB_INT && (tp1 != NULL)) {
|
||||
@ -1039,7 +1050,8 @@ char
|
||||
scncngetc(dev_t dev)
|
||||
{
|
||||
char c;
|
||||
int x=splhigh();
|
||||
int x = spltty();
|
||||
WR_ADR (u_char, SCN_FIRST_MAP_ADR + 14, (RTS_BIT | DTR_BIT));
|
||||
while (0 == (RD_ADR (u_char, SCN_CON_MAP_STAT) & SR_RX_RDY));
|
||||
c = RD_ADR(u_char, SCN_CON_MAP_DATA);
|
||||
splx(x);
|
||||
@ -1064,7 +1076,7 @@ int ___lines = 0;
|
||||
|
||||
scncnputc (dev_t dev, char c)
|
||||
{
|
||||
int x = splhigh();
|
||||
int x = spltty();
|
||||
|
||||
if (c == '\n') scncnputc(dev,'\r');
|
||||
if (_mapped) {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user