Disable array chain mode by default, since it is unused by any of
the current devices. Add more flexibility in the API.
This commit is contained in:
minoura
parent
60f029933e
commit
47d22455b3
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@ -1,4 +1,4 @@
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/* $NetBSD: dmacvar.h,v 1.3 2001/04/30 05:47:31 minoura Exp $ */
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/* $NetBSD: dmacvar.h,v 1.4 2001/05/02 12:48:24 minoura Exp $ */
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/*-
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* Copyright (c) 1997, 1998 The NetBSD Foundation, Inc.
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@ -58,10 +58,12 @@ struct dmac_dma_xfer {
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int dx_ocr; /* direction */
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int dx_scr; /* SCR value */
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void *dx_device; /* (initial) device address */
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bus_dma_segment_t dx_seg; /* b_d_s_t for the array chain */
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#ifdef DMAC_ARRAYCHAIN
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struct dmac_sg_array *dx_array; /* DMAC array chain */
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int dx_arraysize; /* size of above */
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int dx_done;
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#endif
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int dx_nextoff; /* for continued operation */
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int dx_nextsize;
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};
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/*
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@ -112,10 +114,17 @@ struct dmac_channel_stat *dmac_alloc_channel __P((struct device*, int, char*,
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/* ch, name, normalv, normal, errorv, error */
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int dmac_free_channel __P((struct device*, int, void*));
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/* ch, channel */
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struct dmac_dma_xfer *dmac_alloc_xfer __P((struct dmac_channel_stat*,
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bus_dma_tag_t, bus_dmamap_t));
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int dmac_load_xfer __P((struct device*, struct dmac_dma_xfer *));
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int dmac_start_xfer __P((struct device*, struct dmac_dma_xfer*));
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int dmac_start_xfer_offset __P((struct device*, struct dmac_dma_xfer*,
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u_int, u_int));
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int dmac_abort_xfer __P((struct device*, struct dmac_dma_xfer*));
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/* Compatibility function: alloc, fill defaults, load */
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struct dmac_dma_xfer *dmac_prepare_xfer __P((struct dmac_channel_stat*,
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bus_dma_tag_t,
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bus_dmamap_t,
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int, int, void*));
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/* chan, dmat, map, dir, sequence, dar */
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#define dmac_finish_xfer(xfer) free(xfer, M_DEVBUF)
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int dmac_start_xfer __P((struct device*, struct dmac_dma_xfer*));
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@ -1,4 +1,4 @@
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/* $NetBSD: intio_dmac.c,v 1.8 2001/04/30 05:47:31 minoura Exp $ */
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/* $NetBSD: intio_dmac.c,v 1.9 2001/05/02 12:48:24 minoura Exp $ */
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/*-
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* Copyright (c) 1997, 1998 The NetBSD Foundation, Inc.
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@ -45,8 +45,6 @@
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <sys/malloc.h>
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#include <sys/extent.h>
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#include <uvm/uvm_extern.h>
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#include <machine/bus.h>
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@ -66,7 +64,10 @@ int dmacdebug = 0;
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#endif
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static void dmac_init_channels __P((struct dmac_softc*));
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static int dmac_program_arraychain __P((struct device*, struct dmac_dma_xfer*));
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#ifdef DMAC_ARRAYCHAIN
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static int dmac_program_arraychain __P((struct device*, struct dmac_dma_xfer*,
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u_int, u_int));
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#endif
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static int dmac_done __P((void*));
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static int dmac_error __P((void*));
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@ -149,6 +150,9 @@ dmac_init_channels(sc)
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DMAC_CHAN_SIZE*i, DMAC_CHAN_SIZE,
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&sc->sc_channels[i].ch_bht);
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sc->sc_channels[i].ch_xfer.dx_dmamap = 0;
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/* reset the status register */
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bus_space_write_1(sc->sc_bst, sc->sc_channels[i].ch_bht,
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DMAC_REG_CSR, 0xff);
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}
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return;
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@ -175,7 +179,8 @@ dmac_alloc_channel(self, ch, name,
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char intrname[16];
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int r, dummy;
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DPRINTF (3, ("dmac_alloc_channel, %d, %s\n", ch, name));
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printf ("%s: allocating ch %d for %s.\n",
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sc->sc_dev.dv_xname, ch, name);
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DPRINTF (3, ("dmamap=%p\n", (void*) chan->ch_xfer.dx_dmamap));
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#ifdef DIAGNOSTIC
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if (ch < 0 || ch >= DMAC_NCHAN)
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@ -186,6 +191,7 @@ dmac_alloc_channel(self, ch, name,
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panic ("DMAC: wrong user name.");
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#endif
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#ifdef DMAC_ARRAYCHAIN
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/* allocate the DMAC arraychaining map */
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r = bus_dmamem_alloc(intio->sc_dmat,
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sizeof(struct dmac_sg_array) * DMAC_MAPSIZE,
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@ -200,12 +206,13 @@ dmac_alloc_channel(self, ch, name,
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BUS_DMA_NOWAIT|BUS_DMA_COHERENT);
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if (r)
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panic ("DMAC: cannot map DMA safe memory");
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#endif
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/* fill the channel status structure. */
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/* fill the channel status structure by the default values. */
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strcpy(chan->ch_name, name);
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chan->ch_dcr = (DMAC_DCR_XRM_CSWH | DMAC_DCR_OTYP_EASYNC |
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DMAC_DCR_OPS_8BIT);
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chan->ch_ocr = (DMAC_OCR_SIZE_BYTE_NOPACK | DMAC_OCR_REQG_EXTERNAL);
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chan->ch_ocr = (DMAC_OCR_SIZE_BYTE | DMAC_OCR_REQG_EXTERNAL);
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chan->ch_normalv = normalv;
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chan->ch_errorv = errorv;
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chan->ch_normal = normal;
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@ -253,7 +260,8 @@ dmac_free_channel(self, ch, channel)
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int ch;
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void *channel;
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{
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struct dmac_softc *sc = (void*) self;
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struct intio_softc *intio = (void*) self;
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struct dmac_softc *sc = (void*) intio->sc_dmac;
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struct dmac_channel_stat *chan = &sc->sc_channels[ch];
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DPRINTF (3, ("dmac_free_channel, %d\n", ch));
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@ -263,6 +271,11 @@ dmac_free_channel(self, ch, channel)
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if (ch != chan->ch_channel)
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return -1;
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#ifdef DMAC_ARRAYCHAIN
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bus_dmamem_unmap(intio->sc_dmat, (caddr_t) chan->ch_map,
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sizeof(struct dmac_sg_array) * DMAC_MAPSIZE);
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bus_dmamem_free(intio->sc_dmat, &chan->ch_seg[0], 1);
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#endif
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chan->ch_name[0] = 0;
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intio_intr_disestablish(chan->ch_normalv, channel);
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intio_intr_disestablish(chan->ch_errorv, channel);
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@ -273,6 +286,55 @@ dmac_free_channel(self, ch, channel)
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/*
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* Initialization / deinitialization per transfer.
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*/
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struct dmac_dma_xfer *
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dmac_alloc_xfer (chan, dmat, dmamap)
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struct dmac_channel_stat *chan;
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bus_dma_tag_t dmat;
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bus_dmamap_t dmamap;
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{
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struct dmac_dma_xfer *xf = &chan->ch_xfer;
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struct dmac_softc *sc = (struct dmac_softc*) chan->ch_softc;
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DPRINTF (3, ("dmac_alloc_xfer\n"));
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xf->dx_channel = chan;
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xf->dx_dmamap = dmamap;
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xf->dx_tag = dmat;
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#ifdef DMAC_ARRAYCHAIN
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xf->dx_array = chan->ch_map;
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xf->dx_done = 0;
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#endif
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return xf;
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}
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int
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dmac_load_xfer (self, xf)
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struct device *self;
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struct dmac_dma_xfer *xf;
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{
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struct dmac_softc *sc = (void*) self;
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struct dmac_channel_stat *chan = xf->dx_channel;
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DPRINTF (3, ("dmac_load_xfer\n"));
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xf->dx_ocr &= ~DMAC_OCR_CHAIN_MASK;
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if (xf->dx_dmamap->dm_nsegs == 1)
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xf->dx_ocr |= DMAC_OCR_CHAIN_DISABLED;
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else {
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xf->dx_ocr |= DMAC_OCR_CHAIN_ARRAY;
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xf->dx_nextoff = ~0;
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xf->dx_nextsize = ~0;
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}
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bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff);
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bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_SCR, xf->dx_scr);
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bus_space_write_1(sc->sc_bst, chan->ch_bht,
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DMAC_REG_OCR, (xf->dx_ocr | chan->ch_ocr));
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bus_space_write_4(sc->sc_bst, chan->ch_bht,
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DMAC_REG_DAR, (int) xf->dx_device);
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return 0;
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}
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struct dmac_dma_xfer *
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dmac_prepare_xfer (chan, dmat, dmamap, dir, scr, dar)
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struct dmac_channel_stat *chan;
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@ -281,17 +343,16 @@ dmac_prepare_xfer (chan, dmat, dmamap, dir, scr, dar)
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int dir, scr;
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void *dar;
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{
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struct dmac_dma_xfer *xf = &chan->ch_xfer;
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struct dmac_dma_xfer *xf;
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struct dmac_softc *sc = (struct dmac_softc*) chan->ch_softc;
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xf = dmac_alloc_xfer(chan, dmat, dmamap);
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DPRINTF (3, ("dmac_prepare_xfer\n"));
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xf->dx_channel = chan;
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xf->dx_dmamap = dmamap;
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xf->dx_tag = dmat;
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xf->dx_ocr = dir & DMAC_OCR_DIR_MASK;
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xf->dx_scr = scr & (DMAC_SCR_MAC_MASK|DMAC_SCR_DAC_MASK);
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xf->dx_device = dar;
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xf->dx_array = chan->ch_map;
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xf->dx_done = 0;
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dmac_load_xfer(&sc->sc_dev, xf);
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return xf;
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}
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@ -313,45 +374,88 @@ int
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dmac_start_xfer(self, xf)
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struct device *self;
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struct dmac_dma_xfer *xf;
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{
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return dmac_start_xfer_offset(self, xf, 0, 0);
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}
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int
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dmac_start_xfer_offset(self, xf, offset, size)
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struct device *self;
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struct dmac_dma_xfer *xf;
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u_int offset;
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u_int size;
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{
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struct dmac_softc *sc = (void*) self;
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struct dmac_channel_stat *chan = xf->dx_channel;
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int c;
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struct x68k_bus_dmamap *dmamap = xf->dx_dmamap;
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int c, go = DMAC_CCR_STR|DMAC_CCR_INT;
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DPRINTF (3, ("dmac_start_xfer\n"));
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#ifdef DMAC_DEBUG
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debugchan=chan;
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#endif
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if (size == 0) {
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#ifdef DIAGNOSTIC
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if (offset != 0)
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panic ("dmac_start_xfer_offset: invalid offset %x",
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offset);
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#endif
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size = dmamap->dm_mapsize;
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}
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#ifdef DMAC_ARRAYCHAIN
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#ifdef DIAGNOSTIC
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if (xf->dx_done)
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panic("dmac_start_xfer: DMA transfer in progress");
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#endif
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#endif
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DPRINTF (3, ("First program:\n"));
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#ifdef DIAGNOSTIC
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if ((offset >= dmamap->dm_mapsize) ||
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(offset + size > dmamap->dm_mapsize))
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panic ("dmac_start_xfer_offset: invalid offset: "
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"offset=%d, size=%d, mapsize=%d",
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offset, size, dmamap->dm_mapsize);
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#endif
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/* program DMAC in single block mode or array chainning mode */
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if (xf->dx_dmamap->dm_nsegs == 1) {
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if (dmamap->dm_nsegs == 1) {
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DPRINTF(3, ("single block mode\n"));
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bus_space_write_4(sc->sc_bst, chan->ch_bht,
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DMAC_REG_MAR,
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(int) xf->dx_dmamap->dm_segs[0].ds_addr);
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bus_space_write_2(sc->sc_bst, chan->ch_bht,
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DMAC_REG_MTCR,
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(int) xf->dx_dmamap->dm_segs[0].ds_len);
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#ifdef DIAGNOSTIC
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if (dmamap->dm_mapsize != dmamap->dm_segs[0].ds_len)
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panic ("dmac_start_xfer_offset: dmamap curruption");
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#endif
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if (offset == xf->dx_nextoff &&
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size == xf->dx_nextsize) {
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/* Use continued operation */
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go |= DMAC_CCR_CNT;
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xf->dx_nextoff += size;
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} else {
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bus_space_write_4(sc->sc_bst, chan->ch_bht,
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DMAC_REG_MAR,
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(int) dmamap->dm_segs[0].ds_addr
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+ offset);
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bus_space_write_2(sc->sc_bst, chan->ch_bht,
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DMAC_REG_MTCR, (int) size);
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xf->dx_nextoff = offset;
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xf->dx_nextsize = size;
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}
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#ifdef DMAC_ARRAYCHAIN
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xf->dx_done = 1;
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#endif
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} else {
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xf->dx_ocr |= DMAC_OCR_CHAIN_ARRAY;
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c = dmac_program_arraychain(self, xf);
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#ifdef DMAC_ARRAYCHAIN
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c = dmac_program_arraychain(self, xf, offset, size);
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bus_space_write_4(sc->sc_bst, chan->ch_bht,
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DMAC_REG_BAR, (int) chan->ch_seg[0].ds_addr);
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bus_space_write_2(sc->sc_bst, chan->ch_bht,
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DMAC_REG_BTCR, c);
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#else
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panic ("DMAC: unexpected use of arraychaining mode");
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#endif
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}
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/* setup the address/count registers */
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bus_space_write_1(sc->sc_bst, chan->ch_bht,
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DMAC_REG_SCR, xf->dx_scr);
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bus_space_write_1(sc->sc_bst, chan->ch_bht,
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DMAC_REG_OCR, (xf->dx_ocr | chan->ch_ocr));
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bus_space_write_4(sc->sc_bst, chan->ch_bht,
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DMAC_REG_DAR, (int) xf->dx_device);
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bus_space_write_1(sc->sc_bst, chan->ch_bht,
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DMAC_REG_CSR, 0xff);
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bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff);
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/* START!! */
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DDUMPREGS (3, ("first start\n"));
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@ -375,33 +479,51 @@ dmac_start_xfer(self, xf)
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dmar = bus_space_read_4(sc->sc_bst, chan->ch_bht, DMAC_REG_MAR);
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dbar = bus_space_read_4(sc->sc_bst, chan->ch_bht, DMAC_REG_BAR);
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#endif
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#ifdef DMAC_ARRAYCHAIN
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#if defined(M68040) || defined(M68060)
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if (mmutype == MMU_68040)
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dma_cachectl((caddr_t) xf->dx_array, xf->dx_arraysize);
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/* flush data cache for the map */
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if (dmamap->dm_nsegs != 1 && mmutype == MMU_68040)
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dma_cachectl((caddr_t) xf->dx_array,
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sizeof(struct dmac_sg_array) * c);
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#endif
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bus_space_write_1(sc->sc_bst, chan->ch_bht,
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DMAC_REG_CCR, DMAC_CCR_STR|DMAC_CCR_INT);
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#endif
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bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CCR, go);
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if (xf->dx_nextoff != ~0) {
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bus_space_write_4(sc->sc_bst, chan->ch_bht,
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DMAC_REG_BAR, xf->dx_nextoff);
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bus_space_write_2(sc->sc_bst, chan->ch_bht,
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DMAC_REG_BTCR, xf->dx_nextsize);
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}
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return 0;
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}
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#ifdef DMAC_ARRAYCHAIN
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static int
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dmac_program_arraychain(self, xf)
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dmac_program_arraychain(self, xf, offset, size)
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struct device *self;
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struct dmac_dma_xfer *xf;
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u_int offset;
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u_int size;
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{
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struct dmac_channel_stat *chan = xf->dx_channel;
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int ch = chan->ch_channel;
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struct x68k_bus_dmamap *map = xf->dx_dmamap;
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int i, j;
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/* XXX not yet!! */
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if (offset != 0 || size != map->dm_mapsize)
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panic ("dmac_program_arraychain: unsupported offset/size");
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DPRINTF (3, ("dmac_program_arraychain\n"));
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for (i=0, j=xf->dx_done; i<DMAC_MAPSIZE && j<map->dm_nsegs;
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i++, j++) {
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xf->dx_array[i].da_addr = map->dm_segs[j].ds_addr;
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#ifdef DIAGNOSTIC
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if (map->dm_segs[j].ds_len > 0xff00)
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panic ("dmac_program_arraychain: wrong map: %ld", map->dm_segs[j].ds_len);
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if (map->dm_segs[j].ds_len > DMAC_MAXSEGSZ)
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panic ("dmac_program_arraychain: wrong map: %ld",
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map->dm_segs[j].ds_len);
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#endif
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xf->dx_array[i].da_count = map->dm_segs[j].ds_len;
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}
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@ -409,6 +531,7 @@ dmac_program_arraychain(self, xf)
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return i;
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}
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#endif
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/*
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* interrupt handlers.
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@ -424,26 +547,30 @@ dmac_done(arg)
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int c;
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DPRINTF (3, ("dmac_done\n"));
|
||||
|
||||
bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff);
|
||||
|
||||
#ifdef DMAC_ARRAYCHAIN
|
||||
if (xf->dx_done == map->dm_nsegs) {
|
||||
xf->dx_done = 0;
|
||||
#endif
|
||||
/* Done */
|
||||
xf->dx_dmamap = 0;
|
||||
return (*chan->ch_normal) (chan->ch_normalarg);
|
||||
#ifdef DMAC_ARRAYCHAIN
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef DMAC_ARRAYCHAIN
|
||||
/* Continue transfer */
|
||||
DPRINTF (3, ("reprograming\n"));
|
||||
c = dmac_program_arraychain (&sc->sc_dev, xf);
|
||||
c = dmac_program_arraychain (&sc->sc_dev, xf, 0, map->dm_mapsize);
|
||||
|
||||
bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff);
|
||||
bus_space_write_4(sc->sc_bst, chan->ch_bht,
|
||||
DMAC_REG_BAR, (int) chan->ch_map);
|
||||
bus_space_write_4(sc->sc_bst, chan->ch_bht,
|
||||
DMAC_REG_DAR, (int) xf->dx_device);
|
||||
bus_space_write_1(sc->sc_bst, chan->ch_bht,
|
||||
DMAC_REG_CSR, 0xff);
|
||||
bus_space_write_2(sc->sc_bst, chan->ch_bht,
|
||||
DMAC_REG_BTCR, c);
|
||||
bus_space_write_2(sc->sc_bst, chan->ch_bht, DMAC_REG_BTCR, c);
|
||||
|
||||
/* START!! */
|
||||
DDUMPREGS (3, ("restart\n"));
|
||||
|
|
@ -451,6 +578,7 @@ dmac_done(arg)
|
|||
DMAC_REG_CCR, DMAC_CCR_STR|DMAC_CCR_INT);
|
||||
|
||||
return 1;
|
||||
#endif
|
||||
}
|
||||
|
||||
static int
|
||||
|
|
@ -466,7 +594,7 @@ dmac_error(arg)
|
|||
DPRINTF(5, ("registers were:\n"));
|
||||
#ifdef DMAC_DEBUG
|
||||
if ((dmacdebug & 0x0f) > 5) {
|
||||
printf ("CSR=%02x, CER=%02x, DCR=%02x, OCR=%02x, SCR=%02x,"
|
||||
printf ("CSR=%02x, CER=%02x, DCR=%02x, OCR=%02x, SCR=%02x, "
|
||||
"CCR=%02x, CPR=%02x, GCR=%02x\n",
|
||||
dcsr, dcer, ddcr, docr, dscr, dccr, dcpr, dgcr);
|
||||
printf ("NIVR=%02x, EIVR=%02x, MTCR=%04x, BTCR=%04x, "
|
||||
|
|
@ -477,12 +605,31 @@ dmac_error(arg)
|
|||
}
|
||||
#endif
|
||||
|
||||
/* Clear the status bits */
|
||||
bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff);
|
||||
DDUMPREGS(3, ("dmac_error\n"));
|
||||
|
||||
#ifdef DMAC_ARRAYCHAIN
|
||||
chan->ch_xfer.dx_done = 0;
|
||||
#endif
|
||||
|
||||
return (*chan->ch_error) (chan->ch_errorarg);
|
||||
}
|
||||
|
||||
int
|
||||
dmac_abort_xfer(self, xf)
|
||||
struct device *self;
|
||||
struct dmac_dma_xfer *xf;
|
||||
{
|
||||
struct dmac_softc *sc = (void*) self;
|
||||
struct dmac_channel_stat *chan = xf->dx_channel;
|
||||
struct x68k_bus_dmamap *dmamap = xf->dx_dmamap;
|
||||
|
||||
bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CCR,
|
||||
DMAC_CCR_INT | DMAC_CCR_HLT);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef DMAC_DEBUG
|
||||
static int
|
||||
|
|
|
|||
Loading…
Reference in New Issue