Add support for Rockchip eMMC PHY
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jmcneill
parent
a14204ca85
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478d6c3484
@ -1,4 +1,4 @@
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# $NetBSD: files.rockchip,v 1.16 2019/03/07 00:35:22 jakllsch Exp $
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# $NetBSD: files.rockchip,v 1.17 2019/03/10 11:10:21 jmcneill Exp $
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#
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# Configuration info for Rockchip family SoCs
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#
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@ -63,6 +63,11 @@ device rkpcie: pcibus, pcihost_fdt
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attach rkpcie at fdt
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file arch/arm/rockchip/rk3399_pcie.c rkpcie
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# eMMC PHY
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device rkemmcphy
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attach rkemmcphy at fdt
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file arch/arm/rockchip/rk_emmcphy.c rkemmcphy
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# SOC parameters
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defflag opt_soc.h SOC_ROCKCHIP
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defflag opt_soc.h SOC_RK3328: SOC_ROCKCHIP
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237
sys/arch/arm/rockchip/rk_emmcphy.c
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237
sys/arch/arm/rockchip/rk_emmcphy.c
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/* $NetBSD: rk_emmcphy.c,v 1.1 2019/03/10 11:10:21 jmcneill Exp $ */
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/*-
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* Copyright (c) 2019 Jared McNeill <jmcneill@invisible.ca>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: rk_emmcphy.c,v 1.1 2019/03/10 11:10:21 jmcneill Exp $");
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/device.h>
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#include <sys/intr.h>
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#include <sys/systm.h>
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#include <sys/mutex.h>
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#include <sys/kmem.h>
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#include <dev/fdt/fdtvar.h>
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#define GRF_EMMCPHY_CON0 0x00
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#define PHYCTRL_FRQSEL __BITS(13,12)
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#define PHYCTRL_FRQSEL_200M 0
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#define PHYCTRL_FRQSEL_50M 1
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#define PHYCTRL_FRQSEL_100M 2
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#define PHYCTRL_FRQSEL_150M 3
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#define PHYCTRL_OTAPDLYENA __BIT(11)
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#define PHYCTRL_OTAPDLYSEL __BITS(10,7)
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#define PHYCTRL_ITAPCHGWIN __BIT(6)
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#define PHYCTRL_ITAPDLYSEL __BITS(5,1)
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#define PHYCTRL_ITAPDLYENA __BIT(0)
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#define GRF_EMMCPHY_CON1 0x04
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#define PHYCTRL_CLKBUFSEL __BITS(8,6)
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#define PHYCTRL_SELDLYTXCLK __BIT(5)
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#define PHYCTRL_SELDLYRXCLK __BIT(4)
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#define PHYCTRL_STRBSEL __BITS(3,0)
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#define GRF_EMMCPHY_CON2 0x08
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#define PHYCTRL_REN_STRB __BIT(9)
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#define PHYCTRL_REN_CMD __BIT(8)
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#define PHYCTRL_REN_DAT __BITS(7,0)
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#define GRF_EMMCPHY_CON3 0x0c
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#define PHYCTRL_PU_STRB __BIT(9)
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#define PHYCTRL_PU_CMD __BIT(8)
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#define PHYCTRL_PU_DAT __BITS(7,0)
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#define GRF_EMMCPHY_CON4 0x10
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#define PHYCTRL_OD_RELEASE_CMD __BIT(9)
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#define PHYCTRL_OD_RELEASE_STRB __BIT(8)
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#define PHYCTRL_OD_RELEASE_DAT __BITS(7,0)
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#define GRF_EMMCPHY_CON5 0x14
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#define PHYCTRL_ODEN_STRB __BIT(9)
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#define PHYCTRL_ODEN_CMD __BIT(8)
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#define PHYCTRL_ODEN_DAT __BITS(7,0)
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#define GRF_EMMCPHY_CON6 0x18
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#define PHYCTRL_DLL_TRM_ICP __BITS(12,9)
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#define PHYCTRL_EN_RTRIM __BIT(8)
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#define PHYCTRL_RETRIM __BIT(7)
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#define PHYCTRL_DR_TY __BITS(6,4)
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#define PHYCTRL_RETENB __BIT(3)
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#define PHYCTRL_RETEN __BIT(2)
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#define PHYCTRL_ENDLL __BIT(1)
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#define PHYCTRL_PDB __BIT(0)
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#define GRF_EMMCPHY_STATUS 0x20
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#define PHYCTRL_CALDONE __BIT(6)
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#define PHYCTRL_DLLRDY __BIT(5)
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#define PHYCTRL_RTRIM __BITS(4,1)
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#define PHYCTRL_EXR_NINST __BIT(0)
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static const char * const compatible[] = {
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"rockchip,rk3399-emmc-phy",
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NULL
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};
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struct rk_emmcphy_softc {
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device_t sc_dev;
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bus_space_tag_t sc_bst;
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bus_space_handle_t sc_bsh;
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int sc_phandle;
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};
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#define RD4(sc, reg) \
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bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
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#define WR4(sc, reg, val) \
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bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
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static int rk_emmcphy_match(device_t, cfdata_t, void *);
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static void rk_emmcphy_attach(device_t, device_t, void *);
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CFATTACH_DECL_NEW(rkemmcphy, sizeof(struct rk_emmcphy_softc),
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rk_emmcphy_match, rk_emmcphy_attach, NULL, NULL);
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static void *
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rk_emmcphy_acquire(device_t dev, const void *data, size_t len)
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{
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if (len != 0)
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return NULL;
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return device_private(dev);
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}
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static void
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rk_emmcphy_release(device_t dev, void *priv)
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{
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}
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static int
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rk_emmcphy_enable(device_t dev, void *priv, bool enable)
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{
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struct rk_emmcphy_softc * const sc = priv;
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const int phandle = sc->sc_phandle;
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struct clk *clk;
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uint32_t mask, val;
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u_int rate, frqsel;
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/* Power down PHY and disable DLL before making changes */
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mask = PHYCTRL_ENDLL | PHYCTRL_PDB;
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val = 0;
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WR4(sc, GRF_EMMCPHY_CON6, (mask << 16) | val);
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if (enable == false)
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return 0;
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clk = fdtbus_clock_get(phandle, "emmcclk");
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rate = clk ? clk_get_rate(clk) : 0;
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if (rate != 0) {
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if (rate < 75000000)
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frqsel = PHYCTRL_FRQSEL_50M;
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else if (rate < 125000000)
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frqsel = PHYCTRL_FRQSEL_100M;
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else if (rate < 175000000)
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frqsel = PHYCTRL_FRQSEL_150M;
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else
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frqsel = PHYCTRL_FRQSEL_200M;
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} else {
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frqsel = PHYCTRL_FRQSEL_200M;
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}
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delay(3);
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/* Power up PHY */
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mask = PHYCTRL_PDB;
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val = PHYCTRL_PDB;
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WR4(sc, GRF_EMMCPHY_CON6, (mask << 16) | val);
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/* Wait for calibration */
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delay(10);
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val = RD4(sc, GRF_EMMCPHY_STATUS);
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if ((val & PHYCTRL_CALDONE) == 0) {
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device_printf(dev, "PHY calibration did not complete\n");
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return EIO;
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}
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/* Set DLL frequency */
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mask = PHYCTRL_FRQSEL;
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val = __SHIFTIN(frqsel, PHYCTRL_FRQSEL);
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WR4(sc, GRF_EMMCPHY_CON0, (mask << 16) | val);
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/* Enable DLL */
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mask = PHYCTRL_ENDLL;
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val = PHYCTRL_ENDLL;
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WR4(sc, GRF_EMMCPHY_CON6, (mask << 16) | val);
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if (rate != 0) {
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/* Wait for DLL ready */
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delay(50000);
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val = RD4(sc, GRF_EMMCPHY_STATUS);
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if ((val & PHYCTRL_DLLRDY) == 0) {
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device_printf(dev, "DLL loop failed to lock\n");
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return EIO;
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}
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}
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return 0;
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}
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static const struct fdtbus_phy_controller_func rk_emmcphy_funcs = {
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.acquire = rk_emmcphy_acquire,
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.release = rk_emmcphy_release,
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.enable = rk_emmcphy_enable,
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};
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static int
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rk_emmcphy_match(device_t parent, cfdata_t cf, void *aux)
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{
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struct fdt_attach_args * const faa = aux;
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return of_match_compatible(faa->faa_phandle, compatible);
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}
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static void
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rk_emmcphy_attach(device_t parent, device_t self, void *aux)
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{
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struct rk_emmcphy_softc * const sc = device_private(self);
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struct fdt_attach_args * const faa = aux;
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const int phandle = faa->faa_phandle;
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bus_addr_t addr;
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bus_size_t size;
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if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
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aprint_error(": couldn't get registers\n");
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return;
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}
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sc->sc_dev = self;
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sc->sc_phandle = phandle;
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sc->sc_bst = faa->faa_bst;
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if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) {
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aprint_error(": couldn't map registers\n");
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return;
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}
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aprint_naive("\n");
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aprint_normal(": eMMC PHY\n");
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fdtbus_register_phy_controller(self, phandle, &rk_emmcphy_funcs);
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}
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@ -1,5 +1,5 @@
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#
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# $NetBSD: GENERIC64,v 1.82 2019/03/06 19:36:59 jakllsch Exp $
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# $NetBSD: GENERIC64,v 1.83 2019/03/10 11:10:21 jmcneill Exp $
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#
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# GENERIC ARM (aarch64) kernel
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#
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@ -338,6 +338,7 @@ tegrartc* at fdt? # NVIDIA Tegra RTC
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dwcmmc* at fdt? # Designware SD/MMC
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mesongxmmc* at fdt? # Amlogic Meson GX eMMC/SD/SDIO controller
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mmcpwrseq* at fdt? # Simple MMC power sequence provider
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rkemmcphy* at fdt? # Rockchip eMMC PHY
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sdhc* at fdt? # SD Host Controller Interface
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sdhost* at fdt? # Broadcom BCM283x SD Host Interface
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sunximmc* at fdt? # Allwinner SD/MMC
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