Move all splxxx() and softint-related macros and prototypes to intr.h,
and include it where appropriate.
This commit is contained in:
scottr
parent
80a88edd60
commit
4765dedbf5
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@ -1,4 +1,4 @@
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/* $NetBSD: cpu.h,v 1.46 1997/03/15 05:39:47 briggs Exp $ */
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/* $NetBSD: cpu.h,v 1.47 1997/04/13 05:12:41 scottr Exp $ */
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/*
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* Copyright (c) 1988 University of Utah.
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@ -80,6 +80,11 @@
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#include <m68k/cpu.h>
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#define M68K_MMU_MOTOROLA
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/*
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* Get interrupt glue.
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*/
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#include <machine/intr.h>
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/*
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* definitions of cpu-dependent requirements
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* referenced in generic code
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@ -131,24 +136,6 @@ struct clockframe {
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int astpending; /* need to trap before returning to user mode */
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int want_resched; /* resched() was called */
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/*
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* simulated software interrupt register
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*/
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extern volatile u_int8_t ssir;
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#define SIR_NET 0x01
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#define SIR_CLOCK 0x02
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#define SIR_SERIAL 0x04
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#define siroff(mask) \
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__asm __volatile ( "andb %0,_ssir" : : "ir" (~(mask)));
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#define setsoftnet() \
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__asm __volatile ( "orb %0,_ssir" : : "i" (SIR_NET))
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#define setsoftclock() \
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__asm __volatile ( "orb %0,_ssir" : : "i" (SIR_CLOCK))
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#define setsoftserial() \
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__asm __volatile ( "orb %0,_ssir" : : "i" (SIR_SERIAL))
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#define CPU_CONSDEV 1
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#define CPU_MAXID 2
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@ -0,0 +1,86 @@
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/* $NetBSD: intr.h,v 1.1 1997/04/13 05:12:40 scottr Exp $ */
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#ifndef _MAC68K_INTR_H_
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#define _MAC68K_INTR_H_
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#ifdef _KERNEL
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/*
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* spl functions; all but spl0 are done in-line
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*/
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#define _spl(s) \
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({ \
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register int _spl_r; \
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\
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__asm __volatile ("clrl %0; movew sr,%0; movew %1,sr" : \
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"&=d" (_spl_r) : "di" (s)); \
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_spl_r; \
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})
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#define _splraise(s) \
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({ \
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register int _spl_r; \
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\
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__asm __volatile ("clrl %0; movew sr,%0;" : "&=d" (_spl_r) : ); \
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if ((_spl_r & PSL_IPL) < ((s) & PSL_IPL)) \
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__asm __volatile ("movew %0,sr;" : : "di" (s)); \
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_spl_r; \
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})
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/* spl0 requires checking for software interrupts */
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#define spl1() _spl(PSL_S|PSL_IPL1)
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#define spl2() _spl(PSL_S|PSL_IPL2)
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#define spl3() _spl(PSL_S|PSL_IPL3)
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#define spl4() _spl(PSL_S|PSL_IPL4)
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#define spl5() _spl(PSL_S|PSL_IPL5)
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#define spl6() _spl(PSL_S|PSL_IPL6)
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#define spl7() _spl(PSL_S|PSL_IPL7)
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/*
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* These should be used for:
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* 1) ensuring mutual exclusion (why use processor level?)
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* 2) allowing faster devices to take priority
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*
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* Note that on the Mac, most things are masked at spl1, almost
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* everything at spl2, and everything but the panic switch and
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* power at spl4.
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*/
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#define splsoftclock() spl1() /* disallow softclock */
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#define splsoftnet() spl1() /* disallow network */
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#define spltty() spl1() /* disallow tty (softserial & ADB) */
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#define splbio() spl2() /* disallow block I/O */
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#define splnet() spl2() /* disallow network */
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#define splimp() spl2() /* mutual exclusion for memory allocation */
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#define splclock() spl2() /* disallow clock (and other) interrupts */
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#define splstatclock() spl2() /* ditto */
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#define splzs() spl4() /* disallow serial hw interrupts */
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#define spladb() spl7() /* disallow adb interrupts */
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#define splhigh() spl7() /* disallow everything */
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#define splsched() spl7() /* disallow scheduling */
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/* watch out for side effects */
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#define splx(s) ((s) & PSL_IPL ? _spl(s) : spl0())
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/*
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* simulated software interrupt register
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*/
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extern volatile u_int8_t ssir;
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#define SIR_NET 0x01
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#define SIR_CLOCK 0x02
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#define SIR_SERIAL 0x04
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#define siron(mask) \
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__asm __volatile ( "orb %0,_ssir" : : "i" (mask))
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#define siroff(mask) \
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__asm __volatile ( "andb %0,_ssir" : : "ir" (~(mask)));
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#define setsoftnet() siron(SIR_NET)
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#define setsoftclock() siron(SIR_CLOCK)
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#define setsoftserial() siron(SIR_SERIAL)
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/* locore.s */
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int spl0 __P((void));
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#endif /* _KERNEL */
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#endif /* _MAC68K_INTR_H_ */
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@ -1,4 +1,4 @@
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/* $NetBSD: param.h,v 1.28 1997/03/01 06:57:45 scottr Exp $ */
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/* $NetBSD: param.h,v 1.29 1997/04/13 05:12:42 scottr Exp $ */
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/*
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* Copyright (c) 1988 University of Utah.
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@ -79,10 +79,6 @@
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#ifndef _PARAM_MACHINE_
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#define _PARAM_MACHINE_
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#ifndef PSL_IPL
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#include <machine/psl.h>
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#endif /* PSL_IPL */
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/*
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* Machine dependent constants for Macintosh II-and-similar series.
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*/
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@ -92,6 +88,11 @@
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#define MACHINE_ARCH "m68k"
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#define MID_MACHINE MID_M68K
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/*
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* Get interrupt glue.
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*/
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#include <machine/intr.h>
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/*
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* Round p (pointer or byte index) up to a correctly-aligned value
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* for all data types (int, long, ...). The result is u_int and
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@ -1,58 +1,3 @@
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/* $NetBSD: psl.h,v 1.12 1996/09/12 20:39:19 scottr Exp $ */
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/* $NetBSD: psl.h,v 1.13 1997/04/13 05:12:40 scottr Exp $ */
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#ifndef PSL_C
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#include <m68k/psl.h>
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#if defined(_KERNEL) && !defined(_LOCORE)
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/*
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* spl functions; all but spl0 are done in-line
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*/
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#define _spl(s) \
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({ \
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register int _spl_r; \
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\
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__asm __volatile ("clrl %0; movew sr,%0; movew %1,sr" : \
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"&=d" (_spl_r) : "di" (s)); \
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_spl_r; \
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})
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/* spl0 requires checking for software interrupts */
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#define spl1() _spl(PSL_S|PSL_IPL1)
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#define spl2() _spl(PSL_S|PSL_IPL2)
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#define spl3() _spl(PSL_S|PSL_IPL3)
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#define spl4() _spl(PSL_S|PSL_IPL4)
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#define spl5() _spl(PSL_S|PSL_IPL5)
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#define spl6() _spl(PSL_S|PSL_IPL6)
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#define spl7() _spl(PSL_S|PSL_IPL7)
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/*
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* These should be used for:
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* 1) ensuring mutual exclusion (why use processor level?)
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* 2) allowing faster devices to take priority
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*
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* Note that on the Mac, most things are masked at spl1, almost
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* everything at spl2, and everything but the panic switch and
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* power at spl4.
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*/
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#define splsoftclock() spl1() /* disallow softclock */
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#define splsoftnet() spl1() /* disallow network */
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#define spltty() spl1() /* disallow tty (softserial & ADB) */
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#define splbio() spl2() /* disallow block I/O */
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#define splnet() spl2() /* disallow network */
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#define splimp() spl2() /* mutual exclusion for memory allocation */
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#define splclock() spl2() /* disallow clock (and other) interrupts */
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#define splstatclock() spl2() /* ditto */
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#define splzs() spl4() /* disallow serial hw interrupts */
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#define spladb() spl7() /* disallow adb interrupts */
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#define splhigh() spl7() /* disallow everything */
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#define splsched() spl7() /* disallow scheduling */
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/* watch out for side effects */
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#define splx(s) ((s) & PSL_IPL ? _spl(s) : spl0())
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int spl0 __P((void));
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#endif /* _KERNEL && !_LOCORE */
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#endif /* ndef PSL_C */
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