- Move I219 DMA workaround into wm_flush_desc_rings() and call it before
wm_reset(). - Rewite I219 TX DMA workaround based on OpenBSD's one. - Add I219 RX DMA workaroud from OpenBSD.
This commit is contained in:
msaitoh
parent
48429bc512
commit
466c55b2a6
@ -1,4 +1,4 @@
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/* $NetBSD: if_wm.c,v 1.442 2016/11/10 06:57:15 msaitoh Exp $ */
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/* $NetBSD: if_wm.c,v 1.443 2016/11/10 08:35:24 msaitoh Exp $ */
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/*
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* Copyright (c) 2001, 2002, 2003, 2004 Wasabi Systems, Inc.
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@ -84,7 +84,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.442 2016/11/10 06:57:15 msaitoh Exp $");
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__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.443 2016/11/10 08:35:24 msaitoh Exp $");
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#ifdef _KERNEL_OPT
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#include "opt_net_mpsafe.h"
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@ -637,6 +637,7 @@ static void wm_lan_init_done(struct wm_softc *);
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static void wm_get_cfg_done(struct wm_softc *);
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static void wm_initialize_hardware_bits(struct wm_softc *);
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static uint32_t wm_rxpbs_adjust_82580(uint32_t);
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static void wm_flush_desc_rings(struct wm_softc *);
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static void wm_reset(struct wm_softc *);
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static int wm_add_rxbuf(struct wm_rxqueue *, int);
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static void wm_rxdrain(struct wm_rxqueue *);
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@ -3742,6 +3743,82 @@ wm_rxpbs_adjust_82580(uint32_t val)
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return rv;
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}
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static void
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wm_flush_desc_rings(struct wm_softc *sc)
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{
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pcireg_t preg;
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uint32_t reg;
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int nexttx;
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/* First, disable MULR fix in FEXTNVM11 */
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reg = CSR_READ(sc, WMREG_FEXTNVM11);
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reg |= FEXTNVM11_DIS_MULRFIX;
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CSR_WRITE(sc, WMREG_FEXTNVM11, reg);
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preg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, WM_PCI_DESCRING_STATUS);
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reg = CSR_READ(sc, WMREG_TDLEN(0));
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if (((preg & DESCRING_STATUS_FLUSH_REQ) != 0) && (reg != 0)) {
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struct wm_txqueue *txq;
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wiseman_txdesc_t *txd;
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/* TX */
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printf("%s: Need TX flush (reg = %08x, len = %u)\n",
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device_xname(sc->sc_dev), preg, reg);
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reg = CSR_READ(sc, WMREG_TCTL);
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CSR_WRITE(sc, WMREG_TCTL, reg | TCTL_EN);
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txq = &sc->sc_queue[0].wmq_txq;
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nexttx = txq->txq_next;
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txd = &txq->txq_descs[nexttx];
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wm_set_dma_addr(&txd->wtx_addr, WM_CDTXADDR(txq, nexttx));
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txd->wtx_cmdlen = htole32(WTX_CMD_IFCS| 512);
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txd->wtx_fields.wtxu_status = 0;
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txd->wtx_fields.wtxu_options = 0;
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txd->wtx_fields.wtxu_vlan = 0;
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bus_space_barrier(sc->sc_st, sc->sc_sh, 0, 0,
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BUS_SPACE_BARRIER_WRITE);
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txq->txq_next = WM_NEXTTX(txq, txq->txq_next);
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CSR_WRITE(sc, WMREG_TDT(0), txq->txq_next);
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bus_space_barrier(sc->sc_st, sc->sc_sh, 0, 0,
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BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
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delay(250);
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}
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preg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, WM_PCI_DESCRING_STATUS);
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if (preg & DESCRING_STATUS_FLUSH_REQ) {
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uint32_t rctl;
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/* RX */
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printf("%s: Need RX flush (reg = %08x)\n",
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device_xname(sc->sc_dev), preg);
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rctl = CSR_READ(sc, WMREG_RCTL);
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CSR_WRITE(sc, WMREG_RCTL, rctl & ~RCTL_EN);
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CSR_WRITE_FLUSH(sc);
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delay(150);
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reg = CSR_READ(sc, WMREG_RXDCTL(0));
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/* zero the lower 14 bits (prefetch and host thresholds) */
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reg &= 0xffffc000;
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/*
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* update thresholds: prefetch threshold to 31, host threshold
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* to 1 and make sure the granularity is "descriptors" and not
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* "cache lines"
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*/
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reg |= (0x1f | (1 << 8) | RXDCTL_GRAN);
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CSR_WRITE(sc, WMREG_RXDCTL(0), reg);
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/*
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* momentarily enable the RX ring for the changes to take
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* effect
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*/
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CSR_WRITE(sc, WMREG_RCTL, rctl | RCTL_EN);
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CSR_WRITE_FLUSH(sc);
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delay(150);
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CSR_WRITE(sc, WMREG_RCTL, rctl & ~RCTL_EN);
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}
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}
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/*
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* wm_reset:
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*
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@ -4663,6 +4740,10 @@ wm_init_locked(struct ifnet *ifp)
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ifp->if_collisions += CSR_READ(sc, WMREG_COLC);
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ifp->if_ierrors += CSR_READ(sc, WMREG_RXERRC);
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/* PCH_SPT hardware workaround */
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if (sc->sc_type == WM_T_PCH_SPT)
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wm_flush_desc_rings(sc);
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/* Reset the chip to a known state. */
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wm_reset(sc);
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@ -5237,49 +5318,6 @@ wm_stop_locked(struct ifnet *ifp, int disable)
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txs->txs_mbuf = NULL;
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}
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}
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if (sc->sc_type == WM_T_PCH_SPT) {
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pcireg_t preg;
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uint32_t reg;
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int nexttx;
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/* First, disable MULR fix in FEXTNVM11 */
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reg = CSR_READ(sc, WMREG_FEXTNVM11);
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reg |= FEXTNVM11_DIS_MULRFIX;
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CSR_WRITE(sc, WMREG_FEXTNVM11, reg);
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preg = pci_conf_read(sc->sc_pc, sc->sc_pcitag,
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WM_PCI_DESCRING_STATUS);
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reg = CSR_READ(sc, WMREG_TDLEN(0));
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printf("XXX RST: FLUSH = %08x, len = %u\n",
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(uint32_t)(preg & DESCRING_STATUS_FLUSH_REQ), reg);
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if (((preg & DESCRING_STATUS_FLUSH_REQ) != 0)
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&& (reg != 0)) {
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/* TX */
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printf("XXX need TX flush (reg = %08x)\n",
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preg);
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wm_init_tx_descs(sc, txq);
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wm_init_tx_regs(sc, wmq, txq);
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nexttx = txq->txq_next;
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wm_set_dma_addr(
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&txq->txq_descs[nexttx].wtx_addr,
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WM_CDTXADDR(txq, nexttx));
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txq->txq_descs[nexttx].wtx_cmdlen
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= htole32(WTX_CMD_IFCS | 512);
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wm_cdtxsync(txq, nexttx, 1,
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BUS_DMASYNC_PREREAD |BUS_DMASYNC_PREWRITE);
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CSR_WRITE(sc, WMREG_TCTL, TCTL_EN);
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CSR_WRITE(sc, WMREG_TDT(0), nexttx);
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CSR_WRITE_FLUSH(sc);
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delay(250);
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CSR_WRITE(sc, WMREG_TCTL, 0);
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}
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preg = pci_conf_read(sc->sc_pc, sc->sc_pcitag,
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WM_PCI_DESCRING_STATUS);
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if (preg & DESCRING_STATUS_FLUSH_REQ) {
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/* RX */
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printf("XXX need RX flush\n");
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}
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}
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mutex_exit(txq->txq_lock);
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}
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