Add per-segment and per-ragne flag (to store _BUS_DMAMAP_COHERENT).
Use the per-range flag to set the per-segment flag. This allows bus_dma to skip flushing for known coherent memory regions.
This commit is contained in:
matt
parent
bd4999fa18
commit
463cf12d17
@ -1,4 +1,4 @@
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/* $NetBSD: bus_dma.c,v 1.60 2012/10/06 02:58:39 matt Exp $ */
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/* $NetBSD: bus_dma.c,v 1.61 2012/10/17 20:17:18 matt Exp $ */
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/*-
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* Copyright (c) 1996, 1997, 1998 The NetBSD Foundation, Inc.
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@ -33,7 +33,7 @@
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#define _ARM32_BUS_DMA_PRIVATE
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: bus_dma.c,v 1.60 2012/10/06 02:58:39 matt Exp $");
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__KERNEL_RCSID(0, "$NetBSD: bus_dma.c,v 1.61 2012/10/17 20:17:18 matt Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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@ -139,7 +139,7 @@ _bus_dma_busaddr_to_paddr(bus_dma_tag_t t, bus_addr_t curaddr)
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*/
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static int
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_bus_dmamap_load_paddr(bus_dma_tag_t t, bus_dmamap_t map,
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bus_addr_t paddr, bus_size_t size)
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bus_addr_t paddr, bus_size_t size, bool coherent)
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{
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bus_dma_segment_t * const segs = map->dm_segs;
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int nseg = map->dm_nsegs;
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@ -147,6 +147,7 @@ _bus_dmamap_load_paddr(bus_dma_tag_t t, bus_dmamap_t map,
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bus_addr_t bmask = ~(map->_dm_boundary - 1);
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bus_addr_t curaddr;
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bus_size_t sgsize;
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uint32_t _ds_flags = coherent ? _BUS_DMAMAP_COHERENT : 0;
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if (nseg > 0)
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lastaddr = segs[nseg-1].ds_addr + segs[nseg-1].ds_len;
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@ -163,7 +164,16 @@ _bus_dmamap_load_paddr(bus_dma_tag_t t, bus_dmamap_t map,
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_bus_dma_paddr_inrange(t->_ranges, t->_nranges, paddr);
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if (dr == NULL)
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return (EINVAL);
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/*
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* If this region is coherent, mark the segment as coherent.
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*/
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_ds_flags |= dr->dr_flags & _BUS_DMAMAP_COHERENT;
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#if 0
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printf("%p: %#lx: range %#lx/%#lx/%#lx/%#x: %#x\n",
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t, paddr, dr->dr_sysbase, dr->dr_busbase,
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dr->dr_len, dr->dr_flags, _ds_flags);
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#endif
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/*
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* In a valid DMA range. Translate the physical
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* memory address to an address in the DMA window.
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@ -189,6 +199,7 @@ _bus_dmamap_load_paddr(bus_dma_tag_t t, bus_dmamap_t map,
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*/
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if (nseg > 0 && curaddr == lastaddr &&
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segs[nseg-1].ds_len + sgsize <= map->dm_maxsegsz &&
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((segs[nseg-1]._ds_flags ^ _ds_flags) & _BUS_DMAMAP_COHERENT) == 0 &&
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(map->_dm_boundary == 0 ||
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(segs[nseg-1].ds_addr & bmask) == (curaddr & bmask))) {
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/* coalesce */
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@ -199,6 +210,7 @@ _bus_dmamap_load_paddr(bus_dma_tag_t t, bus_dmamap_t map,
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/* new segment */
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segs[nseg].ds_addr = curaddr;
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segs[nseg].ds_len = sgsize;
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segs[nseg]._ds_flags = _ds_flags;
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nseg++;
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}
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@ -208,7 +220,8 @@ _bus_dmamap_load_paddr(bus_dma_tag_t t, bus_dmamap_t map,
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size -= sgsize;
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if (size > 0)
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goto again;
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map->_dm_flags &= (_ds_flags & _BUS_DMAMAP_COHERENT);
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map->dm_nsegs = nseg;
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return (0);
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}
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@ -511,11 +524,8 @@ _bus_dmamap_load_mbuf(bus_dma_tag_t t, bus_dmamap_t map, struct mbuf *m0,
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if (m0->m_pkthdr.len > map->_dm_size)
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return (EINVAL);
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/*
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* Mbuf chains should almost never have coherent (i.e.
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* un-cached) mappings, so clear that flag now.
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*/
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map->_dm_flags &= ~_BUS_DMAMAP_COHERENT;
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/* _bus_dmamap_load_paddr() clears this if we're not... */
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map->_dm_flags |= _BUS_DMAMAP_COHERENT;
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error = 0;
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for (m = m0; m != NULL && error == 0; m = m->m_next) {
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@ -541,7 +551,8 @@ _bus_dmamap_load_mbuf(bus_dma_tag_t t, bus_dmamap_t map, struct mbuf *m0,
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paddr = m->m_ext.ext_paddr +
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(m->m_data - m->m_ext.ext_buf);
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size = m->m_len;
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error = _bus_dmamap_load_paddr(t, map, paddr, size);
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error = _bus_dmamap_load_paddr(t, map, paddr, size,
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false);
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break;
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case M_EXT|M_EXT_PAGES:
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@ -570,7 +581,7 @@ _bus_dmamap_load_mbuf(bus_dma_tag_t t, bus_dmamap_t map, struct mbuf *m0,
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paddr = VM_PAGE_TO_PHYS(pg) + offset;
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error = _bus_dmamap_load_paddr(t, map,
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paddr, size);
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paddr, size, false);
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if (error)
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break;
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offset = 0;
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@ -582,7 +593,8 @@ _bus_dmamap_load_mbuf(bus_dma_tag_t t, bus_dmamap_t map, struct mbuf *m0,
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paddr = m->m_paddr + M_BUFOFFSET(m) +
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(m->m_data - M_BUFADDR(m));
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size = m->m_len;
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error = _bus_dmamap_load_paddr(t, map, paddr, size);
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error = _bus_dmamap_load_paddr(t, map, paddr, size,
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false);
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break;
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default:
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@ -766,7 +778,9 @@ _bus_dmamap_sync_linear(bus_dma_tag_t t, bus_dmamap_t map, bus_addr_t offset,
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paddr_t pa = _bus_dma_busaddr_to_paddr(t, ds->ds_addr + offset);
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size_t seglen = min(len, ds->ds_len - offset);
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_bus_dmamap_sync_segment(va + offset, pa, seglen, ops, false);
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if ((ds->_ds_flags & _BUS_DMAMAP_COHERENT) == 0)
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_bus_dmamap_sync_segment(va + offset, pa, seglen, ops,
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false);
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offset += seglen;
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len -= seglen;
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@ -819,7 +833,9 @@ _bus_dmamap_sync_mbuf(bus_dma_tag_t t, bus_dmamap_t map, bus_size_t offset,
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* cache), this will have to be revisited.
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*/
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_bus_dmamap_sync_segment(va, pa, seglen, ops, M_ROMAP(m));
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if ((ds->_ds_flags & _BUS_DMAMAP_COHERENT) == 0)
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_bus_dmamap_sync_segment(va, pa, seglen, ops,
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M_ROMAP(m));
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voff += seglen;
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ds_off += seglen;
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len -= seglen;
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@ -857,7 +873,8 @@ _bus_dmamap_sync_uio(bus_dma_tag_t t, bus_dmamap_t map, bus_addr_t offset,
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vaddr_t va = (vaddr_t) iov->iov_base + voff;
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paddr_t pa = _bus_dma_busaddr_to_paddr(t, ds->ds_addr + ds_off);
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_bus_dmamap_sync_segment(va, pa, seglen, ops, false);
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if ((ds->_ds_flags & _BUS_DMAMAP_COHERENT) == 0)
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_bus_dmamap_sync_segment(va, pa, seglen, ops, false);
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voff += seglen;
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ds_off += seglen;
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@ -924,8 +941,9 @@ _bus_dmamap_sync(bus_dma_tag_t t, bus_dmamap_t map, bus_addr_t offset,
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#endif
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const int pre_ops = ops & (BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
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if (!bouncing && pre_ops == 0)
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if (!bouncing && pre_ops == 0) {
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return;
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}
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#ifdef _ARM32_NEED_BUS_DMA_BOUNCE
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if (bouncing && (ops & BUS_DMASYNC_PREWRITE)) {
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@ -1283,11 +1301,8 @@ _bus_dmamap_load_buffer(bus_dma_tag_t t, bus_dmamap_t map, void *buf,
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bus_size_t sgsize;
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bus_addr_t curaddr;
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vaddr_t vaddr = (vaddr_t)buf;
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pd_entry_t *pde;
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pt_entry_t pte;
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int error;
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pmap_t pmap;
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pt_entry_t *ptep;
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#ifdef DEBUG_DMA
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printf("_bus_dmamem_load_buffer(buf=%p, len=%lx, flags=%d)\n",
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@ -1303,7 +1318,10 @@ _bus_dmamap_load_buffer(bus_dma_tag_t t, bus_dmamap_t map, void *buf,
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* XXX Doesn't support checking for coherent mappings
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* XXX in user address space.
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*/
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bool coherent;
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if (__predict_true(pmap == pmap_kernel())) {
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pd_entry_t *pde;
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pt_entry_t *ptep;
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(void) pmap_get_pde_pte(pmap, vaddr, &pde, &ptep);
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if (__predict_false(pmap_pde_section(pde))) {
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paddr_t s_frame = L1_S_FRAME;
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@ -1315,32 +1333,24 @@ _bus_dmamap_load_buffer(bus_dma_tag_t t, bus_dmamap_t map, void *buf,
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}
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#endif
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curaddr = (*pde & s_frame) | (vaddr & s_offset);
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if (*pde & L1_S_CACHE_MASK) {
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map->_dm_flags &= ~_BUS_DMAMAP_COHERENT;
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}
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coherent = (*pde & L1_S_CACHE_MASK) != 0;
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} else {
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pte = *ptep;
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pt_entry_t pte = *ptep;
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KDASSERT((pte & L2_TYPE_MASK) != L2_TYPE_INV);
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if (__predict_false((pte & L2_TYPE_MASK)
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== L2_TYPE_L)) {
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curaddr = (pte & L2_L_FRAME) |
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(vaddr & L2_L_OFFSET);
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if (pte & L2_L_CACHE_MASK) {
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map->_dm_flags &=
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~_BUS_DMAMAP_COHERENT;
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}
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coherent = (pte & L2_L_CACHE_MASK) != 0;
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} else {
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curaddr = (pte & L2_S_FRAME) |
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(vaddr & L2_S_OFFSET);
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if (pte & L2_S_CACHE_MASK) {
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map->_dm_flags &=
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~_BUS_DMAMAP_COHERENT;
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}
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coherent = (pte & L2_S_CACHE_MASK) != 0;
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}
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}
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} else {
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(void) pmap_extract(pmap, vaddr, &curaddr);
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map->_dm_flags &= ~_BUS_DMAMAP_COHERENT;
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coherent = false;
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}
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/*
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@ -1350,7 +1360,8 @@ _bus_dmamap_load_buffer(bus_dma_tag_t t, bus_dmamap_t map, void *buf,
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if (buflen < sgsize)
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sgsize = buflen;
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error = _bus_dmamap_load_paddr(t, map, curaddr, sgsize);
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error = _bus_dmamap_load_paddr(t, map, curaddr, sgsize,
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coherent);
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if (error)
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return (error);
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@ -1,4 +1,4 @@
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/* $NetBSD: bus_defs.h,v 1.2 2012/09/18 05:47:27 matt Exp $ */
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/* $NetBSD: bus_defs.h,v 1.3 2012/10/17 20:17:18 matt Exp $ */
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/*-
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* Copyright (c) 1996, 1997, 1998, 2001 The NetBSD Foundation, Inc.
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@ -330,6 +330,7 @@ struct arm32_bus_dma_segment {
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*/
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bus_addr_t ds_addr; /* DMA address */
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bus_size_t ds_len; /* length of transfer */
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uint32_t _ds_flags; /* _BUS_DMAMAP_COHERENT */
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};
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typedef struct arm32_bus_dma_segment bus_dma_segment_t;
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@ -342,6 +343,7 @@ struct arm32_dma_range {
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bus_addr_t dr_sysbase; /* system base address */
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bus_addr_t dr_busbase; /* appears here on bus */
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bus_size_t dr_len; /* length of range */
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uint32_t dr_flags; /* flags for range */
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};
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/*
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