Clean up the bus space function namespace somewhat; make sure they don't
collide with function names used in other parts of the kernel.
This commit is contained in:
thorpej
parent
ad3073beaf
commit
46320bb017
@ -1,4 +1,4 @@
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/* $NetBSD: bus_space_notimpl.S,v 1.3 1998/04/01 22:55:45 mark Exp $ */
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/* $NetBSD: bus_space_notimpl.S,v 1.4 1998/06/28 07:27:51 thorpej Exp $ */
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/*
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* Copyright (c) 1997 Mark Brinicombe.
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@ -42,7 +42,7 @@
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#define __C(x,y) __CONCAT(x,y)
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#define __S(s) __STRING(s)
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#define NAME(func) __C(__C(BUS_SPACE,_),func)
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#define NAME(func) __C(BUS_SPACE,__C(_bs_,func))
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#define LNAME(func) __C(L,NAME(func))
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#define GLOBAL(func) .global __C(_,NAME(func))
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@ -1,4 +1,4 @@
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/* $NetBSD: bus.h,v 1.12 1998/06/28 03:22:10 thorpej Exp $ */
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/* $NetBSD: bus.h,v 1.13 1998/06/28 07:27:52 thorpej Exp $ */
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/*-
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* Copyright (c) 1996, 1997, 1998 The NetBSD Foundation, Inc.
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@ -371,177 +371,177 @@ struct bus_space {
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*/
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#define bs_map_proto(f) \
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int __bs_c(f,_map) __P((void *t, bus_addr_t addr, \
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int __bs_c(f,_bs_map) __P((void *t, bus_addr_t addr, \
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bus_size_t size, int cacheable, bus_space_handle_t *bshp));
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#define bs_unmap_proto(f) \
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void __bs_c(f,_unmap) __P((void *t, bus_space_handle_t bsh, \
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void __bs_c(f,_bs_unmap) __P((void *t, bus_space_handle_t bsh, \
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bus_size_t size));
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#define bs_subregion_proto(f) \
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int __bs_c(f,_subregion) __P((void *t, bus_space_handle_t bsh, \
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int __bs_c(f,_bs_subregion) __P((void *t, bus_space_handle_t bsh, \
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bus_size_t offset, bus_size_t size, \
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bus_space_handle_t *nbshp));
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#define bs_alloc_proto(f) \
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int __bs_c(f,_alloc) __P((void *t, bus_addr_t rstart, \
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int __bs_c(f,_bs_alloc) __P((void *t, bus_addr_t rstart, \
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bus_addr_t rend, bus_size_t size, bus_size_t align, \
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bus_size_t boundary, int cacheable, bus_addr_t *addrp, \
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bus_space_handle_t *bshp));
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#define bs_free_proto(f) \
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void __bs_c(f,_free) __P((void *t, bus_space_handle_t bsh, \
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void __bs_c(f,_bs_free) __P((void *t, bus_space_handle_t bsh, \
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bus_size_t size));
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#define bs_barrier_proto(f) \
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void __bs_c(f,_barrier) __P((void *t, bus_space_handle_t bsh, \
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void __bs_c(f,_bs_barrier) __P((void *t, bus_space_handle_t bsh, \
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bus_size_t offset, bus_size_t len, int flags));
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#define bs_r_1_proto(f) \
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u_int8_t __bs_c(f,_r_1) __P((void *t, bus_space_handle_t bsh, \
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u_int8_t __bs_c(f,_bs_r_1) __P((void *t, bus_space_handle_t bsh, \
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bus_size_t offset));
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#define bs_r_2_proto(f) \
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u_int16_t __bs_c(f,_r_2) __P((void *t, bus_space_handle_t bsh, \
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u_int16_t __bs_c(f,_bs_r_2) __P((void *t, bus_space_handle_t bsh, \
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bus_size_t offset));
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#define bs_r_4_proto(f) \
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u_int32_t __bs_c(f,_r_4) __P((void *t, bus_space_handle_t bsh, \
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u_int32_t __bs_c(f,_bs_r_4) __P((void *t, bus_space_handle_t bsh, \
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bus_size_t offset));
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#define bs_r_8_proto(f) \
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u_int64_t __bs_c(f,_r_8) __P((void *t, bus_space_handle_t bsh, \
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u_int64_t __bs_c(f,_bs_r_8) __P((void *t, bus_space_handle_t bsh, \
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bus_size_t offset));
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#define bs_w_1_proto(f) \
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void __bs_c(f,_w_1) __P((void *t, bus_space_handle_t bsh, \
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void __bs_c(f,_bs_w_1) __P((void *t, bus_space_handle_t bsh, \
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bus_size_t offset, u_int8_t value));
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#define bs_w_2_proto(f) \
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void __bs_c(f,_w_2) __P((void *t, bus_space_handle_t bsh, \
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void __bs_c(f,_bs_w_2) __P((void *t, bus_space_handle_t bsh, \
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bus_size_t offset, u_int16_t value));
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#define bs_w_4_proto(f) \
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void __bs_c(f,_w_4) __P((void *t, bus_space_handle_t bsh, \
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void __bs_c(f,_bs_w_4) __P((void *t, bus_space_handle_t bsh, \
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bus_size_t offset, u_int32_t value));
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#define bs_w_8_proto(f) \
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void __bs_c(f,_w_8) __P((void *t, bus_space_handle_t bsh, \
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void __bs_c(f,_bs_w_8) __P((void *t, bus_space_handle_t bsh, \
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bus_size_t offset, u_int64_t value));
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#define bs_rm_1_proto(f) \
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void __bs_c(f,_rm_1) __P((void *t, bus_space_handle_t bsh, \
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void __bs_c(f,_bs_rm_1) __P((void *t, bus_space_handle_t bsh, \
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bus_size_t offset, u_int8_t *addr, bus_size_t count));
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#define bs_rm_2_proto(f) \
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void __bs_c(f,_rm_2) __P((void *t, bus_space_handle_t bsh, \
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void __bs_c(f,_bs_rm_2) __P((void *t, bus_space_handle_t bsh, \
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bus_size_t offset, u_int16_t *addr, bus_size_t count));
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#define bs_rm_4_proto(f) \
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void __bs_c(f,_rm_4) __P((void *t, bus_space_handle_t bsh, \
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void __bs_c(f,_bs_rm_4) __P((void *t, bus_space_handle_t bsh, \
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bus_size_t offset, u_int32_t *addr, bus_size_t count));
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#define bs_rm_8_proto(f) \
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void __bs_c(f,_rm_8) __P((void *t, bus_space_handle_t bsh, \
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void __bs_c(f,_bs_rm_8) __P((void *t, bus_space_handle_t bsh, \
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bus_size_t offset, u_int64_t *addr, bus_size_t count));
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#define bs_wm_1_proto(f) \
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void __bs_c(f,_wm_1) __P((void *t, bus_space_handle_t bsh, \
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void __bs_c(f,_bs_wm_1) __P((void *t, bus_space_handle_t bsh, \
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bus_size_t offset, const u_int8_t *addr, bus_size_t count));
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#define bs_wm_2_proto(f) \
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void __bs_c(f,_wm_2) __P((void *t, bus_space_handle_t bsh, \
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void __bs_c(f,_bs_wm_2) __P((void *t, bus_space_handle_t bsh, \
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bus_size_t offset, const u_int16_t *addr, bus_size_t count));
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#define bs_wm_4_proto(f) \
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void __bs_c(f,_wm_4) __P((void *t, bus_space_handle_t bsh, \
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void __bs_c(f,_bs_wm_4) __P((void *t, bus_space_handle_t bsh, \
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bus_size_t offset, const u_int32_t *addr, bus_size_t count));
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#define bs_wm_8_proto(f) \
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void __bs_c(f,_wm_8) __P((void *t, bus_space_handle_t bsh, \
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void __bs_c(f,_bs_wm_8) __P((void *t, bus_space_handle_t bsh, \
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bus_size_t offset, const u_int64_t *addr, bus_size_t count));
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#define bs_rr_1_proto(f) \
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void __bs_c(f, _rr_1) __P((void *t, bus_space_handle_t bsh, \
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void __bs_c(f, _bs_rr_1) __P((void *t, bus_space_handle_t bsh, \
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bus_size_t offset, u_int8_t *addr, bus_size_t count));
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#define bs_rr_2_proto(f) \
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void __bs_c(f, _rr_2) __P((void *t, bus_space_handle_t bsh, \
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void __bs_c(f, _bs_rr_2) __P((void *t, bus_space_handle_t bsh, \
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bus_size_t offset, u_int16_t *addr, bus_size_t count));
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#define bs_rr_4_proto(f) \
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void __bs_c(f, _rr_4) __P((void *t, bus_space_handle_t bsh, \
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void __bs_c(f, _bs_rr_4) __P((void *t, bus_space_handle_t bsh, \
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bus_size_t offset, u_int32_t *addr, bus_size_t count));
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#define bs_rr_8_proto(f) \
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void __bs_c(f, _rr_8) __P((void *t, bus_space_handle_t bsh, \
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void __bs_c(f, _bs_rr_8) __P((void *t, bus_space_handle_t bsh, \
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bus_size_t offset, u_int64_t *addr, bus_size_t count));
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#define bs_wr_1_proto(f) \
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void __bs_c(f, _wr_1) __P((void *t, bus_space_handle_t bsh, \
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void __bs_c(f, _bs_wr_1) __P((void *t, bus_space_handle_t bsh, \
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bus_size_t offset, const u_int8_t *addr, bus_size_t count));
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#define bs_wr_2_proto(f) \
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void __bs_c(f, _wr_2) __P((void *t, bus_space_handle_t bsh, \
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void __bs_c(f, _bs_wr_2) __P((void *t, bus_space_handle_t bsh, \
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bus_size_t offset, const u_int16_t *addr, bus_size_t count));
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#define bs_wr_4_proto(f) \
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void __bs_c(f, _wr_4) __P((void *t, bus_space_handle_t bsh, \
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void __bs_c(f, _bs_wr_4) __P((void *t, bus_space_handle_t bsh, \
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bus_size_t offset, const u_int32_t *addr, bus_size_t count));
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#define bs_wr_8_proto(f) \
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void __bs_c(f, _wr_8) __P((void *t, bus_space_handle_t bsh, \
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void __bs_c(f, _bs_wr_8) __P((void *t, bus_space_handle_t bsh, \
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bus_size_t offset, const u_int64_t *addr, bus_size_t count));
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#define bs_sm_1_proto(f) \
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void __bs_c(f,_sm_1) __P((void *t, bus_space_handle_t bsh, \
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void __bs_c(f,_bs_sm_1) __P((void *t, bus_space_handle_t bsh, \
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bus_size_t offset, u_int8_t value, bus_size_t count));
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#define bs_sm_2_proto(f) \
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void __bs_c(f,_sm_2) __P((void *t, bus_space_handle_t bsh, \
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void __bs_c(f,_bs_sm_2) __P((void *t, bus_space_handle_t bsh, \
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bus_size_t offset, u_int16_t value, bus_size_t count));
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#define bs_sm_4_proto(f) \
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void __bs_c(f,_sm_4) __P((void *t, bus_space_handle_t bsh, \
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void __bs_c(f,_bs_sm_4) __P((void *t, bus_space_handle_t bsh, \
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bus_size_t offset, u_int32_t value, bus_size_t count));
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#define bs_sm_8_proto(f) \
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void __bs_c(f,_sm_8) __P((void *t, bus_space_handle_t bsh, \
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void __bs_c(f,_bs_sm_8) __P((void *t, bus_space_handle_t bsh, \
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bus_size_t offset, u_int64_t value, bus_size_t count));
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#define bs_sr_1_proto(f) \
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void __bs_c(f,_sr_1) __P((void *t, bus_space_handle_t bsh, \
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void __bs_c(f,_bs_sr_1) __P((void *t, bus_space_handle_t bsh, \
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bus_size_t offset, u_int8_t value, bus_size_t count));
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#define bs_sr_2_proto(f) \
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void __bs_c(f,_sr_2) __P((void *t, bus_space_handle_t bsh, \
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void __bs_c(f,_bs_sr_2) __P((void *t, bus_space_handle_t bsh, \
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bus_size_t offset, u_int16_t value, bus_size_t count));
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#define bs_sr_4_proto(f) \
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void __bs_c(f,_sr_4) __P((void *t, bus_space_handle_t bsh, \
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void __bs_c(f,_bs_sr_4) __P((void *t, bus_space_handle_t bsh, \
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bus_size_t offset, u_int32_t value, bus_size_t count));
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#define bs_sr_8_proto(f) \
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void __bs_c(f,_sr_8) __P((void *t, bus_space_handle_t bsh, \
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void __bs_c(f,_bs_sr_8) __P((void *t, bus_space_handle_t bsh, \
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bus_size_t offset, u_int64_t value, bus_size_t count));
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#define bs_c_1_proto(f) \
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void __bs_c(f,_c_1) __P((void *t, bus_space_handle_t bsh1, \
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void __bs_c(f,_bs_c_1) __P((void *t, bus_space_handle_t bsh1, \
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bus_size_t offset1, bus_space_handle_t bsh2, \
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bus_size_t offset2, bus_size_t count));
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#define bs_c_2_proto(f) \
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void __bs_c(f,_c_2) __P((void *t, bus_space_handle_t bsh1, \
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void __bs_c(f,_bs_c_2) __P((void *t, bus_space_handle_t bsh1, \
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bus_size_t offset1, bus_space_handle_t bsh2, \
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bus_size_t offset2, bus_size_t count));
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#define bs_c_4_proto(f) \
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void __bs_c(f,_c_4) __P((void *t, bus_space_handle_t bsh1, \
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void __bs_c(f,_bs_c_4) __P((void *t, bus_space_handle_t bsh1, \
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bus_size_t offset1, bus_space_handle_t bsh2, \
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bus_size_t offset2, bus_size_t count));
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#define bs_c_8_proto(f) \
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void __bs_c(f,_c_8) __P((void *t, bus_space_handle_t bsh1, \
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void __bs_c(f,_bs_c_8) __P((void *t, bus_space_handle_t bsh1, \
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bus_size_t offset1, bus_space_handle_t bsh2, \
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bus_size_t offset2, bus_size_t count));
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@ -1,4 +1,4 @@
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/* $NetBSD: iomd_io.c,v 1.1 1997/10/14 10:58:50 mark Exp $ */
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/* $NetBSD: iomd_io.c,v 1.2 1998/06/28 07:27:52 thorpej Exp $ */
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/*
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* Copyright (c) 1997 Mark Brinicombe.
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@ -53,70 +53,70 @@ struct bus_space iomd_bs_tag = {
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NULL,
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/* mapping/unmapping */
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iomd_map,
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iomd_unmap,
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iomd_subregion,
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iomd_bs_map,
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iomd_bs_unmap,
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iomd_bs_subregion,
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/* allocation/deallocation */
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iomd_alloc,
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iomd_free,
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iomd_bs_alloc,
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iomd_bs_free,
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/* barrier */
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iomd_barrier,
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iomd_bs_barrier,
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/* read (single) */
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iomd_r_1,
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iomd_r_2,
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iomd_r_4,
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bs_notimpl_r_8,
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iomd_bs_r_1,
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iomd_bs_r_2,
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iomd_bs_r_4,
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bs_notimpl_bs_r_8,
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/* read multiple */
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bs_notimpl_rm_1,
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iomd_rm_2,
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bs_notimpl_rm_4,
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bs_notimpl_rm_8,
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bs_notimpl_bs_rm_1,
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iomd_bs_rm_2,
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bs_notimpl_bs_rm_4,
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bs_notimpl_bs_rm_8,
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/* read region */
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bs_notimpl_rr_1,
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bs_notimpl_rr_2,
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bs_notimpl_rr_4,
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bs_notimpl_rr_8,
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bs_notimpl_bs_rr_1,
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bs_notimpl_bs_rr_2,
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bs_notimpl_bs_rr_4,
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bs_notimpl_bs_rr_8,
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/* write (single) */
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iomd_w_1,
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iomd_w_2,
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iomd_w_4,
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bs_notimpl_w_8,
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iomd_bs_w_1,
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iomd_bs_w_2,
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iomd_bs_w_4,
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bs_notimpl_bs_w_8,
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/* write multiple */
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bs_notimpl_wm_1,
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iomd_wm_2,
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bs_notimpl_wm_4,
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bs_notimpl_wm_8,
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bs_notimpl_bs_wm_1,
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iomd_bs_wm_2,
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bs_notimpl_bs_wm_4,
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bs_notimpl_bs_wm_8,
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/* write region */
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bs_notimpl_wr_1,
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bs_notimpl_wr_2,
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bs_notimpl_wr_4,
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bs_notimpl_wr_8,
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bs_notimpl_bs_wr_1,
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bs_notimpl_bs_wr_2,
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bs_notimpl_bs_wr_4,
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bs_notimpl_bs_wr_8,
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/* set multiple */
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bs_notimpl_sm_1,
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bs_notimpl_sm_2,
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bs_notimpl_sm_4,
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bs_notimpl_sm_8,
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bs_notimpl_bs_sm_1,
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bs_notimpl_bs_sm_2,
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bs_notimpl_bs_sm_4,
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bs_notimpl_bs_sm_8,
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/* set region */
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||||
bs_notimpl_sr_1,
|
||||
bs_notimpl_sr_2,
|
||||
bs_notimpl_sr_4,
|
||||
bs_notimpl_sr_8,
|
||||
bs_notimpl_bs_sr_1,
|
||||
bs_notimpl_bs_sr_2,
|
||||
bs_notimpl_bs_sr_4,
|
||||
bs_notimpl_bs_sr_8,
|
||||
|
||||
/* copy */
|
||||
bs_notimpl_c_1,
|
||||
bs_notimpl_c_2,
|
||||
bs_notimpl_c_4,
|
||||
bs_notimpl_c_8,
|
||||
bs_notimpl_bs_c_1,
|
||||
bs_notimpl_bs_c_2,
|
||||
bs_notimpl_bs_c_4,
|
||||
bs_notimpl_bs_c_8,
|
||||
};
|
||||
|
||||
/* bus space functions */
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: iomd_io_asm.S,v 1.2 1998/03/26 20:05:13 mark Exp $ */
|
||||
/* $NetBSD: iomd_io_asm.S,v 1.3 1998/06/28 07:27:52 thorpej Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1997 Mark Brinicombe.
|
||||
@ -43,17 +43,17 @@
|
||||
* read single
|
||||
*/
|
||||
|
||||
ENTRY(iomd_r_1)
|
||||
ENTRY(iomd_bs_r_1)
|
||||
ldrb r0, [r1, r2, lsl #2]
|
||||
mov pc, lr
|
||||
|
||||
ENTRY(iomd_r_2)
|
||||
ENTRY(iomd_bs_r_2)
|
||||
ldr r0, [r1, r2, lsl #2]
|
||||
bic r0, r0, #0xff000000
|
||||
bic r0, r0, #0x00ff0000
|
||||
mov pc, lr
|
||||
|
||||
ENTRY(iomd_r_4)
|
||||
ENTRY(iomd_bs_r_4)
|
||||
ldr r0, [r1, r2, lsl #2]
|
||||
mov pc, lr
|
||||
|
||||
@ -61,17 +61,17 @@ ENTRY(iomd_r_4)
|
||||
* write single
|
||||
*/
|
||||
|
||||
ENTRY(iomd_w_1)
|
||||
ENTRY(iomd_bs_w_1)
|
||||
strb r3, [r1, r2, lsl #2]
|
||||
mov pc, lr
|
||||
|
||||
ENTRY(iomd_w_2)
|
||||
ENTRY(iomd_bs_w_2)
|
||||
mov r3, r3, lsl #16
|
||||
orr r3, r3, r3, lsr #16
|
||||
str r3, [r1, r2, lsl #2]
|
||||
mov pc, lr
|
||||
|
||||
ENTRY(iomd_w_4)
|
||||
ENTRY(iomd_bs_w_4)
|
||||
str r3, [r1, r2, lsl #2]
|
||||
mov pc, lr
|
||||
|
||||
@ -80,7 +80,7 @@ ENTRY(iomd_w_4)
|
||||
* read multiple
|
||||
*/
|
||||
|
||||
ENTRY(iomd_rm_2)
|
||||
ENTRY(iomd_bs_rm_2)
|
||||
add r0, r1, r2, lsl #2
|
||||
mov r1, r3
|
||||
ldr r2, [sp, #0]
|
||||
@ -90,7 +90,7 @@ ENTRY(iomd_rm_2)
|
||||
* write multiple
|
||||
*/
|
||||
|
||||
ENTRY(iomd_wm_2)
|
||||
ENTRY(iomd_bs_wm_2)
|
||||
add r0, r1, r2, lsl #2
|
||||
mov r1, r3
|
||||
ldr r2, [sp, #0]
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: isa_io.c,v 1.1 1998/06/08 17:49:44 tv Exp $ */
|
||||
/* $NetBSD: isa_io.c,v 1.2 1998/06/28 07:27:52 thorpej Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright 1997
|
||||
@ -61,70 +61,70 @@ struct bus_space isa_io_bs_tag = {
|
||||
NULL, /* initialized below */
|
||||
|
||||
/* mapping/unmapping */
|
||||
isa_map,
|
||||
isa_unmap,
|
||||
isa_subregion,
|
||||
isa_bs_map,
|
||||
isa_bs_unmap,
|
||||
isa_bs_subregion,
|
||||
|
||||
/* allocation/deallocation */
|
||||
isa_alloc,
|
||||
isa_free,
|
||||
isa_bs_alloc,
|
||||
isa_bs_free,
|
||||
|
||||
/* barrier */
|
||||
isa_barrier,
|
||||
isa_bs_barrier,
|
||||
|
||||
/* read (single) */
|
||||
isa_r_1,
|
||||
isa_r_2,
|
||||
isa_r_4,
|
||||
bs_notimpl_r_8,
|
||||
isa_bs_r_1,
|
||||
isa_bs_r_2,
|
||||
isa_bs_r_4,
|
||||
bs_notimpl_bs_r_8,
|
||||
|
||||
/* read multiple */
|
||||
isa_rm_1,
|
||||
isa_rm_2,
|
||||
isa_rm_4,
|
||||
bs_notimpl_rm_8,
|
||||
isa_bs_rm_1,
|
||||
isa_bs_rm_2,
|
||||
isa_bs_rm_4,
|
||||
bs_notimpl_bs_rm_8,
|
||||
|
||||
/* read region */
|
||||
isa_rr_1,
|
||||
isa_rr_2,
|
||||
isa_rr_4,
|
||||
bs_notimpl_rr_8,
|
||||
isa_bs_rr_1,
|
||||
isa_bs_rr_2,
|
||||
isa_bs_rr_4,
|
||||
bs_notimpl_bs_rr_8,
|
||||
|
||||
/* write (single) */
|
||||
isa_w_1,
|
||||
isa_w_2,
|
||||
isa_w_4,
|
||||
bs_notimpl_w_8,
|
||||
isa_bs_w_1,
|
||||
isa_bs_w_2,
|
||||
isa_bs_w_4,
|
||||
bs_notimpl_bs_w_8,
|
||||
|
||||
/* write multiple */
|
||||
isa_wm_1,
|
||||
isa_wm_2,
|
||||
isa_wm_4,
|
||||
bs_notimpl_wm_8,
|
||||
isa_bs_wm_1,
|
||||
isa_bs_wm_2,
|
||||
isa_bs_wm_4,
|
||||
bs_notimpl_bs_wm_8,
|
||||
|
||||
/* write region */
|
||||
isa_wr_1,
|
||||
isa_wr_2,
|
||||
isa_wr_4,
|
||||
bs_notimpl_wr_8,
|
||||
isa_bs_wr_1,
|
||||
isa_bs_wr_2,
|
||||
isa_bs_wr_4,
|
||||
bs_notimpl_bs_wr_8,
|
||||
|
||||
/* set multiple */
|
||||
bs_notimpl_sm_1,
|
||||
bs_notimpl_sm_2,
|
||||
bs_notimpl_sm_4,
|
||||
bs_notimpl_sm_8,
|
||||
bs_notimpl_bs_sm_1,
|
||||
bs_notimpl_bs_sm_2,
|
||||
bs_notimpl_bs_sm_4,
|
||||
bs_notimpl_bs_sm_8,
|
||||
|
||||
/* set region */
|
||||
bs_notimpl_sr_1,
|
||||
bs_notimpl_sr_2,
|
||||
bs_notimpl_sr_4,
|
||||
bs_notimpl_sr_8,
|
||||
bs_notimpl_bs_sr_1,
|
||||
bs_notimpl_bs_sr_2,
|
||||
bs_notimpl_bs_sr_4,
|
||||
bs_notimpl_bs_sr_8,
|
||||
|
||||
/* copy */
|
||||
bs_notimpl_c_1,
|
||||
bs_notimpl_c_2,
|
||||
bs_notimpl_c_4,
|
||||
bs_notimpl_c_8,
|
||||
bs_notimpl_bs_c_1,
|
||||
bs_notimpl_bs_c_2,
|
||||
bs_notimpl_bs_c_4,
|
||||
bs_notimpl_bs_c_8,
|
||||
};
|
||||
|
||||
/*
|
||||
@ -136,70 +136,70 @@ struct bus_space isa_mem_bs_tag = {
|
||||
NULL, /* initialized below */
|
||||
|
||||
/* mapping/unmapping */
|
||||
isa_map,
|
||||
isa_unmap,
|
||||
isa_subregion,
|
||||
isa_bs_map,
|
||||
isa_bs_unmap,
|
||||
isa_bs_subregion,
|
||||
|
||||
/* allocation/deallocation */
|
||||
isa_alloc,
|
||||
isa_free,
|
||||
isa_bs_alloc,
|
||||
isa_bs_free,
|
||||
|
||||
/* barrier */
|
||||
isa_barrier,
|
||||
isa_bs_barrier,
|
||||
|
||||
/* read (single) */
|
||||
isa_r_1,
|
||||
isa_r_2,
|
||||
isa_r_4,
|
||||
bs_notimpl_r_8,
|
||||
isa_bs_r_1,
|
||||
isa_bs_r_2,
|
||||
isa_bs_r_4,
|
||||
bs_notimpl_bs_r_8,
|
||||
|
||||
/* read multiple */
|
||||
isa_rm_1,
|
||||
isa_rm_2,
|
||||
isa_rm_4,
|
||||
bs_notimpl_rm_8,
|
||||
isa_bs_rm_1,
|
||||
isa_bs_rm_2,
|
||||
isa_bs_rm_4,
|
||||
bs_notimpl_bs_rm_8,
|
||||
|
||||
/* read region */
|
||||
isa_rr_1,
|
||||
isa_rr_2,
|
||||
isa_rr_4,
|
||||
bs_notimpl_rr_8,
|
||||
isa_bs_rr_1,
|
||||
isa_bs_rr_2,
|
||||
isa_bs_rr_4,
|
||||
bs_notimpl_bs_rr_8,
|
||||
|
||||
/* write (single) */
|
||||
isa_w_1,
|
||||
isa_w_2,
|
||||
isa_w_4,
|
||||
bs_notimpl_w_8,
|
||||
isa_bs_w_1,
|
||||
isa_bs_w_2,
|
||||
isa_bs_w_4,
|
||||
bs_notimpl_bs_w_8,
|
||||
|
||||
/* write multiple */
|
||||
isa_wm_1,
|
||||
isa_wm_2,
|
||||
isa_wm_4,
|
||||
bs_notimpl_wm_8,
|
||||
isa_bs_wm_1,
|
||||
isa_bs_wm_2,
|
||||
isa_bs_wm_4,
|
||||
bs_notimpl_bs_wm_8,
|
||||
|
||||
/* write region */
|
||||
isa_wr_1,
|
||||
isa_wr_2,
|
||||
isa_wr_4,
|
||||
bs_notimpl_wr_8,
|
||||
isa_bs_wr_1,
|
||||
isa_bs_wr_2,
|
||||
isa_bs_wr_4,
|
||||
bs_notimpl_bs_wr_8,
|
||||
|
||||
/* set multiple */
|
||||
bs_notimpl_sm_1,
|
||||
bs_notimpl_sm_2,
|
||||
bs_notimpl_sm_4,
|
||||
bs_notimpl_sm_8,
|
||||
bs_notimpl_bs_sm_1,
|
||||
bs_notimpl_bs_sm_2,
|
||||
bs_notimpl_bs_sm_4,
|
||||
bs_notimpl_bs_sm_8,
|
||||
|
||||
/* set region */
|
||||
bs_notimpl_sr_1,
|
||||
bs_notimpl_sr_2,
|
||||
bs_notimpl_sr_4,
|
||||
bs_notimpl_sr_8,
|
||||
bs_notimpl_bs_sr_1,
|
||||
bs_notimpl_bs_sr_2,
|
||||
bs_notimpl_bs_sr_4,
|
||||
bs_notimpl_bs_sr_8,
|
||||
|
||||
/* copy */
|
||||
bs_notimpl_c_1,
|
||||
bs_notimpl_c_2,
|
||||
bs_notimpl_c_4,
|
||||
bs_notimpl_c_8,
|
||||
bs_notimpl_bs_c_1,
|
||||
bs_notimpl_bs_c_2,
|
||||
bs_notimpl_bs_c_4,
|
||||
bs_notimpl_bs_c_8,
|
||||
};
|
||||
|
||||
/* bus space functions */
|
||||
@ -227,7 +227,7 @@ isa_mem_data_vaddr()
|
||||
}
|
||||
|
||||
int
|
||||
isa_map(t, bpa, size, cacheable, bshp)
|
||||
isa_bs_map(t, bpa, size, cacheable, bshp)
|
||||
void *t;
|
||||
bus_addr_t bpa;
|
||||
bus_size_t size;
|
||||
@ -239,7 +239,7 @@ isa_map(t, bpa, size, cacheable, bshp)
|
||||
}
|
||||
|
||||
void
|
||||
isa_unmap(t, bsh, size)
|
||||
isa_bs_unmap(t, bsh, size)
|
||||
void *t;
|
||||
bus_space_handle_t bsh;
|
||||
bus_size_t size;
|
||||
@ -248,7 +248,7 @@ isa_unmap(t, bsh, size)
|
||||
}
|
||||
|
||||
int
|
||||
isa_subregion(t, bsh, offset, size, nbshp)
|
||||
isa_bs_subregion(t, bsh, offset, size, nbshp)
|
||||
void *t;
|
||||
bus_space_handle_t bsh;
|
||||
bus_size_t offset, size;
|
||||
@ -258,7 +258,7 @@ isa_subregion(t, bsh, offset, size, nbshp)
|
||||
}
|
||||
|
||||
int
|
||||
isa_alloc(t, rstart, rend, size, alignment, boundary, cacheable,
|
||||
isa_bs_alloc(t, rstart, rend, size, alignment, boundary, cacheable,
|
||||
bpap, bshp)
|
||||
void *t;
|
||||
bus_addr_t rstart, rend;
|
||||
@ -271,7 +271,7 @@ isa_alloc(t, rstart, rend, size, alignment, boundary, cacheable,
|
||||
}
|
||||
|
||||
void
|
||||
isa_free(t, bsh, size)
|
||||
isa_bs_free(t, bsh, size)
|
||||
void *t;
|
||||
bus_space_handle_t bsh;
|
||||
bus_size_t size;
|
||||
@ -280,7 +280,7 @@ isa_free(t, bsh, size)
|
||||
}
|
||||
|
||||
void
|
||||
isa_barrier(t, bsh, offset, len, flags)
|
||||
isa_bs_barrier(t, bsh, offset, len, flags)
|
||||
void *t;
|
||||
bus_space_handle_t bsh;
|
||||
bus_size_t offset, len;
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: isa_io_asm.S,v 1.1 1998/06/08 17:49:44 tv Exp $ */
|
||||
/* $NetBSD: isa_io_asm.S,v 1.2 1998/06/28 07:27:53 thorpej Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright 1997
|
||||
@ -51,14 +51,14 @@ pc .req r15
|
||||
* read single
|
||||
*/
|
||||
|
||||
ENTRY(isa_r_1)
|
||||
ENTRY(isa_bs_r_1)
|
||||
ldrb r0, [r1, r2]
|
||||
#ifdef GPROF
|
||||
nop ; nop ; nop ; nop ; nop
|
||||
#endif
|
||||
mov pc, lr
|
||||
|
||||
ENTRY(isa_r_2)
|
||||
ENTRY(isa_bs_r_2)
|
||||
add r0, r1, r2
|
||||
/* ldrh r0, [r0] */ .word 0xe1d000b0
|
||||
#ifdef GPROF
|
||||
@ -66,7 +66,7 @@ ENTRY(isa_r_2)
|
||||
#endif
|
||||
mov pc, lr
|
||||
|
||||
ENTRY(isa_r_4)
|
||||
ENTRY(isa_bs_r_4)
|
||||
ldr r0, [r1, r2]
|
||||
#ifdef GPROF
|
||||
nop ; nop ; nop ; nop ; nop
|
||||
@ -78,7 +78,7 @@ ENTRY(isa_r_4)
|
||||
* cloned from assembly generated for:
|
||||
*
|
||||
* void
|
||||
* isa_rm_4(v, h, o, p, s)
|
||||
* isa_bs_rm_4(v, h, o, p, s)
|
||||
* void *v;
|
||||
* bus_space_handle_t h;
|
||||
* bus_size_t o, s;
|
||||
@ -94,7 +94,7 @@ ENTRY(isa_r_4)
|
||||
* }
|
||||
*/
|
||||
|
||||
ENTRY(isa_rm_1)
|
||||
ENTRY(isa_bs_rm_1)
|
||||
mov ip, sp
|
||||
stmfd sp!, {fp, ip, lr, pc}
|
||||
mov r0, r3
|
||||
@ -111,7 +111,7 @@ Lisa_rm_1_loop:
|
||||
bcc Lisa_rm_1_loop
|
||||
ldmea fp, {fp, sp, pc}
|
||||
|
||||
ENTRY(isa_rm_2)
|
||||
ENTRY(isa_bs_rm_2)
|
||||
mov ip, sp
|
||||
stmfd sp!, {fp, ip, lr, pc}
|
||||
mov r0, r3
|
||||
@ -128,7 +128,7 @@ Lisa_rm_2_loop:
|
||||
bcc Lisa_rm_2_loop
|
||||
ldmea fp, {fp, sp, pc}
|
||||
|
||||
ENTRY(isa_rm_4)
|
||||
ENTRY(isa_bs_rm_4)
|
||||
mov ip, sp
|
||||
stmfd sp!, {fp, ip, lr, pc}
|
||||
mov r0, r3
|
||||
@ -151,7 +151,7 @@ Lisa_rm_4_loop:
|
||||
* cloned from assembly generated for:
|
||||
*
|
||||
* void
|
||||
* isa_wr_4(v, h, o, p, s)
|
||||
* isa_bs_wr_4(v, h, o, p, s)
|
||||
* void *v;
|
||||
* bus_space_handle_t h;
|
||||
* bus_size_t o, s;
|
||||
@ -168,7 +168,7 @@ Lisa_rm_4_loop:
|
||||
*
|
||||
*/
|
||||
|
||||
ENTRY(isa_rr_1)
|
||||
ENTRY(isa_bs_rr_1)
|
||||
mov ip, sp
|
||||
stmfd sp!, {fp, ip, lr, pc}
|
||||
mov r0, r3
|
||||
@ -185,7 +185,7 @@ Lisa_rr_1_loop:
|
||||
bcc Lisa_rr_1_loop
|
||||
ldmea fp, {fp, sp, pc}
|
||||
|
||||
ENTRY(isa_rr_2)
|
||||
ENTRY(isa_bs_rr_2)
|
||||
mov ip, sp
|
||||
stmfd sp!, {fp, ip, lr, pc}
|
||||
mov r0, r3
|
||||
@ -202,7 +202,7 @@ Lisa_rr_2_loop:
|
||||
bcc Lisa_rr_2_loop
|
||||
ldmea fp, {fp, sp, pc}
|
||||
|
||||
ENTRY(isa_rr_4)
|
||||
ENTRY(isa_bs_rr_4)
|
||||
mov ip, sp
|
||||
stmfd sp!, {fp, ip, lr, pc}
|
||||
mov r0, r3
|
||||
@ -223,14 +223,14 @@ Lisa_rr_4_loop:
|
||||
* write single
|
||||
*/
|
||||
|
||||
ENTRY(isa_w_1)
|
||||
ENTRY(isa_bs_w_1)
|
||||
strb r3, [r1, r2]
|
||||
#ifdef GPROF
|
||||
nop ; nop ; nop ; nop ; nop
|
||||
#endif
|
||||
mov pc, lr
|
||||
|
||||
ENTRY(isa_w_2)
|
||||
ENTRY(isa_bs_w_2)
|
||||
add r0, r1, r2
|
||||
/* strh r3, [r0] */ .word 0xe1c030b0
|
||||
#ifdef GPROF
|
||||
@ -238,7 +238,7 @@ ENTRY(isa_w_2)
|
||||
#endif
|
||||
mov pc, lr
|
||||
|
||||
ENTRY(isa_w_4)
|
||||
ENTRY(isa_bs_w_4)
|
||||
str r3, [r1, r2]
|
||||
#ifdef GPROF
|
||||
nop ; nop ; nop ; nop ; nop
|
||||
@ -250,7 +250,7 @@ ENTRY(isa_w_4)
|
||||
* cloned from assembly generated for:
|
||||
*
|
||||
* void
|
||||
* isa_wm_4(v, h, o, p, s)
|
||||
* isa_bs_wm_4(v, h, o, p, s)
|
||||
* void *v;
|
||||
* bus_space_handle_t h;
|
||||
* bus_size_t o, s;
|
||||
@ -265,7 +265,7 @@ ENTRY(isa_w_4)
|
||||
* *port = *p++;
|
||||
* }
|
||||
*/
|
||||
ENTRY(isa_wm_1)
|
||||
ENTRY(isa_bs_wm_1)
|
||||
mov ip, sp
|
||||
stmfd sp!, {fp, ip, lr, pc}
|
||||
mov r0, r3
|
||||
@ -282,7 +282,7 @@ Lisa_wm_1_loop:
|
||||
bcc Lisa_wm_1_loop
|
||||
ldmea fp, {fp, sp, pc}
|
||||
|
||||
ENTRY(isa_wm_2)
|
||||
ENTRY(isa_bs_wm_2)
|
||||
mov ip, sp
|
||||
stmfd sp!, {fp, ip, lr, pc}
|
||||
mov r0, r3
|
||||
@ -299,7 +299,7 @@ Lisa_wm_2_loop:
|
||||
bcc Lisa_wm_2_loop
|
||||
ldmea fp, {fp, sp, pc}
|
||||
|
||||
ENTRY(isa_wm_4)
|
||||
ENTRY(isa_bs_wm_4)
|
||||
mov ip, sp
|
||||
stmfd sp!, {fp, ip, lr, pc}
|
||||
mov r0, r3
|
||||
@ -322,7 +322,7 @@ Lisa_wm_4_loop:
|
||||
* cloned from assembly generated for:
|
||||
*
|
||||
* void
|
||||
* isa_wr_4(v, h, o, p, s)
|
||||
* isa_bs_wr_4(v, h, o, p, s)
|
||||
* void *v;
|
||||
* bus_space_handle_t h;
|
||||
* bus_size_t o, s;
|
||||
@ -339,7 +339,7 @@ Lisa_wm_4_loop:
|
||||
*
|
||||
*/
|
||||
|
||||
ENTRY(isa_wr_1)
|
||||
ENTRY(isa_bs_wr_1)
|
||||
mov ip, sp
|
||||
stmfd sp!, {fp, ip, lr, pc}
|
||||
mov r0, r3
|
||||
@ -356,7 +356,7 @@ Lisa_wr_1_loop:
|
||||
bcc Lisa_wr_1_loop
|
||||
ldmea fp, {fp, sp, pc}
|
||||
|
||||
ENTRY(isa_wr_2)
|
||||
ENTRY(isa_bs_wr_2)
|
||||
mov ip, sp
|
||||
stmfd sp!, {fp, ip, lr, pc}
|
||||
mov r0, r3
|
||||
@ -373,7 +373,7 @@ Lisa_wr_2_loop:
|
||||
bcc Lisa_wr_2_loop
|
||||
ldmea fp, {fp, sp, pc}
|
||||
|
||||
ENTRY(isa_wr_4)
|
||||
ENTRY(isa_bs_wr_4)
|
||||
mov ip, sp
|
||||
stmfd sp!, {fp, ip, lr, pc}
|
||||
mov r0, r3
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: mainbus_io.c,v 1.3 1997/10/14 21:25:03 mark Exp $ */
|
||||
/* $NetBSD: mainbus_io.c,v 1.4 1998/06/28 07:27:53 thorpej Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1997 Mark Brinicombe.
|
||||
@ -52,75 +52,75 @@ struct bus_space mainbus_bs_tag = {
|
||||
NULL,
|
||||
|
||||
/* mapping/unmapping */
|
||||
mainbus_map,
|
||||
mainbus_unmap,
|
||||
mainbus_subregion,
|
||||
mainbus_bs_map,
|
||||
mainbus_bs_unmap,
|
||||
mainbus_bs_subregion,
|
||||
|
||||
/* allocation/deallocation */
|
||||
mainbus_alloc,
|
||||
mainbus_free,
|
||||
mainbus_bs_alloc,
|
||||
mainbus_bs_free,
|
||||
|
||||
/* barrier */
|
||||
mainbus_barrier,
|
||||
mainbus_bs_barrier,
|
||||
|
||||
/* read (single) */
|
||||
mainbus_r_1,
|
||||
mainbus_r_2,
|
||||
mainbus_r_4,
|
||||
bs_notimpl_r_8,
|
||||
mainbus_bs_r_1,
|
||||
mainbus_bs_r_2,
|
||||
mainbus_bs_r_4,
|
||||
bs_notimpl_bs_r_8,
|
||||
|
||||
/* read multiple */
|
||||
bs_notimpl_rm_1,
|
||||
mainbus_rm_2,
|
||||
bs_notimpl_rm_4,
|
||||
bs_notimpl_rm_8,
|
||||
bs_notimpl_bs_rm_1,
|
||||
mainbus_bs_rm_2,
|
||||
bs_notimpl_bs_rm_4,
|
||||
bs_notimpl_bs_rm_8,
|
||||
|
||||
/* read region */
|
||||
bs_notimpl_rr_1,
|
||||
bs_notimpl_rr_2,
|
||||
bs_notimpl_rr_4,
|
||||
bs_notimpl_rr_8,
|
||||
bs_notimpl_bs_rr_1,
|
||||
bs_notimpl_bs_rr_2,
|
||||
bs_notimpl_bs_rr_4,
|
||||
bs_notimpl_bs_rr_8,
|
||||
|
||||
/* write (single) */
|
||||
mainbus_w_1,
|
||||
mainbus_w_2,
|
||||
mainbus_w_4,
|
||||
bs_notimpl_w_8,
|
||||
mainbus_bs_w_1,
|
||||
mainbus_bs_w_2,
|
||||
mainbus_bs_w_4,
|
||||
bs_notimpl_bs_w_8,
|
||||
|
||||
/* write multiple */
|
||||
mainbus_wm_1,
|
||||
mainbus_wm_2,
|
||||
bs_notimpl_wm_4,
|
||||
bs_notimpl_wm_8,
|
||||
mainbus_bs_wm_1,
|
||||
mainbus_bs_wm_2,
|
||||
bs_notimpl_bs_wm_4,
|
||||
bs_notimpl_bs_wm_8,
|
||||
|
||||
/* write region */
|
||||
bs_notimpl_wr_1,
|
||||
bs_notimpl_wr_2,
|
||||
bs_notimpl_wr_4,
|
||||
bs_notimpl_wr_8,
|
||||
bs_notimpl_bs_wr_1,
|
||||
bs_notimpl_bs_wr_2,
|
||||
bs_notimpl_bs_wr_4,
|
||||
bs_notimpl_bs_wr_8,
|
||||
|
||||
bs_notimpl_sm_1,
|
||||
bs_notimpl_sm_2,
|
||||
bs_notimpl_sm_4,
|
||||
bs_notimpl_sm_8,
|
||||
bs_notimpl_bs_sm_1,
|
||||
bs_notimpl_bs_sm_2,
|
||||
bs_notimpl_bs_sm_4,
|
||||
bs_notimpl_bs_sm_8,
|
||||
|
||||
/* set region */
|
||||
bs_notimpl_sr_1,
|
||||
bs_notimpl_sr_2,
|
||||
bs_notimpl_sr_4,
|
||||
bs_notimpl_sr_8,
|
||||
bs_notimpl_bs_sr_1,
|
||||
bs_notimpl_bs_sr_2,
|
||||
bs_notimpl_bs_sr_4,
|
||||
bs_notimpl_bs_sr_8,
|
||||
|
||||
/* copy */
|
||||
bs_notimpl_c_1,
|
||||
bs_notimpl_c_2,
|
||||
bs_notimpl_c_4,
|
||||
bs_notimpl_c_8,
|
||||
bs_notimpl_bs_c_1,
|
||||
bs_notimpl_bs_c_2,
|
||||
bs_notimpl_bs_c_4,
|
||||
bs_notimpl_bs_c_8,
|
||||
};
|
||||
|
||||
/* bus space functions */
|
||||
|
||||
int
|
||||
mainbus_map(t, bpa, size, cacheable, bshp)
|
||||
mainbus_bs_map(t, bpa, size, cacheable, bshp)
|
||||
void *t;
|
||||
bus_addr_t bpa;
|
||||
bus_size_t size;
|
||||
@ -137,7 +137,7 @@ mainbus_map(t, bpa, size, cacheable, bshp)
|
||||
}
|
||||
|
||||
int
|
||||
mainbus_alloc(t, rstart, rend, size, alignment, boundary, cacheable,
|
||||
mainbus_bs_alloc(t, rstart, rend, size, alignment, boundary, cacheable,
|
||||
bpap, bshp)
|
||||
void *t;
|
||||
bus_addr_t rstart, rend;
|
||||
@ -146,12 +146,12 @@ mainbus_alloc(t, rstart, rend, size, alignment, boundary, cacheable,
|
||||
bus_addr_t *bpap;
|
||||
bus_space_handle_t *bshp;
|
||||
{
|
||||
panic("mainbus_alloc(): Help!\n");
|
||||
panic("mainbus_bs_alloc(): Help!\n");
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
mainbus_unmap(t, bsh, size)
|
||||
mainbus_bs_unmap(t, bsh, size)
|
||||
void *t;
|
||||
bus_space_handle_t bsh;
|
||||
bus_size_t size;
|
||||
@ -162,19 +162,19 @@ mainbus_unmap(t, bsh, size)
|
||||
}
|
||||
|
||||
void
|
||||
mainbus_free(t, bsh, size)
|
||||
mainbus_bs_free(t, bsh, size)
|
||||
void *t;
|
||||
bus_space_handle_t bsh;
|
||||
bus_size_t size;
|
||||
{
|
||||
|
||||
panic("mainbus_free(): Help!\n");
|
||||
/* mainbus_unmap() does all that we need to do. */
|
||||
/* mainbus_unmap(t, bsh, size);*/
|
||||
panic("mainbus_bs_free(): Help!\n");
|
||||
/* mainbus_bs_unmap() does all that we need to do. */
|
||||
/* mainbus_bs_unmap(t, bsh, size);*/
|
||||
}
|
||||
|
||||
int
|
||||
mainbus_subregion(t, bsh, offset, size, nbshp)
|
||||
mainbus_bs_subregion(t, bsh, offset, size, nbshp)
|
||||
void *t;
|
||||
bus_space_handle_t bsh;
|
||||
bus_size_t offset, size;
|
||||
@ -186,7 +186,7 @@ mainbus_subregion(t, bsh, offset, size, nbshp)
|
||||
}
|
||||
|
||||
void
|
||||
mainbus_barrier(t, bsh, offset, len, flags)
|
||||
mainbus_bs_barrier(t, bsh, offset, len, flags)
|
||||
void *t;
|
||||
bus_space_handle_t bsh;
|
||||
bus_size_t offset, len;
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: mainbus_io_asm.S,v 1.4 1998/04/01 23:14:21 mark Exp $ */
|
||||
/* $NetBSD: mainbus_io_asm.S,v 1.5 1998/06/28 07:27:53 thorpej Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1997 Mark Brinicombe.
|
||||
@ -43,17 +43,17 @@
|
||||
* read single
|
||||
*/
|
||||
|
||||
ENTRY(mainbus_r_1)
|
||||
ENTRY(mainbus_bs_r_1)
|
||||
ldrb r0, [r1, r2, lsl #2]
|
||||
mov pc, lr
|
||||
|
||||
ENTRY(mainbus_r_2)
|
||||
ENTRY(mainbus_bs_r_2)
|
||||
ldr r0, [r1, r2, lsl #2]
|
||||
bic r0, r0, #0xff000000
|
||||
bic r0, r0, #0x00ff0000
|
||||
mov pc, lr
|
||||
|
||||
ENTRY(mainbus_r_4)
|
||||
ENTRY(mainbus_bs_r_4)
|
||||
ldr r0, [r1, r2, lsl #2]
|
||||
mov pc, lr
|
||||
|
||||
@ -61,17 +61,17 @@ ENTRY(mainbus_r_4)
|
||||
* write single
|
||||
*/
|
||||
|
||||
ENTRY(mainbus_w_1)
|
||||
ENTRY(mainbus_bs_w_1)
|
||||
strb r3, [r1, r2, lsl #2]
|
||||
mov pc, lr
|
||||
|
||||
ENTRY(mainbus_w_2)
|
||||
ENTRY(mainbus_bs_w_2)
|
||||
mov r3, r3, lsl #16
|
||||
orr r3, r3, r3, lsr #16
|
||||
str r3, [r1, r2, lsl #2]
|
||||
mov pc, lr
|
||||
|
||||
ENTRY(mainbus_w_4)
|
||||
ENTRY(mainbus_bs_w_4)
|
||||
str r3, [r1, r2, lsl #2]
|
||||
mov pc, lr
|
||||
|
||||
@ -79,7 +79,7 @@ ENTRY(mainbus_w_4)
|
||||
* read multiple
|
||||
*/
|
||||
|
||||
ENTRY(mainbus_rm_2)
|
||||
ENTRY(mainbus_bs_rm_2)
|
||||
add r0, r1, r2, lsl #2
|
||||
mov r1, r3
|
||||
ldr r2, [sp, #0]
|
||||
@ -89,7 +89,7 @@ ENTRY(mainbus_rm_2)
|
||||
* write multiple
|
||||
*/
|
||||
|
||||
ENTRY(mainbus_wm_1)
|
||||
ENTRY(mainbus_bs_wm_1)
|
||||
add r0, r1, r2, lsl #2
|
||||
ldr r2, [sp, #0]
|
||||
|
||||
@ -105,7 +105,7 @@ mainbus_wm_1_loop:
|
||||
|
||||
mov pc, lr
|
||||
|
||||
ENTRY(mainbus_wm_2)
|
||||
ENTRY(mainbus_bs_wm_2)
|
||||
add r0, r1, r2, lsl #2
|
||||
mov r1, r3
|
||||
ldr r2, [sp, #0]
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: icside_io.c,v 1.3 1997/10/14 22:59:11 mark Exp $ */
|
||||
/* $NetBSD: icside_io.c,v 1.4 1998/06/28 07:27:53 thorpej Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1997 Mark Brinicombe.
|
||||
@ -54,76 +54,76 @@ struct bus_space icside_bs_tag = {
|
||||
NULL,
|
||||
|
||||
/* mapping/unmapping */
|
||||
icside_map,
|
||||
icside_unmap,
|
||||
icside_subregion,
|
||||
icside_bs_map,
|
||||
icside_bs_unmap,
|
||||
icside_bs_subregion,
|
||||
|
||||
/* allocation/deallocation */
|
||||
icside_alloc,
|
||||
icside_free,
|
||||
icside_bs_alloc,
|
||||
icside_bs_free,
|
||||
|
||||
/* barrier */
|
||||
icside_barrier,
|
||||
icside_bs_barrier,
|
||||
|
||||
/* read (single) */
|
||||
icside_r_1,
|
||||
icside_r_2,
|
||||
icside_r_4,
|
||||
bs_notimpl_r_8,
|
||||
icside_bs_r_1,
|
||||
icside_bs_r_2,
|
||||
icside_bs_r_4,
|
||||
bs_notimpl_bs_r_8,
|
||||
|
||||
/* read multiple */
|
||||
bs_notimpl_rm_1,
|
||||
icside_rm_2,
|
||||
bs_notimpl_rm_4,
|
||||
bs_notimpl_rm_8,
|
||||
bs_notimpl_bs_rm_1,
|
||||
icside_bs_rm_2,
|
||||
bs_notimpl_bs_rm_4,
|
||||
bs_notimpl_bs_rm_8,
|
||||
|
||||
/* read region */
|
||||
bs_notimpl_rr_1,
|
||||
bs_notimpl_rr_2,
|
||||
bs_notimpl_rr_4,
|
||||
bs_notimpl_rr_8,
|
||||
bs_notimpl_bs_rr_1,
|
||||
bs_notimpl_bs_rr_2,
|
||||
bs_notimpl_bs_rr_4,
|
||||
bs_notimpl_bs_rr_8,
|
||||
|
||||
/* write (single) */
|
||||
icside_w_1,
|
||||
icside_w_2,
|
||||
icside_w_4,
|
||||
bs_notimpl_w_8,
|
||||
icside_bs_w_1,
|
||||
icside_bs_w_2,
|
||||
icside_bs_w_4,
|
||||
bs_notimpl_bs_w_8,
|
||||
|
||||
/* write multiple */
|
||||
bs_notimpl_wm_1,
|
||||
icside_wm_2,
|
||||
bs_notimpl_wm_4,
|
||||
bs_notimpl_wm_8,
|
||||
bs_notimpl_bs_wm_1,
|
||||
icside_bs_wm_2,
|
||||
bs_notimpl_bs_wm_4,
|
||||
bs_notimpl_bs_wm_8,
|
||||
|
||||
/* write region */
|
||||
bs_notimpl_wr_1,
|
||||
bs_notimpl_wr_2,
|
||||
bs_notimpl_wr_4,
|
||||
bs_notimpl_wr_8,
|
||||
bs_notimpl_bs_wr_1,
|
||||
bs_notimpl_bs_wr_2,
|
||||
bs_notimpl_bs_wr_4,
|
||||
bs_notimpl_bs_wr_8,
|
||||
|
||||
/* set multiple */
|
||||
bs_notimpl_sm_1,
|
||||
bs_notimpl_sm_2,
|
||||
bs_notimpl_sm_4,
|
||||
bs_notimpl_sm_8,
|
||||
bs_notimpl_bs_sm_1,
|
||||
bs_notimpl_bs_sm_2,
|
||||
bs_notimpl_bs_sm_4,
|
||||
bs_notimpl_bs_sm_8,
|
||||
|
||||
/* set region */
|
||||
bs_notimpl_sr_1,
|
||||
bs_notimpl_sr_2,
|
||||
bs_notimpl_sr_4,
|
||||
bs_notimpl_sr_8,
|
||||
bs_notimpl_bs_sr_1,
|
||||
bs_notimpl_bs_sr_2,
|
||||
bs_notimpl_bs_sr_4,
|
||||
bs_notimpl_bs_sr_8,
|
||||
|
||||
/* copy */
|
||||
bs_notimpl_c_1,
|
||||
bs_notimpl_c_2,
|
||||
bs_notimpl_c_4,
|
||||
bs_notimpl_c_8,
|
||||
bs_notimpl_bs_c_1,
|
||||
bs_notimpl_bs_c_2,
|
||||
bs_notimpl_bs_c_4,
|
||||
bs_notimpl_bs_c_8,
|
||||
};
|
||||
|
||||
/* bus space functions */
|
||||
|
||||
int
|
||||
icside_map(t, bpa, size, cacheable, bshp)
|
||||
icside_bs_map(t, bpa, size, cacheable, bshp)
|
||||
void *t;
|
||||
bus_addr_t bpa;
|
||||
bus_size_t size;
|
||||
@ -140,7 +140,7 @@ icside_map(t, bpa, size, cacheable, bshp)
|
||||
}
|
||||
|
||||
int
|
||||
icside_alloc(t, rstart, rend, size, alignment, boundary, cacheable,
|
||||
icside_bs_alloc(t, rstart, rend, size, alignment, boundary, cacheable,
|
||||
bpap, bshp)
|
||||
void *t;
|
||||
bus_addr_t rstart, rend;
|
||||
@ -149,12 +149,12 @@ icside_alloc(t, rstart, rend, size, alignment, boundary, cacheable,
|
||||
bus_addr_t *bpap;
|
||||
bus_space_handle_t *bshp;
|
||||
{
|
||||
panic("icside_alloc(): Help!\n");
|
||||
panic("icside_bs_alloc(): Help!\n");
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
icside_unmap(t, bsh, size)
|
||||
icside_bs_unmap(t, bsh, size)
|
||||
void *t;
|
||||
bus_space_handle_t bsh;
|
||||
bus_size_t size;
|
||||
@ -165,19 +165,19 @@ icside_unmap(t, bsh, size)
|
||||
}
|
||||
|
||||
void
|
||||
icside_free(t, bsh, size)
|
||||
icside_bs_free(t, bsh, size)
|
||||
void *t;
|
||||
bus_space_handle_t bsh;
|
||||
bus_size_t size;
|
||||
{
|
||||
|
||||
panic("icside_free(): Help!\n");
|
||||
/* icside_unmap() does all that we need to do. */
|
||||
/* icside_unmap(t, bsh, size);*/
|
||||
panic("icside_bs_free(): Help!\n");
|
||||
/* icside_bs_unmap() does all that we need to do. */
|
||||
/* icside_bs_unmap(t, bsh, size);*/
|
||||
}
|
||||
|
||||
int
|
||||
icside_subregion(t, bsh, offset, size, nbshp)
|
||||
icside_bs_subregion(t, bsh, offset, size, nbshp)
|
||||
void *t;
|
||||
bus_space_handle_t bsh;
|
||||
bus_size_t offset, size;
|
||||
@ -189,7 +189,7 @@ icside_subregion(t, bsh, offset, size, nbshp)
|
||||
}
|
||||
|
||||
void
|
||||
icside_barrier(t, bsh, offset, len, flags)
|
||||
icside_bs_barrier(t, bsh, offset, len, flags)
|
||||
void *t;
|
||||
bus_space_handle_t bsh;
|
||||
bus_size_t offset, len;
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: icside_io_asm.S,v 1.4 1997/10/17 06:46:27 mark Exp $ */
|
||||
/* $NetBSD: icside_io_asm.S,v 1.5 1998/06/28 07:27:54 thorpej Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1997 Mark Brinicombe.
|
||||
@ -42,17 +42,17 @@
|
||||
* read single
|
||||
*/
|
||||
|
||||
ENTRY(icside_r_1)
|
||||
ENTRY(icside_bs_r_1)
|
||||
ldrb r0, [r1, r2, lsl #6]
|
||||
mov pc, lr
|
||||
|
||||
ENTRY(icside_r_2)
|
||||
ENTRY(icside_bs_r_2)
|
||||
ldr r0, [r1, r2, lsl #6]
|
||||
bic r0, r0, #0xff000000
|
||||
bic r0, r0, #0x00ff0000
|
||||
mov pc, lr
|
||||
|
||||
ENTRY(icside_r_4)
|
||||
ENTRY(icside_bs_r_4)
|
||||
ldr r0, [r1, r2, lsl #6]
|
||||
mov pc, lr
|
||||
|
||||
@ -60,17 +60,17 @@ ENTRY(icside_r_4)
|
||||
* write single
|
||||
*/
|
||||
|
||||
ENTRY(icside_w_1)
|
||||
ENTRY(icside_bs_w_1)
|
||||
strb r3, [r1, r2, lsl #6]
|
||||
mov pc, lr
|
||||
|
||||
ENTRY(icside_w_2)
|
||||
ENTRY(icside_bs_w_2)
|
||||
mov r3, r3, lsl #16
|
||||
orr r3, r3, r3, lsr #16
|
||||
str r3, [r1, r2, lsl #6]
|
||||
mov pc, lr
|
||||
|
||||
ENTRY(icside_w_4)
|
||||
ENTRY(icside_bs_w_4)
|
||||
str r3, [r1, r2, lsl #6]
|
||||
mov pc, lr
|
||||
|
||||
@ -78,7 +78,7 @@ ENTRY(icside_w_4)
|
||||
* read multiple
|
||||
*/
|
||||
|
||||
ENTRY(icside_rm_2)
|
||||
ENTRY(icside_bs_rm_2)
|
||||
add r0, r1, r2, lsl #6
|
||||
mov r1, r3
|
||||
ldr r2, [sp, #0]
|
||||
@ -88,7 +88,7 @@ ENTRY(icside_rm_2)
|
||||
* write multiple
|
||||
*/
|
||||
|
||||
ENTRY(icside_wm_2)
|
||||
ENTRY(icside_bs_wm_2)
|
||||
add r0, r1, r2, lsl #6
|
||||
mov r1, r3
|
||||
ldr r2, [sp, #0]
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: podulebus_io.c,v 1.6 1998/03/23 17:07:38 mark Exp $ */
|
||||
/* $NetBSD: podulebus_io.c,v 1.7 1998/06/28 07:27:54 thorpej Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1997 Mark Brinicombe.
|
||||
@ -52,76 +52,76 @@ struct bus_space podulebus_bs_tag = {
|
||||
(void *) 2, /* Shift to apply to registers */
|
||||
|
||||
/* mapping/unmapping */
|
||||
podulebus_map,
|
||||
podulebus_unmap,
|
||||
podulebus_subregion,
|
||||
podulebus_bs_map,
|
||||
podulebus_bs_unmap,
|
||||
podulebus_bs_subregion,
|
||||
|
||||
/* allocation/deallocation */
|
||||
podulebus_alloc,
|
||||
podulebus_free,
|
||||
podulebus_bs_alloc,
|
||||
podulebus_bs_free,
|
||||
|
||||
/* barrier */
|
||||
podulebus_barrier,
|
||||
podulebus_bs_barrier,
|
||||
|
||||
/* read (single) */
|
||||
podulebus_r_1,
|
||||
podulebus_r_2,
|
||||
podulebus_r_4,
|
||||
bs_notimpl_r_8,
|
||||
podulebus_bs_r_1,
|
||||
podulebus_bs_r_2,
|
||||
podulebus_bs_r_4,
|
||||
bs_notimpl_bs_r_8,
|
||||
|
||||
/* read multiple */
|
||||
podulebus_rm_1,
|
||||
podulebus_rm_2,
|
||||
bs_notimpl_rm_4,
|
||||
bs_notimpl_rm_8,
|
||||
podulebus_bs_rm_1,
|
||||
podulebus_bs_rm_2,
|
||||
bs_notimpl_bs_rm_4,
|
||||
bs_notimpl_bs_rm_8,
|
||||
|
||||
/* read region */
|
||||
bs_notimpl_rr_1,
|
||||
bs_notimpl_rr_2,
|
||||
bs_notimpl_rr_4,
|
||||
bs_notimpl_rr_8,
|
||||
bs_notimpl_bs_rr_1,
|
||||
bs_notimpl_bs_rr_2,
|
||||
bs_notimpl_bs_rr_4,
|
||||
bs_notimpl_bs_rr_8,
|
||||
|
||||
/* write (single) */
|
||||
podulebus_w_1,
|
||||
podulebus_w_2,
|
||||
podulebus_w_4,
|
||||
bs_notimpl_w_8,
|
||||
podulebus_bs_w_1,
|
||||
podulebus_bs_w_2,
|
||||
podulebus_bs_w_4,
|
||||
bs_notimpl_bs_w_8,
|
||||
|
||||
/* write multiple */
|
||||
podulebus_wm_1,
|
||||
podulebus_wm_2,
|
||||
bs_notimpl_wm_4,
|
||||
bs_notimpl_wm_8,
|
||||
podulebus_bs_wm_1,
|
||||
podulebus_bs_wm_2,
|
||||
bs_notimpl_bs_wm_4,
|
||||
bs_notimpl_bs_wm_8,
|
||||
|
||||
/* write region */
|
||||
bs_notimpl_wr_1,
|
||||
bs_notimpl_wr_2,
|
||||
bs_notimpl_wr_4,
|
||||
bs_notimpl_wr_8,
|
||||
bs_notimpl_bs_wr_1,
|
||||
bs_notimpl_bs_wr_2,
|
||||
bs_notimpl_bs_wr_4,
|
||||
bs_notimpl_bs_wr_8,
|
||||
|
||||
/* set multiple */
|
||||
bs_notimpl_sm_1,
|
||||
bs_notimpl_sm_2,
|
||||
bs_notimpl_sm_4,
|
||||
bs_notimpl_sm_8,
|
||||
bs_notimpl_bs_sm_1,
|
||||
bs_notimpl_bs_sm_2,
|
||||
bs_notimpl_bs_sm_4,
|
||||
bs_notimpl_bs_sm_8,
|
||||
|
||||
/* set region */
|
||||
bs_notimpl_sr_1,
|
||||
bs_notimpl_sr_2,
|
||||
bs_notimpl_sr_4,
|
||||
bs_notimpl_sr_8,
|
||||
bs_notimpl_bs_sr_1,
|
||||
bs_notimpl_bs_sr_2,
|
||||
bs_notimpl_bs_sr_4,
|
||||
bs_notimpl_bs_sr_8,
|
||||
|
||||
/* copy */
|
||||
bs_notimpl_c_1,
|
||||
bs_notimpl_c_2,
|
||||
bs_notimpl_c_4,
|
||||
bs_notimpl_c_8,
|
||||
bs_notimpl_bs_c_1,
|
||||
bs_notimpl_bs_c_2,
|
||||
bs_notimpl_bs_c_4,
|
||||
bs_notimpl_bs_c_8,
|
||||
};
|
||||
|
||||
/* bus space functions */
|
||||
|
||||
int
|
||||
podulebus_map(t, bpa, size, cacheable, bshp)
|
||||
podulebus_bs_map(t, bpa, size, cacheable, bshp)
|
||||
void *t;
|
||||
bus_addr_t bpa;
|
||||
bus_size_t size;
|
||||
@ -138,7 +138,7 @@ podulebus_map(t, bpa, size, cacheable, bshp)
|
||||
}
|
||||
|
||||
int
|
||||
podulebus_alloc(t, rstart, rend, size, alignment, boundary, cacheable,
|
||||
podulebus_bs_alloc(t, rstart, rend, size, alignment, boundary, cacheable,
|
||||
bpap, bshp)
|
||||
void *t;
|
||||
bus_addr_t rstart, rend;
|
||||
@ -147,12 +147,12 @@ podulebus_alloc(t, rstart, rend, size, alignment, boundary, cacheable,
|
||||
bus_addr_t *bpap;
|
||||
bus_space_handle_t *bshp;
|
||||
{
|
||||
panic("podulebus_alloc(): Help!\n");
|
||||
panic("podulebus_bs_alloc(): Help!\n");
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
podulebus_unmap(t, bsh, size)
|
||||
podulebus_bs_unmap(t, bsh, size)
|
||||
void *t;
|
||||
bus_space_handle_t bsh;
|
||||
bus_size_t size;
|
||||
@ -163,19 +163,19 @@ podulebus_unmap(t, bsh, size)
|
||||
}
|
||||
|
||||
void
|
||||
podulebus_free(t, bsh, size)
|
||||
podulebus_bs_free(t, bsh, size)
|
||||
void *t;
|
||||
bus_space_handle_t bsh;
|
||||
bus_size_t size;
|
||||
{
|
||||
|
||||
panic("podulebus_free(): Help!\n");
|
||||
/* podulebus_unmap() does all that we need to do. */
|
||||
/* podulebus_unmap(t, bsh, size);*/
|
||||
panic("podulebus_bs_free(): Help!\n");
|
||||
/* podulebus_bs_unmap() does all that we need to do. */
|
||||
/* podulebus_bs_unmap(t, bsh, size);*/
|
||||
}
|
||||
|
||||
int
|
||||
podulebus_subregion(t, bsh, offset, size, nbshp)
|
||||
podulebus_bs_subregion(t, bsh, offset, size, nbshp)
|
||||
void *t;
|
||||
bus_space_handle_t bsh;
|
||||
bus_size_t offset, size;
|
||||
@ -187,7 +187,7 @@ podulebus_subregion(t, bsh, offset, size, nbshp)
|
||||
}
|
||||
|
||||
void
|
||||
podulebus_barrier(t, bsh, offset, len, flags)
|
||||
podulebus_bs_barrier(t, bsh, offset, len, flags)
|
||||
void *t;
|
||||
bus_space_handle_t bsh;
|
||||
bus_size_t offset, len;
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: podulebus_io_asm.S,v 1.7 1998/03/23 17:07:39 mark Exp $ */
|
||||
/* $NetBSD: podulebus_io_asm.S,v 1.8 1998/06/28 07:27:54 thorpej Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1997 Mark Brinicombe.
|
||||
@ -42,19 +42,19 @@
|
||||
* read single
|
||||
*/
|
||||
|
||||
ENTRY(podulebus_r_1)
|
||||
ENTRY(podulebus_bs_r_1)
|
||||
mov r2, r2, lsl r0
|
||||
ldrb r0, [r1, r2]
|
||||
mov pc, lr
|
||||
|
||||
ENTRY(podulebus_r_2)
|
||||
ENTRY(podulebus_bs_r_2)
|
||||
mov r2, r2, lsl r0
|
||||
ldr r0, [r1, r2]
|
||||
bic r0, r0, #0xff000000
|
||||
bic r0, r0, #0x00ff0000
|
||||
mov pc, lr
|
||||
|
||||
ENTRY(podulebus_r_4)
|
||||
ENTRY(podulebus_bs_r_4)
|
||||
mov r2, r2, lsl r0
|
||||
ldr r0, [r1, r2]
|
||||
mov pc, lr
|
||||
@ -63,19 +63,19 @@ ENTRY(podulebus_r_4)
|
||||
* write single
|
||||
*/
|
||||
|
||||
ENTRY(podulebus_w_1)
|
||||
ENTRY(podulebus_bs_w_1)
|
||||
mov r2, r2, lsl r0
|
||||
strb r3, [r1, r2]
|
||||
mov pc, lr
|
||||
|
||||
ENTRY(podulebus_w_2)
|
||||
ENTRY(podulebus_bs_w_2)
|
||||
mov r3, r3, lsl #16
|
||||
orr r3, r3, r3, lsr #16
|
||||
mov r2, r2, lsl r0
|
||||
str r3, [r1, r2]
|
||||
mov pc, lr
|
||||
|
||||
ENTRY(podulebus_w_4)
|
||||
ENTRY(podulebus_bs_w_4)
|
||||
mov r2, r2, lsl r0
|
||||
str r3, [r1, r2]
|
||||
mov pc, lr
|
||||
@ -84,7 +84,7 @@ ENTRY(podulebus_w_4)
|
||||
* read multiple
|
||||
*/
|
||||
|
||||
ENTRY(podulebus_rm_1)
|
||||
ENTRY(podulebus_bs_rm_1)
|
||||
add r0, r1, r2, lsl r0
|
||||
ldr r2, [sp, #0]
|
||||
|
||||
@ -100,7 +100,7 @@ podulebus_rm_1_loop:
|
||||
|
||||
mov pc, lr
|
||||
|
||||
ENTRY(podulebus_rm_2)
|
||||
ENTRY(podulebus_bs_rm_2)
|
||||
add r0, r1, r2, lsl r0
|
||||
mov r1, r3
|
||||
ldr r2, [sp, #0]
|
||||
@ -110,7 +110,7 @@ ENTRY(podulebus_rm_2)
|
||||
* write multiple
|
||||
*/
|
||||
|
||||
ENTRY(podulebus_wm_1)
|
||||
ENTRY(podulebus_bs_wm_1)
|
||||
add r0, r1, r2, lsl r0
|
||||
ldr r2, [sp, #0]
|
||||
|
||||
@ -126,7 +126,7 @@ podulebus_wm_1_loop:
|
||||
|
||||
mov pc, lr
|
||||
|
||||
ENTRY(podulebus_wm_2)
|
||||
ENTRY(podulebus_bs_wm_2)
|
||||
add r0, r1, r2, lsl r0
|
||||
mov r1, r3
|
||||
ldr r2, [sp, #0]
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: rapide.c,v 1.7 1998/01/18 04:09:52 mark Exp $ */
|
||||
/* $NetBSD: rapide.c,v 1.8 1998/06/28 07:27:55 thorpej Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1997 Mark Brinicombe
|
||||
@ -225,8 +225,8 @@ rapide_attach(parent, self, aux)
|
||||
*/
|
||||
|
||||
rapide_bs_tag = *pa->pa_iot;
|
||||
rapide_bs_tag.bs_rm_4 = rapide_rm_4;
|
||||
rapide_bs_tag.bs_wm_4 = rapide_wm_4;
|
||||
rapide_bs_tag.bs_rm_4 = rapide_bs_rm_4;
|
||||
rapide_bs_tag.bs_wm_4 = rapide_bs_wm_4;
|
||||
sc->sc_iot = iot = &rapide_bs_tag;
|
||||
|
||||
if (bus_space_map(iot, pa->pa_podule->easi_base +
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: rapide_io_asm.S,v 1.4 1997/10/17 06:46:32 mark Exp $ */
|
||||
/* $NetBSD: rapide_io_asm.S,v 1.5 1998/06/28 07:27:55 thorpej Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1997 Mark Brinicombe.
|
||||
@ -43,7 +43,7 @@
|
||||
|
||||
.text
|
||||
|
||||
ENTRY(rapide_rm_4)
|
||||
ENTRY(rapide_bs_rm_4)
|
||||
add r0, r1, r2
|
||||
mov r1, r3
|
||||
|
||||
@ -110,7 +110,7 @@ rapide_rm_4_m128_loop:
|
||||
|
||||
ldmfd sp!, {r4-r12, pc}
|
||||
|
||||
ENTRY(rapide_wm_4)
|
||||
ENTRY(rapide_bs_wm_4)
|
||||
add r0, r1, r2
|
||||
mov r1, r3
|
||||
ldr r2, [sp, #0]
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: simide.c,v 1.5 1998/01/18 04:09:53 mark Exp $ */
|
||||
/* $NetBSD: simide.c,v 1.6 1998/06/28 07:27:57 thorpej Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1997 Mark Brinicombe
|
||||
@ -198,8 +198,8 @@ simide_attach(parent, self, aux)
|
||||
|
||||
sc->sc_tag = *pa->pa_iot;
|
||||
sc->sc_tag.bs_cookie = (void *) 7;
|
||||
sc->sc_tag.bs_rm_2 = simide_rm_2;
|
||||
sc->sc_tag.bs_wm_2 = simide_wm_2;
|
||||
sc->sc_tag.bs_rm_2 = simide_bs_rm_2;
|
||||
sc->sc_tag.bs_wm_2 = simide_bs_wm_2;
|
||||
sc->sc_iot = &sc->sc_tag;
|
||||
|
||||
/* Obtain bus space handles for all the control registers */
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: simide_io_asm.S,v 1.2 1997/10/17 06:46:34 mark Exp $ */
|
||||
/* $NetBSD: simide_io_asm.S,v 1.3 1998/06/28 07:27:58 thorpej Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1997 Mark Brinicombe.
|
||||
@ -42,7 +42,7 @@
|
||||
* Fast read multiple
|
||||
*/
|
||||
|
||||
ENTRY(simide_rm_2)
|
||||
ENTRY(simide_bs_rm_2)
|
||||
add r0, r1, r2, lsl r0
|
||||
mov r1, r3
|
||||
ldr r2, [sp, #0]
|
||||
@ -52,7 +52,7 @@ ENTRY(simide_rm_2)
|
||||
* Fast write multiple
|
||||
*/
|
||||
|
||||
ENTRY(simide_wm_2)
|
||||
ENTRY(simide_bs_wm_2)
|
||||
add r0, r1, r2, lsl r0
|
||||
mov r1, r3
|
||||
ldr r2, [sp, #0]
|
||||
|
||||
Loading…
Reference in New Issue
Block a user