Add support of Silicon Image 0680 Ultra ATA/133 ATA Controller.
It's ugly that all register values are written in numeric, but I can't find any definition of the registers to be written in literal.
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onoe
parent
2354f208d4
commit
46243dd61d
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@ -1,4 +1,4 @@
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/* $NetBSD: pciide.c,v 1.160 2002/07/22 20:56:57 bouyer Exp $ */
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/* $NetBSD: pciide.c,v 1.161 2002/07/26 10:23:30 onoe Exp $ */
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/*
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@ -76,7 +76,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: pciide.c,v 1.160 2002/07/22 20:56:57 bouyer Exp $");
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__KERNEL_RCSID(0, "$NetBSD: pciide.c,v 1.161 2002/07/26 10:23:30 onoe Exp $");
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#ifndef WDCDEBUG
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#define WDCDEBUG
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@ -177,6 +177,10 @@ void cmd_channel_map __P((struct pci_attach_args *,
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struct pciide_softc *, int));
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int cmd_pci_intr __P((void *));
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void cmd646_9_irqack __P((struct channel_softc *));
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void cmd680_chip_map __P((struct pciide_softc*, struct pci_attach_args*));
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void cmd680_setup_channel __P((struct channel_softc*));
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void cmd680_channel_map __P((struct pci_attach_args *,
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struct pciide_softc *, int));
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void cy693_chip_map __P((struct pciide_softc*, struct pci_attach_args*));
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void cy693_setup_channel __P((struct channel_softc*));
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@ -358,6 +362,11 @@ const struct pciide_product_desc pciide_cmd_products[] = {
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"CMD Technology PCI0649",
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cmd0643_9_chip_map,
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},
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{ PCI_PRODUCT_CMDTECH_680,
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IDE_PCI_CLASS_OVERRIDE,
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"Silicon Image 0680",
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cmd680_chip_map,
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},
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{ 0,
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0,
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NULL,
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@ -2689,6 +2698,182 @@ cmd646_9_irqack(chp)
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pciide_irqack(chp);
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}
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void
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cmd680_chip_map(sc, pa)
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struct pciide_softc *sc;
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struct pci_attach_args *pa;
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{
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struct pciide_channel *cp;
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int channel;
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if (pciide_chipen(sc, pa) == 0)
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return;
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printf("%s: bus-master DMA support present",
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sc->sc_wdcdev.sc_dev.dv_xname);
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pciide_mapreg_dma(sc, pa);
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printf("\n");
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sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 |
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WDC_CAPABILITY_MODE;
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if (sc->sc_dma_ok) {
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sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK;
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sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA;
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sc->sc_wdcdev.UDMA_cap = 6;
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sc->sc_wdcdev.irqack = pciide_irqack;
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}
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sc->sc_wdcdev.channels = sc->wdc_chanarray;
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sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS;
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sc->sc_wdcdev.PIO_cap = 4;
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sc->sc_wdcdev.DMA_cap = 2;
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sc->sc_wdcdev.set_modes = cmd680_setup_channel;
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pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x80, 0x00);
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pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x84, 0x00);
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pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x8a,
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pciide_pci_read(sc->sc_pc, sc->sc_tag, 0x8a) | 0x01);
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for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
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cp = &sc->pciide_channels[channel];
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cmd680_channel_map(pa, sc, channel);
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if (cp->hw_ok == 0)
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continue;
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cmd680_setup_channel(&cp->wdc_channel);
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}
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}
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void
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cmd680_channel_map(pa, sc, channel)
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struct pci_attach_args *pa;
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struct pciide_softc *sc;
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int channel;
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{
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struct pciide_channel *cp = &sc->pciide_channels[channel];
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bus_size_t cmdsize, ctlsize;
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int interface, i, reg;
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static const u_int8_t init_val[] =
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{ 0x8a, 0x32, 0x8a, 0x32, 0x8a, 0x32,
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0x92, 0x43, 0x92, 0x43, 0x09, 0x40, 0x09, 0x40 };
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if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) {
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interface = PCIIDE_INTERFACE_SETTABLE(0) |
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PCIIDE_INTERFACE_SETTABLE(1);
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interface |= PCIIDE_INTERFACE_PCI(0) |
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PCIIDE_INTERFACE_PCI(1);
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} else {
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interface = PCI_INTERFACE(pa->pa_class);
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}
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sc->wdc_chanarray[channel] = &cp->wdc_channel;
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cp->name = PCIIDE_CHANNEL_NAME(channel);
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cp->wdc_channel.channel = channel;
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cp->wdc_channel.wdc = &sc->sc_wdcdev;
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cp->wdc_channel.ch_queue =
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malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT);
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if (cp->wdc_channel.ch_queue == NULL) {
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printf("%s %s channel: "
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"can't allocate memory for command queue",
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sc->sc_wdcdev.sc_dev.dv_xname, cp->name);
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return;
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}
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/* XXX */
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reg = 0xa2 + channel * 16;
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for (i = 0; i < sizeof(init_val); i++)
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pciide_pci_write(sc->sc_pc, sc->sc_tag, reg + i, init_val[i]);
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printf("%s: %s channel %s to %s mode\n",
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sc->sc_wdcdev.sc_dev.dv_xname, cp->name,
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(interface & PCIIDE_INTERFACE_SETTABLE(channel)) ?
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"configured" : "wired",
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(interface & PCIIDE_INTERFACE_PCI(channel)) ?
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"native-PCI" : "compatibility");
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pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, pciide_pci_intr);
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if (cp->hw_ok == 0)
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return;
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pciide_map_compat_intr(pa, cp, channel, interface);
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}
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void
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cmd680_setup_channel(chp)
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struct channel_softc *chp;
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{
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struct ata_drive_datas *drvp;
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u_int8_t mode, off, scsc;
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u_int16_t val;
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u_int32_t idedma_ctl;
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int drive;
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struct pciide_channel *cp = (struct pciide_channel*)chp;
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struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc;
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pci_chipset_tag_t pc = sc->sc_pc;
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pcitag_t pa = sc->sc_tag;
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static const u_int8_t udma2_tbl[] =
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{ 0x0f, 0x0b, 0x07, 0x06, 0x03, 0x02, 0x01 };
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static const u_int8_t udma_tbl[] =
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{ 0x0c, 0x07, 0x05, 0x04, 0x02, 0x01, 0x00 };
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static const u_int16_t dma_tbl[] =
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{ 0x2208, 0x10c2, 0x10c1 };
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static const u_int16_t pio_tbl[] =
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{ 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 };
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idedma_ctl = 0;
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pciide_channel_dma_setup(cp);
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mode = pciide_pci_read(pc, pa, 0x80 + chp->channel * 4);
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for (drive = 0; drive < 2; drive++) {
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drvp = &chp->ch_drive[drive];
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/* If no drive, skip */
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if ((drvp->drive_flags & DRIVE) == 0)
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continue;
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mode &= ~(0x03 << (drive * 4));
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if (drvp->drive_flags & DRIVE_UDMA) {
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drvp->drive_flags &= ~DRIVE_DMA;
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off = 0xa0 + chp->channel * 16;
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if (drvp->UDMA_mode > 2 &&
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(pciide_pci_read(pc, pa, off) & 0x01) == 0)
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drvp->UDMA_mode = 2;
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scsc = pciide_pci_read(pc, pa, 0x8a);
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if (drvp->UDMA_mode == 6 && (scsc & 0x30) == 0) {
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pciide_pci_write(pc, pa, 0x8a, scsc | 0x01);
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scsc = pciide_pci_read(pc, pa, 0x8a);
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if ((scsc & 0x30) == 0)
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drvp->UDMA_mode = 5;
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}
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mode |= 0x03 << (drive * 4);
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off = 0xac + chp->channel * 16 + drive * 2;
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val = pciide_pci_read(pc, pa, off) & ~0x3f;
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if (scsc & 0x30)
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val |= udma2_tbl[drvp->UDMA_mode];
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else
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val |= udma_tbl[drvp->UDMA_mode];
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pciide_pci_write(pc, pa, off, val);
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idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
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} else if (drvp->drive_flags & DRIVE_DMA) {
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mode |= 0x02 << (drive * 4);
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off = 0xa8 + chp->channel * 16 + drive * 2;
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val = dma_tbl[drvp->DMA_mode];
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pciide_pci_write(pc, pa, off, val & 0xff);
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pciide_pci_write(pc, pa, off, val >> 8);
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idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
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} else {
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mode |= 0x01 << (drive * 4);
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off = 0xa4 + chp->channel * 16 + drive * 2;
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val = pio_tbl[drvp->PIO_mode];
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pciide_pci_write(pc, pa, off, val & 0xff);
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pciide_pci_write(pc, pa, off, val >> 8);
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}
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}
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pciide_pci_write(pc, pa, 0x80 + chp->channel * 4, mode);
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if (idedma_ctl != 0) {
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/* Add software bits in status register */
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bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh,
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IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel),
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idedma_ctl);
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}
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pciide_print_modes(cp);
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}
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void
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cy693_chip_map(sc, pa)
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struct pciide_softc *sc;
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