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Import RISC-V starfive DTS from https://github.com/starfive-tech/linux.git" 

The files are taken from the visionfive branch with latest DTS related commit

    commit 9b5f280fa413ee76fac20cd575075fc53468d527
    Author: Emil Renner Berthing <kernel@esmil.dk>
    Date:   Sun Oct 31 17:15:58 2021 +0100

        riscv: dts: Add full JH7100, Starlight and VisionFive support
This commit is contained in:
skrll 2024-01-14 07:39:25 +00:00
parent 688f2af965
commit 45e41911cd
26 changed files with 5366 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
distrib/sets/lists/dtb/ad.riscv32
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@ -1,8 +1,14 @@
# $NetBSD: ad.riscv32,v 1.1 2021/11/13 10:13:42 skrll Exp $
# $NetBSD: ad.riscv32,v 1.2 2024/01/14 07:39:25 skrll Exp $
#
# DO NOT EDIT THIS FILE MANUALLY
# Generated by "make update-sets" in sys/dtb
#
./boot/dtb/sifive dtb-base-boot dtb
./boot/dtb/sifive/hifive-unleashed-a00.dtb dtb-base-boot dtb
./boot/dtb/sifive/hifive-unmatched-a00.dtb dtb-base-boot dtb
./boot/dtb/sifive dtb-base-boot dtb
./boot/dtb/sifive/hifive-unleashed-a00.dtb dtb-base-boot dtb
./boot/dtb/sifive/hifive-unmatched-a00.dtb dtb-base-boot dtb
./boot/dtb/starfive dtb-base-boot dtb
./boot/dtb/starfive/jh7100-beaglev-starlight-a1.dtb dtb-base-boot dtb
./boot/dtb/starfive/jh7100-beaglev-starlight.dtb dtb-base-boot dtb
./boot/dtb/starfive/jh7100-starfive-visionfive-v1.dtb dtb-base-boot dtb
./boot/dtb/starfive/jh7110-starfive-visionfive-2-v1.2a.dtb dtb-base-boot dtb
./boot/dtb/starfive/jh7110-starfive-visionfive-2-v1.3b.dtb dtb-base-boot dtb

14
distrib/sets/lists/dtb/ad.riscv64
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@ -1,8 +1,14 @@
# $NetBSD: ad.riscv64,v 1.1 2021/11/13 10:13:42 skrll Exp $
# $NetBSD: ad.riscv64,v 1.2 2024/01/14 07:39:25 skrll Exp $
#
# DO NOT EDIT THIS FILE MANUALLY
# Generated by "make update-sets" in sys/dtb
#
./boot/dtb/sifive dtb-base-boot dtb
./boot/dtb/sifive/hifive-unleashed-a00.dtb dtb-base-boot dtb
./boot/dtb/sifive/hifive-unmatched-a00.dtb dtb-base-boot dtb
./boot/dtb/sifive dtb-base-boot dtb
./boot/dtb/sifive/hifive-unleashed-a00.dtb dtb-base-boot dtb
./boot/dtb/sifive/hifive-unmatched-a00.dtb dtb-base-boot dtb
./boot/dtb/starfive dtb-base-boot dtb
./boot/dtb/starfive/jh7100-beaglev-starlight-a1.dtb dtb-base-boot dtb
./boot/dtb/starfive/jh7100-beaglev-starlight.dtb dtb-base-boot dtb
./boot/dtb/starfive/jh7100-starfive-visionfive-v1.dtb dtb-base-boot dtb
./boot/dtb/starfive/jh7110-starfive-visionfive-2-v1.2a.dtb dtb-base-boot dtb
./boot/dtb/starfive/jh7110-starfive-visionfive-2-v1.3b.dtb dtb-base-boot dtb

3
sys/dtb/riscv/Makefile
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@ -1,7 +1,8 @@
# $NetBSD: Makefile,v 1.1 2021/11/13 10:13:42 skrll Exp $
# $NetBSD: Makefile,v 1.2 2024/01/14 07:39:25 skrll Exp $
TARGETS+= dtblist
SUBDIR+= sifive
SUBDIR+= starfive
.include <bsd.subdir.mk>

8
sys/dtb/riscv/starfive/Makefile Normal file
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@ -0,0 +1,8 @@
# $NetBSD: Makefile,v 1.1 2024/01/14 07:39:25 skrll Exp $
DTSSUBDIR= starfive
DTSMAKEVARS= CONFIG_ARCH_STARFIVE=y
DTSFILESCMD= ${MAKE} -C ${ARCHDTSDIR}/${DTSSUBDIR} ${DTSMAKEVARS} -v dtb-y
DTS= ${DTSFILESCMD:sh}
.include <bsd.dtb.mk>

1
sys/external/gpl2/dts/dist/arch/riscv/boot/dts/Makefile vendored
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@ -1,5 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
subdir-y += sifive
subdir-y += starfive
subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan
subdir-y += microchip

14
sys/external/gpl2/dts/dist/arch/riscv/boot/dts/starfive/Makefile vendored Normal file
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@ -0,0 +1,14 @@
# SPDX-License-Identifier: GPL-2.0
# Enables support for device-tree overlays
DTC_FLAGS_jh7100-beaglev-starlight-a1 := -@
DTC_FLAGS_jh7100-beaglev-starlight := -@
DTC_FLAGS_jh7100-starfive-visionfive-v1 := -@
DTC_FLAGS_jh7110-starfive-visionfive-2-v1.2a := -@
DTC_FLAGS_jh7110-starfive-visionfive-2-v1.3b := -@
dtb-$(CONFIG_ARCH_STARFIVE) += jh7100-beaglev-starlight-a1.dtb
dtb-$(CONFIG_ARCH_STARFIVE) += jh7100-beaglev-starlight.dtb
dtb-$(CONFIG_ARCH_STARFIVE) += jh7100-starfive-visionfive-v1.dtb
dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.2a.dtb
dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.3b.dtb

24
sys/external/gpl2/dts/dist/arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight-a1.dts vendored Normal file
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// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
* Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
*/
/dts-v1/;
#include "jh7100-common.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "BeagleV Starlight Beta A1";
compatible = "beagle,beaglev-starlight-jh7100-a1", "starfive,jh7100";
gpio-restart {
compatible = "gpio-restart";
gpios = <&gpio 63 GPIO_ACTIVE_HIGH>;
priority = <224>;
};
};
&gpio {
/* don't reset gpio mux for serial console and reset gpio */
starfive,keep-gpiomux = <13 14 63>;
};

30
sys/external/gpl2/dts/dist/arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts vendored Normal file
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// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
* Copyright (C) 2021 StarFive Technology Co., Ltd.
* Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
*/
/dts-v1/;
#include "jh7100-common.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "BeagleV Starlight Beta";
compatible = "beagle,beaglev-starlight-jh7100-r0", "starfive,jh7100";
};
&gmac {
phy-handle = <&phy>;
};
&gpio {
/* don't reset gpio mux for serial console on uart3 */
starfive,keep-gpiomux = <13 14>;
};
&mdio {
phy: ethernet-phy@7 {
reg = <7>;
reset-gpios = <&gpio 63 GPIO_ACTIVE_LOW>;
};
};

611
sys/external/gpl2/dts/dist/arch/riscv/boot/dts/starfive/jh7100-common.dtsi vendored Normal file
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// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
* Copyright (C) 2021 StarFive Technology Co., Ltd.
* Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
*/
/dts-v1/;
#include "jh7100.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/pinctrl/pinctrl-starfive-jh7100.h>
/ {
aliases {
mmc0 = &sdio0;
mmc1 = &sdio1;
serial0 = &uart3;
serial1 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
cpus {
timebase-frequency = <6250000>;
};
memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x2 0x0>;
};
leds {
compatible = "gpio-leds";
led-ack {
gpios = <&gpio 43 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_HEARTBEAT;
linux,default-trigger = "heartbeat";
label = "ack";
};
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
linux,cma {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0xa0000000 0x0 0x28000000>;
size = <0x0 0x28000000>;
alignment = <0x0 0x1000>;
reusable;
linux,cma-default;
};
jpu_reserved: framebuffer@c9000000 {
reg = <0x0 0xc9000000 0x0 0x4000000>;
};
nvdla_reserved: framebuffer@d0000000 {
reg = <0x0 0xd0000000 0x0 0x28000000>;
no-map;
};
vin_reserved: framebuffer@f9000000 {
compatible = "shared-dma-pool";
reg = <0x0 0xf9000000 0x0 0x1000000>;
no-map;
};
dma-reserved@fa000000 {
reg = <0x0 0xfa000000 0x0 0x1000000>;
no-map;
};
sffb_reserved: framebuffer@fb000000 {
compatible = "shared-dma-pool";
reg = <0x0 0xfb000000 0x0 0x2000000>;
no-map;
};
linux,dma@107a000000 {
compatible = "shared-dma-pool";
reg = <0x10 0x7a000000 0x0 0x1000000>;
no-map;
linux,dma-default;
};
};
soc {
dma-ranges = <0x00 0x80000000 0x00 0x80000000 0x00 0x7a000000>,
<0x00 0xfa000000 0x10 0x7a000000 0x00 0x01000000>,
<0x00 0xfb000000 0x00 0xfb000000 0x07 0x85000000>;
};
wifi_pwrseq: wifi-pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&gpio 37 GPIO_ACTIVE_LOW>;
};
};
&display {
memory-region = <&sffb_reserved>;
status = "okay";
};
&crtc {
ddr-format = <4>; //<WIN_FMT_RGB565>;
status = "okay";
port: port@0 {
reg = <0>;
crtc_0_out: endpoint {
remote-endpoint = <&hdmi_input0>;
};
};
};
&encoder {
encoder-type = <2>; // 2-TMDS, 3-LVDS, 6-DSI, 8-DPI
status = "okay";
ports {
port@0 {
hdmi_out: endpoint {
remote-endpoint = <&tda998x_0_input>;
};
};
port@1 {
hdmi_input0: endpoint {
remote-endpoint = <&crtc_0_out>;
};
};
};
};
&gmac {
pinctrl-names = "default";
pinctrl-0 = <&gmac_pins>;
phy-mode = "rgmii-id";
status = "okay";
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
};
};
&gpio {
gmac_pins: gmac-0 {
gtxclk-pins {
pins = <PAD_FUNC_SHARE(115)>;
bias-pull-up;
drive-strength = <35>;
input-enable;
input-schmitt-enable;
slew-rate = <0>;
};
miitxclk-pins {
pins = <PAD_FUNC_SHARE(116)>;
bias-pull-up;
drive-strength = <14>;
input-enable;
input-schmitt-disable;
slew-rate = <0>;
};
tx-pins {
pins = <PAD_FUNC_SHARE(117)>,
<PAD_FUNC_SHARE(119)>,
<PAD_FUNC_SHARE(120)>,
<PAD_FUNC_SHARE(121)>,
<PAD_FUNC_SHARE(122)>,
<PAD_FUNC_SHARE(123)>,
<PAD_FUNC_SHARE(124)>,
<PAD_FUNC_SHARE(125)>,
<PAD_FUNC_SHARE(126)>;
bias-pull-up;
drive-strength = <35>;
input-disable;
input-schmitt-disable;
slew-rate = <0>;
};
rxclk-pins {
pins = <PAD_FUNC_SHARE(127)>;
bias-pull-up;
drive-strength = <14>;
input-enable;
input-schmitt-disable;
slew-rate = <6>;
};
rxer-pins {
pins = <PAD_FUNC_SHARE(129)>;
bias-pull-up;
drive-strength = <14>;
input-enable;
input-schmitt-disable;
slew-rate = <0>;
};
rx-pins {
pins = <PAD_FUNC_SHARE(128)>,
<PAD_FUNC_SHARE(130)>,
<PAD_FUNC_SHARE(131)>,
<PAD_FUNC_SHARE(132)>,
<PAD_FUNC_SHARE(133)>,
<PAD_FUNC_SHARE(134)>,
<PAD_FUNC_SHARE(135)>,
<PAD_FUNC_SHARE(136)>,
<PAD_FUNC_SHARE(137)>,
<PAD_FUNC_SHARE(138)>,
<PAD_FUNC_SHARE(139)>,
<PAD_FUNC_SHARE(140)>,
<PAD_FUNC_SHARE(141)>;
bias-pull-up;
drive-strength = <14>;
input-enable;
input-schmitt-enable;
slew-rate = <0>;
};
};
i2c0_pins: i2c0-0 {
i2c-pins {
pinmux = <GPIOMUX(62, GPO_LOW,
GPO_I2C0_PAD_SCK_OEN,
GPI_I2C0_PAD_SCK_IN)>,
<GPIOMUX(61, GPO_LOW,
GPO_I2C0_PAD_SDA_OEN,
GPI_I2C0_PAD_SDA_IN)>;
bias-disable; /* external pull-up */
input-enable;
input-schmitt-enable;
};
};
i2c1_pins: i2c1-0 {
i2c-pins {
pinmux = <GPIOMUX(47, GPO_LOW,
GPO_I2C1_PAD_SCK_OEN,
GPI_I2C1_PAD_SCK_IN)>,
<GPIOMUX(48, GPO_LOW,
GPO_I2C1_PAD_SDA_OEN,
GPI_I2C1_PAD_SDA_IN)>;
bias-pull-up;
input-enable;
input-schmitt-enable;
};
};
i2c2_pins: i2c2-0 {
i2c-pins {
pinmux = <GPIOMUX(60, GPO_LOW,
GPO_I2C2_PAD_SCK_OEN,
GPI_I2C2_PAD_SCK_IN)>,
<GPIOMUX(59, GPO_LOW,
GPO_I2C2_PAD_SDA_OEN,
GPI_I2C2_PAD_SDA_IN)>;
bias-disable; /* external pull-up */
input-enable;
input-schmitt-enable;
};
};
pwmdac_pins: pwmdac-0 {
pwmdac-pins {
pinmux = <GPIOMUX(23, GPO_PWMDAC_LEFT_OUT,
GPO_ENABLE, GPI_NONE)>,
<GPIOMUX(24, GPO_PWMDAC_RIGHT_OUT,
GPO_ENABLE, GPI_NONE)>;
bias-disable;
drive-strength = <35>;
input-disable;
input-schmitt-disable;
slew-rate = <0>;
};
};
pwm_pins: pwm-0 {
pwm-pins {
pinmux = <GPIOMUX(7,
GPO_PWM_PAD_OUT_BIT0,
GPO_PWM_PAD_OE_N_BIT0,
GPI_NONE)>,
<GPIOMUX(5,
GPO_PWM_PAD_OUT_BIT1,
GPO_PWM_PAD_OE_N_BIT1,
GPI_NONE)>;
bias-disable;
drive-strength = <35>;
input-disable;
input-schmitt-disable;
slew-rate = <0>;
};
};
sdio0_pins: sdio0-0 {
clk-pins {
pinmux = <GPIOMUX(54, GPO_SDIO0_PAD_CCLK_OUT,
GPO_ENABLE, GPI_NONE)>;
bias-disable;
input-disable;
input-schmitt-disable;
};
sdio-pins {
pinmux = <GPIOMUX(55, GPO_LOW, GPO_DISABLE,
GPI_SDIO0_PAD_CARD_DETECT_N)>,
<GPIOMUX(53,
GPO_SDIO0_PAD_CCMD_OUT,
GPO_SDIO0_PAD_CCMD_OEN,
GPI_SDIO0_PAD_CCMD_IN)>,
<GPIOMUX(49,
GPO_SDIO0_PAD_CDATA_OUT_BIT0,
GPO_SDIO0_PAD_CDATA_OEN_BIT0,
GPI_SDIO0_PAD_CDATA_IN_BIT0)>,
<GPIOMUX(50,
GPO_SDIO0_PAD_CDATA_OUT_BIT1,
GPO_SDIO0_PAD_CDATA_OEN_BIT1,
GPI_SDIO0_PAD_CDATA_IN_BIT1)>,
<GPIOMUX(51,
GPO_SDIO0_PAD_CDATA_OUT_BIT2,
GPO_SDIO0_PAD_CDATA_OEN_BIT2,
GPI_SDIO0_PAD_CDATA_IN_BIT2)>,
<GPIOMUX(52,
GPO_SDIO0_PAD_CDATA_OUT_BIT3,
GPO_SDIO0_PAD_CDATA_OEN_BIT3,
GPI_SDIO0_PAD_CDATA_IN_BIT3)>;
bias-pull-up;
input-enable;
input-schmitt-enable;
};
};
sdio1_pins: sdio1-0 {
clk-pins {
pinmux = <GPIOMUX(33, GPO_SDIO1_PAD_CCLK_OUT,
GPO_ENABLE, GPI_NONE)>;
bias-disable;
input-disable;
input-schmitt-disable;
};
sdio-pins {
pinmux = <GPIOMUX(29,
GPO_SDIO1_PAD_CCMD_OUT,
GPO_SDIO1_PAD_CCMD_OEN,
GPI_SDIO1_PAD_CCMD_IN)>,
<GPIOMUX(36,
GPO_SDIO1_PAD_CDATA_OUT_BIT0,
GPO_SDIO1_PAD_CDATA_OEN_BIT0,
GPI_SDIO1_PAD_CDATA_IN_BIT0)>,
<GPIOMUX(30,
GPO_SDIO1_PAD_CDATA_OUT_BIT1,
GPO_SDIO1_PAD_CDATA_OEN_BIT1,
GPI_SDIO1_PAD_CDATA_IN_BIT1)>,
<GPIOMUX(34,
GPO_SDIO1_PAD_CDATA_OUT_BIT2,
GPO_SDIO1_PAD_CDATA_OEN_BIT2,
GPI_SDIO1_PAD_CDATA_IN_BIT2)>,
<GPIOMUX(31,
GPO_SDIO1_PAD_CDATA_OUT_BIT3,
GPO_SDIO1_PAD_CDATA_OEN_BIT3,
GPI_SDIO1_PAD_CDATA_IN_BIT3)>;
bias-pull-up;
input-enable;
input-schmitt-enable;
};
};
spi2_pins: spi2-0 {
mosi-pins {
pinmux = <GPIOMUX(18, GPO_SPI2_PAD_TXD,
GPO_ENABLE, GPI_NONE)>;
bias-disable;
input-disable;
input-schmitt-disable;
};
miso-pins {
pinmux = <GPIOMUX(16, GPO_LOW, GPO_DISABLE,
GPI_SPI2_PAD_RXD)>;
bias-pull-up;
input-enable;
input-schmitt-enable;
};
sck-pins {
pinmux = <GPIOMUX(12, GPO_SPI2_PAD_SCK_OUT,
GPO_ENABLE, GPI_NONE)>;
bias-disable;
input-disable;
input-schmitt-disable;
};
ss-pins {
pinmux = <GPIOMUX(15, GPO_SPI2_PAD_SS_0_N,
GPO_ENABLE, GPI_NONE)>,
<GPIOMUX(11, GPO_SPI2_PAD_SS_1_N,
GPO_ENABLE, GPI_NONE)>;
bias-disable;
input-disable;
input-schmitt-disable;
};
};
uart0_pins: uart0-0 {
rx-pins {
pinmux = <GPIOMUX(40, GPO_LOW, GPO_DISABLE,
GPI_UART0_PAD_SIN)>,
<GPIOMUX(39, GPO_LOW, GPO_DISABLE,
GPI_UART0_PAD_CTSN)>;
bias-pull-up;
drive-strength = <14>;
input-enable;
input-schmitt-enable;
};
tx-pins {
pinmux = <GPIOMUX(41, GPO_UART0_PAD_SOUT,
GPO_ENABLE, GPI_NONE)>,
<GPIOMUX(42, GPO_UART0_PAD_RTSN,
GPO_ENABLE, GPI_NONE)>;
bias-disable;
drive-strength = <35>;
input-disable;
input-schmitt-disable;
};
};
uart3_pins: uart3-0 {
rx-pins {
pinmux = <GPIOMUX(13, GPO_LOW, GPO_DISABLE,
GPI_UART3_PAD_SIN)>;
bias-pull-up;
drive-strength = <14>;
input-enable;
input-schmitt-enable;
slew-rate = <0>;
};
tx-pins {
pinmux = <GPIOMUX(14, GPO_UART3_PAD_SOUT,
GPO_ENABLE, GPI_NONE)>;
bias-disable;
drive-strength = <35>;
input-disable;
input-schmitt-disable;
slew-rate = <0>;
};
};
};
&i2c0 {
clock-frequency = <100000>;
i2c-sda-hold-time-ns = <300>;
i2c-sda-falling-time-ns = <500>;
i2c-scl-falling-time-ns = <500>;
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
status = "okay";
pmic@5e {
compatible = "ti,tps65086";
reg = <0x5e>;
gpio-controller;
#gpio-cells = <2>;
regulators {
};
};
tda998x@70 {
compatible = "nxp,tda998x";
reg = <0x70>;
port {
tda998x_0_input: endpoint {
remote-endpoint = <&hdmi_out>;
};
};
};
};
&i2c1 {
clock-frequency = <400000>;
i2c-sda-hold-time-ns = <300>;
i2c-sda-falling-time-ns = <100>;
i2c-scl-falling-time-ns = <100>;
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
status = "okay";
};
&i2c2 {
clock-frequency = <100000>;
i2c-sda-hold-time-ns = <300>;
i2c-sda-falling-time-ns = <500>;
i2c-scl-falling-time-ns = <500>;
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins>;
status = "okay";
};
&osc_sys {
clock-frequency = <25000000>;
};
&osc_aud {
clock-frequency = <27000000>;
};
&pwm {
pinctrl-names = "default";
pinctrl-0 = <&pwm_pins>;
status = "okay";
};
&pwmdac {
pinctrl-names = "default";
pinctrl-0 = <&pwmdac_pins>;
status = "okay";
};
&qspi {
nor_flash: nor-flash@0 {
compatible = "spi-flash";
reg = <0>;
spi-max-frequency = <31250000>;
page-size = <256>;
block-size = <16>;
cdns,read-delay = <4>;
cdns,tshsl-ns = <1>;
cdns,tsd2d-ns = <1>;
cdns,tchsh-ns = <1>;
cdns,tslch-ns = <1>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <1>;
};
nand_flash: nand-flash@1 {
compatible = "spi-flash-nand";
reg = <1>;
spi-max-frequency = <31250000>;
page-size = <2048>;
block-size = <17>;
cdns,read-delay = <4>;
cdns,tshsl-ns = <1>;
cdns,tsd2d-ns = <1>;
cdns,tchsh-ns = <1>;
cdns,tslch-ns = <1>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <1>;
};
};
&sdio0 {
broken-cd;
bus-width = <4>;
cap-sd-highspeed;
pinctrl-names = "default";
pinctrl-0 = <&sdio0_pins>;
status = "okay";
};
&sdio1 {
#address-cells = <1>;
#size-cells = <0>;
bus-width = <4>;
cap-sd-highspeed;
cap-sdio-irq;
cap-power-off-card;
mmc-pwrseq = <&wifi_pwrseq>;
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&sdio1_pins>;
status = "okay";
wifi@1 {
compatible = "brcm,bcm4329-fmac";
reg = <1>;
};
};
&spi2 {
pinctrl-names = "default";
pinctrl-0 = <&spi2_pins>;
status = "okay";
spi_dev0: spi@0 {
compatible = "rohm,dh2228fv";
spi-max-frequency = <10000000>;
reg = <0>;
};
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&uart3_pins>;
status = "okay";
};
&usb3 {
dr_mode = "host";
status = "okay";
};

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// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
* Copyright (C) 2021 StarFive Technology Co., Ltd.
* Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
*/
/dts-v1/;
#include "jh7100-common.dtsi"
/ {
model = "StarFive VisionFive V1";
compatible = "starfive,visionfive-v1", "starfive,jh7100";
gpio-restart {
compatible = "gpio-restart";
gpios = <&gpio 63 GPIO_ACTIVE_HIGH>;
priority = <224>;
};
};
&gmac {
phy-handle = <&phy>;
};
&gpio {
/* don't reset gpio mux for serial console and reset gpio */
starfive,keep-gpiomux = <13 14 63>;
};
&i2c0 {
eeprom@50 {
compatible = "atmel,24c04";
reg = <0x50>;
pagesize = <16>;
};
};
/*
* The board uses a Motorcomm YT8521 PHY supporting RGMII-ID, but requires
* manual adjustment of the RX internal delay to work properly. The default
* RX delay provided by the driver (1.95ns) is too high, but applying a 50%
* reduction seems to mitigate the issue.
*
* It is worth noting the adjustment is not necessary on BeagleV Starlight SBC,
* which uses a Microchip PHY. Hence, most likely the Motorcomm PHY is the one
* responsible for the misbehaviour, not the GMAC.
*/
&mdio {
phy: ethernet-phy@0 {
reg = <0>;
rx-internal-delay-ps = <900>;
};
};

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// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
* Copyright (C) 2021 StarFive Technology Co., Ltd.
* Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
*/
/dts-v1/;
#include <dt-bindings/clock/starfive-jh7100.h>
#include <dt-bindings/clock/starfive-jh7100-audio.h>
#include <dt-bindings/reset/starfive-jh7100.h>
#include <dt-bindings/reset/starfive-jh7100-audio.h>
/ {
compatible = "starfive,jh7100";
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
U74_0: cpu@0 {
compatible = "sifive,u74-mc", "riscv";
reg = <0>;
d-cache-block-size = <64>;
d-cache-sets = <64>;
d-cache-size = <32768>;
d-tlb-sets = <1>;
d-tlb-size = <32>;
device_type = "cpu";
i-cache-block-size = <64>;
i-cache-sets = <64>;
i-cache-size = <32768>;
i-tlb-sets = <1>;
i-tlb-size = <32>;
mmu-type = "riscv,sv39";
next-level-cache = <&ccache>;
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
"zifencei", "zihpm";
starfive,itim = <&itim0>;
tlb-split;
cpu0_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
U74_1: cpu@1 {
compatible = "sifive,u74-mc", "riscv";
reg = <1>;
d-cache-block-size = <64>;
d-cache-sets = <64>;
d-cache-size = <32768>;
d-tlb-sets = <1>;
d-tlb-size = <32>;
device_type = "cpu";
i-cache-block-size = <64>;
i-cache-sets = <64>;
i-cache-size = <32768>;
i-tlb-sets = <1>;
i-tlb-size = <32>;
mmu-type = "riscv,sv39";
next-level-cache = <&ccache>;
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
"zifencei", "zihpm";
starfive,itim = <&itim1>;
tlb-split;
cpu1_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
cpu-map {
cluster0 {
core0 {
cpu = <&U74_0>;
};
core1 {
cpu = <&U74_1>;
};
};
};
};
thermal-zones {
cpu-thermal {
polling-delay-passive = <250>;
polling-delay = <15000>;
thermal-sensors = <&sfctemp>;
trips {
cpu_alert0 {
/* milliCelsius */
temperature = <75000>;
hysteresis = <2000>;
type = "passive";
};
cpu_crit {
/* milliCelsius */
temperature = <90000>;
hysteresis = <2000>;
type = "critical";
};
};
};
};
osc_sys: osc_sys {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
};
osc_aud: osc_aud {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
};
gmac_rmii_ref: gmac_rmii_ref {
compatible = "fixed-clock";
#clock-cells = <0>;
/* Should be overridden by the board when needed */
clock-frequency = <0>;
};
gmac_gr_mii_rxclk: gmac_gr_mii_rxclk {
compatible = "fixed-clock";
#clock-cells = <0>;
/* Should be overridden by the board when needed */
clock-frequency = <0>;
};
soc {
compatible = "simple-bus";
interrupt-parent = <&plic>;
#address-cells = <2>;
#size-cells = <2>;
dma-noncoherent;
ranges;
dtim: dtim@1000000 {
compatible = "starfive,dtim0";
reg = <0x0 0x1000000 0x0 0x2000>;
reg-names = "mem";
};
itim0: itim@1808000 {
compatible = "starfive,itim0";
reg = <0x0 0x1808000 0x0 0x8000>;
reg-names = "mem";
};
itim1: itim@1820000 {
compatible = "starfive,itim0";
reg = <0x0 0x1820000 0x0 0x8000>;
reg-names = "mem";
};
clint: clint@2000000 {
compatible = "starfive,jh7100-clint", "sifive,clint0";
reg = <0x0 0x2000000 0x0 0x10000>;
interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
<&cpu1_intc 3>, <&cpu1_intc 7>;
};
ccache: cache-controller@2010000 {
compatible = "starfive,jh7100-ccache", "sifive,ccache0", "cache";
reg = <0x0 0x2010000 0x0 0x1000>;
interrupts = <128>, <130>, <131>, <129>;
cache-block-size = <64>;
cache-level = <2>;
cache-sets = <2048>;
cache-size = <2097152>;
cache-unified;
};
plic: interrupt-controller@c000000 {
compatible = "starfive,jh7100-plic", "sifive,plic-1.0.0";
reg = <0x0 0xc000000 0x0 0x4000000>;
interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
<&cpu1_intc 11>, <&cpu1_intc 9>;
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
riscv,ndev = <133>;
};
sdio0: mmc@10000000 {
compatible = "snps,dw-mshc";
reg = <0x0 0x10000000 0x0 0x10000>;
clocks = <&clkgen JH7100_CLK_SDIO0_AHB>,
<&clkgen JH7100_CLK_SDIO0_CCLKINT_INV>;
clock-names = "biu", "ciu";
interrupts = <4>;
data-addr = <0>;
fifo-depth = <32>;
fifo-watermark-aligned;
status = "disabled";
};
sdio1: mmc@10010000 {
compatible = "snps,dw-mshc";
reg = <0x0 0x10010000 0x0 0x10000>;
clocks = <&clkgen JH7100_CLK_SDIO1_AHB>,
<&clkgen JH7100_CLK_SDIO1_CCLKINT_INV>;
clock-names = "biu", "ciu";
interrupts = <5>;
data-addr = <0>;
fifo-depth = <32>;
fifo-watermark-aligned;
status = "disabled";
};
gmac: ethernet@10020000 {
compatible = "starfive,jh7100-dwmac", "snps,dwmac";
reg = <0x0 0x10020000 0x0 0x10000>;
clocks = <&clkgen JH7100_CLK_GMAC_ROOT_DIV>,
<&clkgen JH7100_CLK_GMAC_AHB>,
<&clkgen JH7100_CLK_GMAC_PTP_REF>,
<&clkgen JH7100_CLK_GMAC_TX_INV>,
<&clkgen JH7100_CLK_GMAC_GTX>;
clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "gtx";
resets = <&rstgen JH7100_RSTN_GMAC_AHB>;
reset-names = "ahb";
interrupts = <6>, <7>;
interrupt-names = "macirq", "eth_wake_irq";
max-frame-size = <9000>;
snps,multicast-filter-bins = <32>;
snps,perfect-filter-entries = <128>;
starfive,syscon = <&sysmain 0x70 0>;
rx-fifo-depth = <32768>;
tx-fifo-depth = <16384>;
snps,axi-config = <&stmmac_axi_setup>;
snps,fixed-burst;
snps,force_thresh_dma_mode;
status = "disabled";
stmmac_axi_setup: stmmac-axi-config {
snps,wr_osr_lmt = <16>;
snps,rd_osr_lmt = <16>;
snps,blen = <256 128 64 32 0 0 0>;
};
};
dma2p: dma-controller@100b0000 {
compatible = "starfive,jh7100-axi-dma";
reg = <0x0 0x100b0000 0x0 0x10000>;
clocks = <&clkgen JH7100_CLK_SGDMA2P_AXI>,
<&clkgen JH7100_CLK_SGDMA2P_AHB>;
clock-names = "core-clk", "cfgr-clk";
resets = <&rstgen JH7100_RSTN_SGDMA2P_AXI>,
<&rstgen JH7100_RSTN_SGDMA2P_AHB>;
reset-names = "axi", "ahb";
interrupts = <2>;
#dma-cells = <1>;
dma-channels = <4>;
snps,dma-masters = <1>;
snps,data-width = <4>;
snps,block-size = <4096 4096 4096 4096>;
snps,priority = <0 1 2 3>;
snps,axi-max-burst-len = <128>;
dma-coherent;
};
crypto: crypto@100d0000 {
compatible = "starfive,vic-sec";
reg = <0x0 0x100d0000 0x0 0x20000>,
<0x0 0x11800234 0x0 0xc>;
reg-names = "secmem", "secclk";
clocks = <&clkgen JH7100_CLK_SEC_AHB>;
interrupts = <31>;
};
i2sadc0: i2sadc0@10400000 {
compatible = "snps,designware-i2sadc0";
reg = <0x0 0x10400000 0x0 0x1000>;
clocks = <&clkgen JH7100_CLK_APB1_BUS>;
clock-names = "i2sclk";
interrupt-parent = <&plic>;
#sound-dai-cells = <0>;
dmas = <&dma2p 28>;
dma-names = "rx";
};
i2svad: i2svad@10420000 {
compatible = "starfive,sf-i2svad";
reg = <0x0 0x10420000 0x0 0x1000> ;
clocks = <&audclk JH7100_AUDCLK_I2SVAD_APB>;
clock-names = "i2svad_apb";
resets = <&audrst JH7100_AUDRSTN_I2SVAD_APB>,
<&audrst JH7100_AUDRSTN_I2SVAD_SRST>;
reset-names = "apb_i2svad", "i2svad_srst";
interrupts = <60>, <61>;
interrupt-names = "spintr", "slintr";
#sound-dai-cells = <0>;
};
pwmdac: pwmdac@10440000 {
compatible = "starfive,pwmdac";
reg = <0x0 0x10440000 0x0 0x1000>;
clocks = <&clkgen JH7100_CLK_AUDIO_ROOT>,
<&clkgen JH7100_CLK_AUDIO_SRC>,
<&clkgen JH7100_CLK_AUDIO_12288>,
<&audclk JH7100_AUDCLK_DMA1P_AHB>,
<&audclk JH7100_AUDCLK_PWMDAC_APB>,
<&audclk JH7100_AUDCLK_DAC_MCLK>;
clock-names = "audio_root",
"audio_src",
"audio_12288",
"dma1p_ahb",
"pwmdac_apb",
"dac_mclk";
resets = <&audrst JH7100_AUDRSTN_APB_BUS>,
<&audrst JH7100_AUDRSTN_DMA1P_AHB>,
<&audrst JH7100_AUDRSTN_PWMDAC_APB>;
reset-names = "apb_bus", "dma1p_ahb", "apb_pwmdac";
dmas = <&dma2p 23>;
dma-names = "tx";
#sound-dai-cells = <0>;
};
i2sdac0: i2sdac0@10450000 {
compatible = "snps,designware-i2sdac0";
reg = <0x0 0x10450000 0x0 0x1000>;
clocks = <&audclk JH7100_AUDCLK_DAC_MCLK>,
<&audclk JH7100_AUDCLK_I2SDAC_BCLK>,
<&audclk JH7100_AUDCLK_I2SDAC_LRCLK>,
<&audclk JH7100_AUDCLK_I2SDAC_APB>;
clock-names = "dac_mclk", "i2sdac0_bclk", "i2sdac0_lrclk", "i2sdac_apb";
resets = <&audrst JH7100_AUDRSTN_I2SDAC_APB>,
<&audrst JH7100_AUDRSTN_I2SDAC_SRST>;
reset-names = "apb_i2sdac", "i2sdac_srst";
#sound-dai-cells = <0>;
dmas = <&dma2p 30>;
dma-names = "tx";
};
i2sdac1: i2sdac1@10460000 {
compatible = "snps,designware-i2sdac1";
reg = <0x0 0x10460000 0x0 0x1000>;
clocks = <&audclk JH7100_AUDCLK_DAC_MCLK>,
<&audclk JH7100_AUDCLK_I2S1_BCLK>,
<&audclk JH7100_AUDCLK_I2S1_LRCLK>,
<&audclk JH7100_AUDCLK_I2S1_APB>;
clock-names = "dac_mclk", "i2sdac1_bclk", "i2sdac1_lrclk", "i2s1_apb";
resets = <&audrst JH7100_AUDRSTN_I2S1_APB>,
<&audrst JH7100_AUDRSTN_I2S1_SRST>;
#sound-dai-cells = <0>;
dmas = <&dma2p 31>;
dma-names = "tx";
};
i2sdac16k: i2sdac16k@10470000 {
compatible = "snps,designware-i2sdac16k";
reg = <0x0 0x10470000 0x0 0x1000>;
clocks = <&clkgen JH7100_CLK_APB1_BUS>;
clock-names = "i2sclk";
#sound-dai-cells = <0>;
dmas = <&dma2p 29>;
dma-names = "tx";
};
audclk: clock-controller@10480000 {
compatible = "starfive,jh7100-audclk";
reg = <0x0 0x10480000 0x0 0x10000>;
clocks = <&clkgen JH7100_CLK_AUDIO_SRC>,
<&clkgen JH7100_CLK_AUDIO_12288>,
<&clkgen JH7100_CLK_DOM7AHB_BUS>;
clock-names = "audio_src", "audio_12288", "dom7ahb_bus";
#clock-cells = <1>;
};
audrst: reset-controller@10490000 {
compatible = "starfive,jh7100-audrst";
reg = <0x0 0x10490000 0x0 0x10000>;
#reset-cells = <1>;
};
spdif_transmitter: spdif-transmitter {
compatible = "linux,spdif-dit";
#sound-dai-cells = <0>;
};
spdif_receiver: spdif-receiver {
compatible = "linux,spdif-dir";
#sound-dai-cells = <0>;
};
pwmdac_codec: pwmdac-transmitter {
compatible = "linux,pwmdac-dit";
#sound-dai-cells = <0>;
};
dmic_codec: dmic {
compatible = "dmic-codec";
#sound-dai-cells = <0>;
};
sound: snd-card {
compatible = "simple-audio-card";
simple-audio-card,name = "Starfive-Multi-Sound-Card";
#address-cells = <1>;
#size-cells = <0>;
/* pwmdac */
simple-audio-card,dai-link@0 {
reg = <0>;
status = "okay";
format = "left_j";
bitclock-master = <&sndcpu0>;
frame-master = <&sndcpu0>;
sndcpu0: cpu {
sound-dai = <&pwmdac>;
};
codec {
sound-dai = <&pwmdac_codec>;
};
};
};
sysaudio: syscon@104a0000 {
compatible = "starfive,jh7100-sysaudio", "syscon";
reg = <0x0 0x104a0000 0x0 0x10000>;
};
usb3: usb@104c0000 {
compatible = "starfive,jh7100-usb";
ranges = <0x0 0x0 0x104c0000 0x100000>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&audclk JH7100_AUDCLK_USB_LPM>,
<&audclk JH7100_AUDCLK_USB_STB>,
<&clkgen JH7100_CLK_USB_AXI>,
<&clkgen JH7100_CLK_USBNOC_AXI>;
clock-names = "lpm", "stb", "axi", "nocaxi";
resets = <&rstgen JH7100_RSTN_USB_AXI>,
<&rstgen JH7100_RSTN_USBNOC_AXI>;
reset-names = "axi", "nocaxi";
starfive,syscon = <&sysaudio>;
status = "disabled";
usb_cdns3: usb@0 {
compatible = "cdns,usb3";
reg = <0x00000 0x10000>,
<0x10000 0x10000>,
<0x20000 0x10000>;
reg-names = "otg", "xhci", "dev";
interrupts = <44>, <52>, <43>;
interrupt-names = "host", "peripheral", "otg";
};
};
dma1p: dma-controller@10500000 {
compatible = "starfive,jh7100-axi-dma";
reg = <0x0 0x10500000 0x0 0x10000>;
clocks = <&clkgen JH7100_CLK_SGDMA1P_AXI>,
<&clkgen JH7100_CLK_SGDMA1P_BUS>;
clock-names = "core-clk", "cfgr-clk";
resets = <&rstgen JH7100_RSTN_DMA1P_AXI>,
<&rstgen JH7100_RSTN_SGDMA1P_AXI>;
reset-names = "axi", "ahb";
interrupts = <1>;
#dma-cells = <1>;
dma-channels = <16>;
snps,dma-masters = <1>;
snps,data-width = <3>;
snps,block-size = <4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096>;
snps,priority = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
snps,axi-max-burst-len = <64>;
};
clkgen: clock-controller@11800000 {
compatible = "starfive,jh7100-clkgen";
reg = <0x0 0x11800000 0x0 0x10000>;
clocks = <&osc_sys>, <&osc_aud>, <&gmac_rmii_ref>, <&gmac_gr_mii_rxclk>;
clock-names = "osc_sys", "osc_aud", "gmac_rmii_ref", "gmac_gr_mii_rxclk";
#clock-cells = <1>;
};
otp: otp@11810000 {
compatible = "starfive,fu740-otp";
reg = <0x0 0x11810000 0x0 0x10000>;
clocks = <&clkgen JH7100_CLK_OTP_APB>;
fuse-count = <0x200>;
};
rstgen: reset-controller@11840000 {
compatible = "starfive,jh7100-reset";
reg = <0x0 0x11840000 0x0 0x10000>;
#reset-cells = <1>;
};
sysmain: syscon@11850000 {
compatible = "starfive,jh7100-sysmain", "syscon";
reg = <0x0 0x11850000 0x0 0x10000>;
};
qspi: spi@11860000 {
compatible = "cdns,qspi-nor";
reg = <0x0 0x11860000 0x0 0x10000>,
<0x0 0x20000000 0x0 0x20000000>;
clocks = <&clkgen JH7100_CLK_QSPI_AHB>;
interrupts = <3>;
#address-cells = <1>;
#size-cells = <0>;
cdns,fifo-depth = <256>;
cdns,fifo-width = <4>;
cdns,trigger-address = <0x0>;
spi-max-frequency = <250000000>;
status = "disabled";
};
uart0: serial@11870000 {
compatible = "starfive,jh7100-hsuart", "snps,dw-apb-uart";
reg = <0x0 0x11870000 0x0 0x10000>;
clocks = <&clkgen JH7100_CLK_UART0_CORE>,
<&clkgen JH7100_CLK_UART0_APB>;
clock-names = "baudclk", "apb_pclk";
resets = <&rstgen JH7100_RSTN_UART0_APB>;
interrupts = <92>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
};
uart1: serial@11880000 {
compatible = "starfive,jh7100-hsuart", "snps,dw-apb-uart";
reg = <0x0 0x11880000 0x0 0x10000>;
clocks = <&clkgen JH7100_CLK_UART1_CORE>,
<&clkgen JH7100_CLK_UART1_APB>;
clock-names = "baudclk", "apb_pclk";
resets = <&rstgen JH7100_RSTN_UART1_APB>;
interrupts = <93>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
};
spi0: spi@11890000 {
compatible = "snps,dw-apb-ssi";
reg = <0x0 0x11890000 0x0 0x10000>;
clocks = <&clkgen JH7100_CLK_SPI0_CORE>,
<&clkgen JH7100_CLK_SPI0_APB>;
clock-names = "ssi_clk", "pclk";
resets = <&rstgen JH7100_RSTN_SPI0_APB>;
reset-names = "spi";
interrupts = <94>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi1: spi@118a0000 {
compatible = "snps,dw-apb-ssi";
reg = <0x0 0x118a0000 0x0 0x10000>;
clocks = <&clkgen JH7100_CLK_SPI1_CORE>,
<&clkgen JH7100_CLK_SPI1_APB>;
clock-names = "ssi_clk", "pclk";
resets = <&rstgen JH7100_RSTN_SPI1_APB>;
reset-names = "spi";
interrupts = <95>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c0: i2c@118b0000 {
compatible = "snps,designware-i2c";
reg = <0x0 0x118b0000 0x0 0x10000>;
clocks = <&clkgen JH7100_CLK_I2C0_CORE>,
<&clkgen JH7100_CLK_I2C0_APB>;
clock-names = "ref", "pclk";
resets = <&rstgen JH7100_RSTN_I2C0_APB>;
interrupts = <96>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c1: i2c@118c0000 {
compatible = "snps,designware-i2c";
reg = <0x0 0x118c0000 0x0 0x10000>;
clocks = <&clkgen JH7100_CLK_I2C1_CORE>,
<&clkgen JH7100_CLK_I2C1_APB>;
clock-names = "ref", "pclk";
resets = <&rstgen JH7100_RSTN_I2C1_APB>;
interrupts = <97>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
trng: trng@118d0000 {
compatible = "starfive,vic-rng";
reg = <0x0 0x118d0000 0x0 0x10000>;
clocks = <&clkgen JH7100_CLK_TRNG_APB>;
interrupts = <98>;
};
vpu_enc: vpu_enc@118e0000 {
compatible = "cm,cm521-vpu";
reg = <0x0 0x118e0000 0x0 0x4000>;
reg-names = "control";
clocks = <&clkgen JH7100_CLK_VP6_CORE>;
clock-names = "vcodec";
interrupts = <26>;
};
vpu_dec: vpu_dec@118f0000 {
compatible = "c&m,cm511-vpu";
reg = <0 0x118f0000 0 0x10000>;
clocks = <&clkgen JH7100_CLK_VP6_CORE>;
clock-names = "vcodec";
interrupts = <23>;
//memory-region = <&vpu_reserved>;
};
jpu: coadj12@11900000 {
compatible = "cm,codaj12-jpu-1";
reg = <0x0 0x11900000 0x0 0x300>;
reg-names = "control";
clocks = <&clkgen JH7100_CLK_JPEG_APB>;
clock-names = "jpege";
interrupts = <24>;
memory-region = <&jpu_reserved>;
};
gpio: pinctrl@11910000 {
compatible = "starfive,jh7100-pinctrl";
reg = <0x0 0x11910000 0x0 0x10000>,
<0x0 0x11858000 0x0 0x1000>;
reg-names = "gpio", "padctl";
clocks = <&clkgen JH7100_CLK_GPIO_APB>;
resets = <&rstgen JH7100_RSTN_GPIO_APB>;
interrupts = <32>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
nvdla@11940000 {
compatible = "nvidia,nvdla_os_initial";
interrupts = <22>;
memory-region = <&nvdla_reserved>;
reg = <0x0 0x11940000 0x0 0x40000>;
status = "okay";
};
display: display-subsystem {
compatible = "starfive,display-subsystem";
dma-coherent;
status = "disabled";
};
encoder: display-encoder {
compatible = "starfive,display-encoder";
status = "disabled";
};
crtc: crtc@12000000 {
compatible = "starfive,jh7100-crtc";
reg = <0x0 0x12000000 0x0 0x10000>,
<0x0 0x12040000 0x0 0x10000>,
<0x0 0x12080000 0x0 0x10000>,
<0x0 0x120c0000 0x0 0x10000>,
<0x0 0x12240000 0x0 0x10000>,
<0x0 0x12250000 0x0 0x10000>,
<0x0 0x12260000 0x0 0x10000>;
reg-names = "lcdc", "vpp0", "vpp1", "vpp2", "clk", "rst", "sys";
clocks = <&clkgen JH7100_CLK_DISP_AXI>, <&clkgen JH7100_CLK_VOUT_SRC>;
clock-names = "disp_axi", "vout_src";
resets = <&rstgen JH7100_RSTN_DISP_AXI>, <&rstgen JH7100_RSTN_VOUT_SRC>;
reset-names = "disp_axi", "vout_src";
interrupts = <101>, <103>;
interrupt-names = "lcdc_irq", "vpp1_irq";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
pp1 {
pp-id = <1>;
fifo-out;
//sys-bus-out;
src-format = <11>; //<COLOR_RGB565>;
src-width = <1920>;
src-height = <1080>;
dst-format = <7>; //<COLOR_RGB888_ARGB>;
dst-width = <1920>;
dst-height = <1080>;
};
};
spi2: spi@12410000 {
compatible = "snps,dw-apb-ssi";
reg = <0x0 0x12410000 0x0 0x10000>;
clocks = <&clkgen JH7100_CLK_SPI2_CORE>,
<&clkgen JH7100_CLK_SPI2_APB>;
clock-names = "ssi_clk", "pclk";
resets = <&rstgen JH7100_RSTN_SPI2_APB>;
reset-names = "spi";
interrupts = <70>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi3: spi@12420000 {
compatible = "snps,dw-apb-ssi";
reg = <0x0 0x12420000 0x0 0x10000>;
clocks = <&clkgen JH7100_CLK_SPI3_CORE>,
<&clkgen JH7100_CLK_SPI3_APB>;
clock-names = "ssi_clk", "pclk";
resets = <&rstgen JH7100_RSTN_SPI3_APB>;
reset-names = "spi";
interrupts = <71>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
uart2: serial@12430000 {
compatible = "starfive,jh7100-uart", "snps,dw-apb-uart";
reg = <0x0 0x12430000 0x0 0x10000>;
clocks = <&clkgen JH7100_CLK_UART2_CORE>,
<&clkgen JH7100_CLK_UART2_APB>;
clock-names = "baudclk", "apb_pclk";
resets = <&rstgen JH7100_RSTN_UART2_APB>;
interrupts = <72>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
};
uart3: serial@12440000 {
compatible = "starfive,jh7100-uart", "snps,dw-apb-uart";
reg = <0x0 0x12440000 0x0 0x10000>;
clocks = <&clkgen JH7100_CLK_UART3_CORE>,
<&clkgen JH7100_CLK_UART3_APB>;
clock-names = "baudclk", "apb_pclk";
resets = <&rstgen JH7100_RSTN_UART3_APB>;
interrupts = <73>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
};
i2c2: i2c@12450000 {
compatible = "snps,designware-i2c";
reg = <0x0 0x12450000 0x0 0x10000>;
clocks = <&clkgen JH7100_CLK_I2C2_CORE>,
<&clkgen JH7100_CLK_I2C2_APB>;
clock-names = "ref", "pclk";
resets = <&rstgen JH7100_RSTN_I2C2_APB>;
interrupts = <74>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c3: i2c@12460000 {
compatible = "snps,designware-i2c";
reg = <0x0 0x12460000 0x0 0x10000>;
clocks = <&clkgen JH7100_CLK_I2C3_CORE>,
<&clkgen JH7100_CLK_I2C3_APB>;
clock-names = "ref", "pclk";
resets = <&rstgen JH7100_RSTN_I2C3_APB>;
interrupts = <75>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
watchdog@12480000 {
compatible = "starfive,jh7100-wdt";
reg = <0x0 0x12480000 0x0 0x10000>;
clocks = <&clkgen JH7100_CLK_WDTIMER_APB>,
<&clkgen JH7100_CLK_WDT_CORE>;
clock-names = "apb", "core";
resets = <&rstgen JH7100_RSTN_WDTIMER_APB>,
<&rstgen JH7100_RSTN_WDT>;
};
pwm: pwm@12490000 {
compatible = "starfive,jh7100-pwm", "opencores,pwm-v1";
reg = <0x0 0x12490000 0x0 0x10000>;
clocks = <&clkgen JH7100_CLK_PWM_APB>;
resets = <&rstgen JH7100_RSTN_PWM_APB>;
#pwm-cells = <3>;
status = "disabled";
};
sfctemp: temperature-sensor@124a0000 {
compatible = "starfive,jh7100-temp";
reg = <0x0 0x124a0000 0x0 0x10000>;
clocks = <&clkgen JH7100_CLK_TEMP_SENSE>,
<&clkgen JH7100_CLK_TEMP_APB>;
clock-names = "sense", "bus";
resets = <&rstgen JH7100_RSTN_TEMP_SENSE>,
<&rstgen JH7100_RSTN_TEMP_APB>;
reset-names = "sense", "bus";
#thermal-sensor-cells = <0>;
};
xrp@f0000000 {
compatible = "cdns,xrp";
reg = <0x0 0xf0000000 0x0 0x01ffffff>,
<0x10 0x72000000 0x0 0x00001000>,
<0x10 0x72001000 0x0 0x00fff000>,
<0x0 0x124b0000 0x0 0x00010000>;
clocks = <&clkgen JH7100_CLK_VP6_CORE>;
interrupts = <27>, <28>;
firmware-name = "vp6_elf";
dsp-irq = <19 20>;
dsp-irq-src = <0x20 0x21>;
intc-irq-mode = <1>;
intc-irq = <0 1>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x40000000 0x0 0x40000000 0x01000000>,
<0xb0000000 0x10 0x70000000 0x3000000>;
dsp@0 {
};
};
};
};

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sys/external/gpl2/dts/dist/arch/riscv/boot/dts/starfive/jh7110-pinfunc.h vendored Normal file
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/* SPDX-License-Identifier: GPL-2.0 OR MIT */
/*
* Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
* Copyright (C) 2022 StarFive Technology Co., Ltd.
*/
#ifndef __JH7110_PINFUNC_H__
#define __JH7110_PINFUNC_H__
/*
* mux bits:
* | 31 - 24 | 23 - 16 | 15 - 10 | 9 - 8 | 7 - 0 |
* | din | dout | doen | function | gpio nr |
*
* dout: output signal
* doen: output enable signal
* din: optional input signal, 0xff = none
* function: function selector
* gpio nr: gpio number, 0 - 63
*/
#define GPIOMUX(n, dout, doen, din) ( \
(((din) & 0xff) << 24) | \
(((dout) & 0xff) << 16) | \
(((doen) & 0x3f) << 10) | \
((n) & 0x3f))
#define PINMUX(n, func) ((1 << 10) | (((func) & 0x3) << 8) | ((n) & 0xff))
/* sys_iomux dout */
#define GPOUT_LOW 0
#define GPOUT_HIGH 1
#define GPOUT_SYS_WAVE511_UART_TX 2
#define GPOUT_SYS_CAN0_STBY 3
#define GPOUT_SYS_CAN0_TST_NEXT_BIT 4
#define GPOUT_SYS_CAN0_TST_SAMPLE_POINT 5
#define GPOUT_SYS_CAN0_TXD 6
#define GPOUT_SYS_USB_DRIVE_VBUS 7
#define GPOUT_SYS_QSPI_CS1 8
#define GPOUT_SYS_SPDIF 9
#define GPOUT_SYS_HDMI_CEC_SDA 10
#define GPOUT_SYS_HDMI_DDC_SCL 11
#define GPOUT_SYS_HDMI_DDC_SDA 12
#define GPOUT_SYS_WATCHDOG 13
#define GPOUT_SYS_I2C0_CLK 14
#define GPOUT_SYS_I2C0_DATA 15
#define GPOUT_SYS_SDIO0_BACK_END_POWER 16
#define GPOUT_SYS_SDIO0_CARD_POWER_EN 17
#define GPOUT_SYS_SDIO0_CCMD_OD_PULLUP_EN 18
#define GPOUT_SYS_SDIO0_RST 19
#define GPOUT_SYS_UART0_TX 20
#define GPOUT_SYS_HIFI4_JTAG_TDO 21
#define GPOUT_SYS_JTAG_TDO 22
#define GPOUT_SYS_PDM_MCLK 23
#define GPOUT_SYS_PWM_CHANNEL0 24
#define GPOUT_SYS_PWM_CHANNEL1 25
#define GPOUT_SYS_PWM_CHANNEL2 26
#define GPOUT_SYS_PWM_CHANNEL3 27
#define GPOUT_SYS_PWMDAC_LEFT 28
#define GPOUT_SYS_PWMDAC_RIGHT 29
#define GPOUT_SYS_SPI0_CLK 30
#define GPOUT_SYS_SPI0_FSS 31
#define GPOUT_SYS_SPI0_TXD 32
#define GPOUT_SYS_GMAC_PHYCLK 33
#define GPOUT_SYS_I2SRX_BCLK 34
#define GPOUT_SYS_I2SRX_LRCK 35
#define GPOUT_SYS_I2STX0_BCLK 36
#define GPOUT_SYS_I2STX0_LRCK 37
#define GPOUT_SYS_MCLK 38
#define GPOUT_SYS_TDM_CLK 39
#define GPOUT_SYS_TDM_SYNC 40
#define GPOUT_SYS_TDM_TXD 41
#define GPOUT_SYS_TRACE_DATA0 42
#define GPOUT_SYS_TRACE_DATA1 43
#define GPOUT_SYS_TRACE_DATA2 44
#define GPOUT_SYS_TRACE_DATA3 45
#define GPOUT_SYS_TRACE_REF 46
#define GPOUT_SYS_CAN1_STBY 47
#define GPOUT_SYS_CAN1_TST_NEXT_BIT 48
#define GPOUT_SYS_CAN1_TST_SAMPLE_POINT 49
#define GPOUT_SYS_CAN1_TXD 50
#define GPOUT_SYS_I2C1_CLK 51
#define GPOUT_SYS_I2C1_DATA 52
#define GPOUT_SYS_SDIO1_BACK_END_POWER 53
#define GPOUT_SYS_SDIO1_CARD_POWER_EN 54
#define GPOUT_SYS_SDIO1_CLK 55
#define GPOUT_SYS_SDIO1_CMD_OD_PULLUP_EN 56
#define GPOUT_SYS_SDIO1_CMD 57
#define GPOUT_SYS_SDIO1_DATA0 58
#define GPOUT_SYS_SDIO1_DATA1 59
#define GPOUT_SYS_SDIO1_DATA2 60
#define GPOUT_SYS_SDIO1_DATA3 61
#define GPOUT_SYS_SDIO1_DATA4 63
#define GPOUT_SYS_SDIO1_DATA5 63
#define GPOUT_SYS_SDIO1_DATA6 64
#define GPOUT_SYS_SDIO1_DATA7 65
#define GPOUT_SYS_SDIO1_RST 66
#define GPOUT_SYS_UART1_RTS 67
#define GPOUT_SYS_UART1_TX 68
#define GPOUT_SYS_I2STX1_SDO0 69
#define GPOUT_SYS_I2STX1_SDO1 70
#define GPOUT_SYS_I2STX1_SDO2 71
#define GPOUT_SYS_I2STX1_SDO3 72
#define GPOUT_SYS_SPI1_CLK 73
#define GPOUT_SYS_SPI1_FSS 74
#define GPOUT_SYS_SPI1_TXD 75
#define GPOUT_SYS_I2C2_CLK 76
#define GPOUT_SYS_I2C2_DATA 77
#define GPOUT_SYS_UART2_RTS 78
#define GPOUT_SYS_UART2_TX 79
#define GPOUT_SYS_SPI2_CLK 80
#define GPOUT_SYS_SPI2_FSS 81
#define GPOUT_SYS_SPI2_TXD 82
#define GPOUT_SYS_I2C3_CLK 83
#define GPOUT_SYS_I2C3_DATA 84
#define GPOUT_SYS_UART3_TX 85
#define GPOUT_SYS_SPI3_CLK 86
#define GPOUT_SYS_SPI3_FSS 87
#define GPOUT_SYS_SPI3_TXD 88
#define GPOUT_SYS_I2C4_CLK 89
#define GPOUT_SYS_I2C4_DATA 90
#define GPOUT_SYS_UART4_RTS 91
#define GPOUT_SYS_UART4_TX 92
#define GPOUT_SYS_SPI4_CLK 93
#define GPOUT_SYS_SPI4_FSS 94
#define GPOUT_SYS_SPI4_TXD 95
#define GPOUT_SYS_I2C5_CLK 96
#define GPOUT_SYS_I2C5_DATA 97
#define GPOUT_SYS_UART5_RTS 98
#define GPOUT_SYS_UART5_TX 99
#define GPOUT_SYS_SPI5_CLK 100
#define GPOUT_SYS_SPI5_FSS 101
#define GPOUT_SYS_SPI5_TXD 102
#define GPOUT_SYS_I2C6_CLK 103
#define GPOUT_SYS_I2C6_DATA 104
#define GPOUT_SYS_SPI6_CLK 105
#define GPOUT_SYS_SPI6_FSS 106
#define GPOUT_SYS_SPI6_TXD 107
/* aon_iomux dout */
#define GPOUT_AON_CLK_32K_OUT 2
#define GPOUT_AON_PTC0_PWM4 3
#define GPOUT_AON_PTC0_PWM5 4
#define GPOUT_AON_PTC0_PWM6 5
#define GPOUT_AON_PTC0_PWM7 6
#define GPOUT_AON_CLK_GCLK0 7
#define GPOUT_AON_CLK_GCLK1 8
#define GPOUT_AON_CLK_GCLK2 9
/* sys_iomux doen */
#define GPOEN_ENABLE 0
#define GPOEN_DISABLE 1
#define GPOEN_SYS_HDMI_CEC_SDA 2
#define GPOEN_SYS_HDMI_DDC_SCL 3
#define GPOEN_SYS_HDMI_DDC_SDA 4
#define GPOEN_SYS_I2C0_CLK 5
#define GPOEN_SYS_I2C0_DATA 6
#define GPOEN_SYS_HIFI4_JTAG_TDO 7
#define GPOEN_SYS_JTAG_TDO 8
#define GPOEN_SYS_PWM0_CHANNEL0 9
#define GPOEN_SYS_PWM0_CHANNEL1 10
#define GPOEN_SYS_PWM0_CHANNEL2 11
#define GPOEN_SYS_PWM0_CHANNEL3 12
#define GPOEN_SYS_SPI0_NSSPCTL 13
#define GPOEN_SYS_SPI0_NSSP 14
#define GPOEN_SYS_TDM_SYNC 15
#define GPOEN_SYS_TDM_TXD 16
#define GPOEN_SYS_I2C1_CLK 17
#define GPOEN_SYS_I2C1_DATA 18
#define GPOEN_SYS_SDIO1_CMD 19
#define GPOEN_SYS_SDIO1_DATA0 20
#define GPOEN_SYS_SDIO1_DATA1 21
#define GPOEN_SYS_SDIO1_DATA2 22
#define GPOEN_SYS_SDIO1_DATA3 23
#define GPOEN_SYS_SDIO1_DATA4 24
#define GPOEN_SYS_SDIO1_DATA5 25
#define GPOEN_SYS_SDIO1_DATA6 26
#define GPOEN_SYS_SDIO1_DATA7 27
#define GPOEN_SYS_SPI1_NSSPCTL 28
#define GPOEN_SYS_SPI1_NSSP 29
#define GPOEN_SYS_I2C2_CLK 30
#define GPOEN_SYS_I2C2_DATA 31
#define GPOEN_SYS_SPI2_NSSPCTL 32
#define GPOEN_SYS_SPI2_NSSP 33
#define GPOEN_SYS_I2C3_CLK 34
#define GPOEN_SYS_I2C3_DATA 35
#define GPOEN_SYS_SPI3_NSSPCTL 36
#define GPOEN_SYS_SPI3_NSSP 37
#define GPOEN_SYS_I2C4_CLK 38
#define GPOEN_SYS_I2C4_DATA 39
#define GPOEN_SYS_SPI4_NSSPCTL 40
#define GPOEN_SYS_SPI4_NSSP 41
#define GPOEN_SYS_I2C5_CLK 42
#define GPOEN_SYS_I2C5_DATA 43
#define GPOEN_SYS_SPI5_NSSPCTL 44
#define GPOEN_SYS_SPI5_NSSP 45
#define GPOEN_SYS_I2C6_CLK 46
#define GPOEN_SYS_I2C6_DATA 47
#define GPOEN_SYS_SPI6_NSSPCTL 48
#define GPOEN_SYS_SPI6_NSSP 49
/* aon_iomux doen */
#define GPOEN_AON_PTC0_OE_N_4 2
#define GPOEN_AON_PTC0_OE_N_5 3
#define GPOEN_AON_PTC0_OE_N_6 4
#define GPOEN_AON_PTC0_OE_N_7 5
/* sys_iomux gin */
#define GPI_NONE 255
#define GPI_SYS_WAVE511_UART_RX 0
#define GPI_SYS_CAN0_RXD 1
#define GPI_SYS_USB_OVERCURRENT 2
#define GPI_SYS_SPDIF 3
#define GPI_SYS_JTAG_RST 4
#define GPI_SYS_HDMI_CEC_SDA 5
#define GPI_SYS_HDMI_DDC_SCL 6
#define GPI_SYS_HDMI_DDC_SDA 7
#define GPI_SYS_HDMI_HPD 8
#define GPI_SYS_I2C0_CLK 9
#define GPI_SYS_I2C0_DATA 10
#define GPI_SYS_SDIO0_CD 11
#define GPI_SYS_SDIO0_INT 12
#define GPI_SYS_SDIO0_WP 13
#define GPI_SYS_UART0_RX 14
#define GPI_SYS_HIFI4_JTAG_TCK 15
#define GPI_SYS_HIFI4_JTAG_TDI 16
#define GPI_SYS_HIFI4_JTAG_TMS 17
#define GPI_SYS_HIFI4_JTAG_RST 18
#define GPI_SYS_JTAG_TDI 19
#define GPI_SYS_JTAG_TMS 20
#define GPI_SYS_PDM_DMIC0 21
#define GPI_SYS_PDM_DMIC1 22
#define GPI_SYS_I2SRX_SDIN0 23
#define GPI_SYS_I2SRX_SDIN1 24
#define GPI_SYS_I2SRX_SDIN2 25
#define GPI_SYS_SPI0_CLK 26
#define GPI_SYS_SPI0_FSS 27
#define GPI_SYS_SPI0_RXD 28
#define GPI_SYS_JTAG_TCK 29
#define GPI_SYS_MCLK_EXT 30
#define GPI_SYS_I2SRX_BCLK 31
#define GPI_SYS_I2SRX_LRCK 32
#define GPI_SYS_I2STX1_BCLK 33
#define GPI_SYS_I2STX1_LRCK 34
#define GPI_SYS_TDM_CLK 35
#define GPI_SYS_TDM_RXD 36
#define GPI_SYS_TDM_SYNC 37
#define GPI_SYS_CAN1_RXD 38
#define GPI_SYS_I2C1_CLK 39
#define GPI_SYS_I2C1_DATA 40
#define GPI_SYS_SDIO1_CD 41
#define GPI_SYS_SDIO1_INT 42
#define GPI_SYS_SDIO1_WP 43
#define GPI_SYS_SDIO1_CMD 44
#define GPI_SYS_SDIO1_DATA0 45
#define GPI_SYS_SDIO1_DATA1 46
#define GPI_SYS_SDIO1_DATA2 47
#define GPI_SYS_SDIO1_DATA3 48
#define GPI_SYS_SDIO1_DATA4 49
#define GPI_SYS_SDIO1_DATA5 50
#define GPI_SYS_SDIO1_DATA6 51
#define GPI_SYS_SDIO1_DATA7 52
#define GPI_SYS_SDIO1_STRB 53
#define GPI_SYS_UART1_CTS 54
#define GPI_SYS_UART1_RX 55
#define GPI_SYS_SPI1_CLK 56
#define GPI_SYS_SPI1_FSS 57
#define GPI_SYS_SPI1_RXD 58
#define GPI_SYS_I2C2_CLK 59
#define GPI_SYS_I2C2_DATA 60
#define GPI_SYS_UART2_CTS 61
#define GPI_SYS_UART2_RX 62
#define GPI_SYS_SPI2_CLK 63
#define GPI_SYS_SPI2_FSS 64
#define GPI_SYS_SPI2_RXD 65
#define GPI_SYS_I2C3_CLK 66
#define GPI_SYS_I2C3_DATA 67
#define GPI_SYS_UART3_RX 68
#define GPI_SYS_SPI3_CLK 69
#define GPI_SYS_SPI3_FSS 70
#define GPI_SYS_SPI3_RXD 71
#define GPI_SYS_I2C4_CLK 72
#define GPI_SYS_I2C4_DATA 73
#define GPI_SYS_UART4_CTS 74
#define GPI_SYS_UART4_RX 75
#define GPI_SYS_SPI4_CLK 76
#define GPI_SYS_SPI4_FSS 77
#define GPI_SYS_SPI4_RXD 78
#define GPI_SYS_I2C5_CLK 79
#define GPI_SYS_I2C5_DATA 80
#define GPI_SYS_UART5_CTS 81
#define GPI_SYS_UART5_RX 82
#define GPI_SYS_SPI5_CLK 83
#define GPI_SYS_SPI5_FSS 84
#define GPI_SYS_SPI5_RXD 85
#define GPI_SYS_I2C6_CLK 86
#define GPI_SYS_I2C6_DATA 87
#define GPI_SYS_SPI6_CLK 88
#define GPI_SYS_SPI6_FSS 89
#define GPI_SYS_SPI6_RXD 90
/* aon_iomux gin */
#define GPI_AON_PMU_GPIO_WAKEUP_0 0
#define GPI_AON_PMU_GPIO_WAKEUP_1 1
#define GPI_AON_PMU_GPIO_WAKEUP_2 2
#define GPI_AON_PMU_GPIO_WAKEUP_3 3
#endif

26
sys/external/gpl2/dts/dist/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dts vendored Normal file
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// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
* Copyright (C) 2022 StarFive Technology Co., Ltd.
* Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
*/
/dts-v1/;
#include "jh7110-starfive-visionfive-2.dtsi"
/ {
model = "StarFive VisionFive 2 v1.2A";
compatible = "starfive,visionfive-2-v1.2a", "starfive,jh7110";
};
&gmac1 {
phy-mode = "rmii";
assigned-clocks = <&syscrg JH7110_SYSCLK_GMAC1_TX>,
<&syscrg JH7110_SYSCLK_GMAC1_RX>;
assigned-clock-parents = <&syscrg JH7110_SYSCLK_GMAC1_RMII_RTX>,
<&syscrg JH7110_SYSCLK_GMAC1_RMII_RTX>;
};
&phy0 {
rx-internal-delay-ps = <1900>;
tx-internal-delay-ps = <1350>;
};

44
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// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
* Copyright (C) 2022 StarFive Technology Co., Ltd.
* Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
*/
/dts-v1/;
#include "jh7110-starfive-visionfive-2.dtsi"
/ {
model = "StarFive VisionFive 2 v1.3B";
compatible = "starfive,visionfive-2-v1.3b", "starfive,jh7110";
};
&gmac0 {
starfive,tx-use-rgmii-clk;
assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
};
&gmac1 {
starfive,tx-use-rgmii-clk;
assigned-clocks = <&syscrg JH7110_SYSCLK_GMAC1_TX>;
assigned-clock-parents = <&syscrg JH7110_SYSCLK_GMAC1_RMII_RTX>;
};
&phy0 {
motorcomm,tx-clk-adj-enabled;
motorcomm,tx-clk-100-inverted;
motorcomm,tx-clk-1000-inverted;
motorcomm,rx-clk-drv-microamp = <3970>;
motorcomm,rx-data-drv-microamp = <2910>;
rx-internal-delay-ps = <1500>;
tx-internal-delay-ps = <1500>;
};
&phy1 {
motorcomm,tx-clk-adj-enabled;
motorcomm,tx-clk-100-inverted;
motorcomm,rx-clk-drv-microamp = <3970>;
motorcomm,rx-data-drv-microamp = <2910>;
rx-internal-delay-ps = <300>;
tx-internal-delay-ps = <0>;
};

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// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
* Copyright (C) 2022 StarFive Technology Co., Ltd.
* Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
*/
/dts-v1/;
#include "jh7110.dtsi"
#include "jh7110-pinfunc.h"
#include <dt-bindings/gpio/gpio.h>
/ {
aliases {
ethernet0 = &gmac0;
ethernet1 = &gmac1;
i2c0 = &i2c0;
i2c2 = &i2c2;
i2c5 = &i2c5;
i2c6 = &i2c6;
mmc0 = &mmc0;
mmc1 = &mmc1;
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
cpus {
timebase-frequency = <4000000>;
};
memory@40000000 {
device_type = "memory";
reg = <0x0 0x40000000 0x1 0x0>;
};
gpio-restart {
compatible = "gpio-restart";
gpios = <&sysgpio 35 GPIO_ACTIVE_HIGH>;
priority = <224>;
};
pwmdac_codec: pwmdac-codec {
compatible = "linux,spdif-dit";
#sound-dai-cells = <0>;
};
sound-pwmdac {
compatible = "simple-audio-card";
simple-audio-card,name = "StarFive-PWMDAC-Sound-Card";
#address-cells = <1>;
#size-cells = <0>;
simple-audio-card,dai-link@0 {
reg = <0>;
format = "left_j";
bitclock-master = <&sndcpu0>;
frame-master = <&sndcpu0>;
sndcpu0: cpu {
sound-dai = <&pwmdac>;
};
codec {
sound-dai = <&pwmdac_codec>;
};
};
};
};
&dvp_clk {
clock-frequency = <74250000>;
};
&gmac0_rgmii_rxin {
clock-frequency = <125000000>;
};
&gmac0_rmii_refin {
clock-frequency = <50000000>;
};
&gmac1_rgmii_rxin {
clock-frequency = <125000000>;
};
&gmac1_rmii_refin {
clock-frequency = <50000000>;
};
&hdmitx0_pixelclk {
clock-frequency = <297000000>;
};
&i2srx_bclk_ext {
clock-frequency = <12288000>;
};
&i2srx_lrck_ext {
clock-frequency = <192000>;
};
&i2stx_bclk_ext {
clock-frequency = <12288000>;
};
&i2stx_lrck_ext {
clock-frequency = <192000>;
};
&mclk_ext {
clock-frequency = <12288000>;
};
&osc {
clock-frequency = <24000000>;
};
&rtc_osc {
clock-frequency = <32768>;
};
&tdm_ext {
clock-frequency = <49152000>;
};
&gmac0 {
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
phy0: ethernet-phy@0 {
reg = <0>;
};
};
};
&gmac1 {
phy-handle = <&phy1>;
phy-mode = "rgmii-id";
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
phy1: ethernet-phy@1 {
reg = <0>;
};
};
};
&i2c0 {
clock-frequency = <100000>;
i2c-sda-hold-time-ns = <300>;
i2c-sda-falling-time-ns = <510>;
i2c-scl-falling-time-ns = <510>;
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
status = "okay";
};
&i2c2 {
clock-frequency = <100000>;
i2c-sda-hold-time-ns = <300>;
i2c-sda-falling-time-ns = <510>;
i2c-scl-falling-time-ns = <510>;
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins>;
status = "okay";
};
&i2c5 {
clock-frequency = <100000>;
i2c-sda-hold-time-ns = <300>;
i2c-sda-falling-time-ns = <510>;
i2c-scl-falling-time-ns = <510>;
pinctrl-names = "default";
pinctrl-0 = <&i2c5_pins>;
status = "okay";
axp15060: pmic@36 {
compatible = "x-powers,axp15060";
reg = <0x36>;
interrupts = <0>;
interrupt-controller;
#interrupt-cells = <1>;
regulators {
vcc_3v3: dcdc1 {
regulator-boot-on;
regulator-always-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc_3v3";
};
vdd_cpu: dcdc2 {
regulator-always-on;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1540000>;
regulator-name = "vdd-cpu";
};
emmc_vdd: aldo4 {
regulator-boot-on;
regulator-always-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "emmc_vdd";
};
};
};
};
&i2c6 {
clock-frequency = <100000>;
i2c-sda-hold-time-ns = <300>;
i2c-sda-falling-time-ns = <510>;
i2c-scl-falling-time-ns = <510>;
pinctrl-names = "default";
pinctrl-0 = <&i2c6_pins>;
status = "okay";
};
&i2srx {
pinctrl-names = "default";
pinctrl-0 = <&i2srx_pins>;
status = "okay";
};
&i2stx0 {
pinctrl-names = "default";
pinctrl-0 = <&mclk_ext_pins>;
status = "okay";
};
&i2stx1 {
pinctrl-names = "default";
pinctrl-0 = <&i2stx1_pins>;
status = "okay";
};
&mmc0 {
max-frequency = <100000000>;
assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>;
assigned-clock-rates = <50000000>;
bus-width = <8>;
cap-mmc-highspeed;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
non-removable;
cap-mmc-hw-reset;
post-power-on-delay-ms = <200>;
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
vmmc-supply = <&vcc_3v3>;
vqmmc-supply = <&emmc_vdd>;
status = "okay";
};
&mmc1 {
max-frequency = <100000000>;
assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>;
assigned-clock-rates = <50000000>;
bus-width = <4>;
no-sdio;
no-mmc;
broken-cd;
cap-sd-highspeed;
post-power-on-delay-ms = <200>;
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins>;
status = "okay";
};
&pwmdac {
pinctrl-names = "default";
pinctrl-0 = <&pwmdac_pins>;
status = "okay";
};
&qspi {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
nor_flash: flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
cdns,read-delay = <5>;
spi-max-frequency = <12000000>;
cdns,tshsl-ns = <1>;
cdns,tsd2d-ns = <1>;
cdns,tchsh-ns = <1>;
cdns,tslch-ns = <1>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
spl@0 {
reg = <0x0 0x80000>;
};
uboot-env@f0000 {
reg = <0xf0000 0x10000>;
};
uboot@100000 {
reg = <0x100000 0x400000>;
};
reserved-data@600000 {
reg = <0x600000 0xa00000>;
};
};
};
};
&pwm {
pinctrl-names = "default";
pinctrl-0 = <&pwm_pins>;
status = "okay";
};
&spi0 {
pinctrl-names = "default";
pinctrl-0 = <&spi0_pins>;
status = "okay";
spi_dev0: spi@0 {
compatible = "rohm,dh2228fv";
reg = <0>;
spi-max-frequency = <10000000>;
};
};
&sysgpio {
i2c0_pins: i2c0-0 {
i2c-pins {
pinmux = <GPIOMUX(57, GPOUT_LOW,
GPOEN_SYS_I2C0_CLK,
GPI_SYS_I2C0_CLK)>,
<GPIOMUX(58, GPOUT_LOW,
GPOEN_SYS_I2C0_DATA,
GPI_SYS_I2C0_DATA)>;
bias-disable; /* external pull-up */
input-enable;
input-schmitt-enable;
};
};
i2c2_pins: i2c2-0 {
i2c-pins {
pinmux = <GPIOMUX(3, GPOUT_LOW,
GPOEN_SYS_I2C2_CLK,
GPI_SYS_I2C2_CLK)>,
<GPIOMUX(2, GPOUT_LOW,
GPOEN_SYS_I2C2_DATA,
GPI_SYS_I2C2_DATA)>;
bias-disable; /* external pull-up */
input-enable;
input-schmitt-enable;
};
};
i2c5_pins: i2c5-0 {
i2c-pins {
pinmux = <GPIOMUX(19, GPOUT_LOW,
GPOEN_SYS_I2C5_CLK,
GPI_SYS_I2C5_CLK)>,
<GPIOMUX(20, GPOUT_LOW,
GPOEN_SYS_I2C5_DATA,
GPI_SYS_I2C5_DATA)>;
bias-disable; /* external pull-up */
input-enable;
input-schmitt-enable;
};
};
i2c6_pins: i2c6-0 {
i2c-pins {
pinmux = <GPIOMUX(16, GPOUT_LOW,
GPOEN_SYS_I2C6_CLK,
GPI_SYS_I2C6_CLK)>,
<GPIOMUX(17, GPOUT_LOW,
GPOEN_SYS_I2C6_DATA,
GPI_SYS_I2C6_DATA)>;
bias-disable; /* external pull-up */
input-enable;
input-schmitt-enable;
};
};
i2srx_pins: i2srx-0 {
clk-sd-pins {
pinmux = <GPIOMUX(38, GPOUT_LOW,
GPOEN_DISABLE,
GPI_SYS_I2SRX_BCLK)>,
<GPIOMUX(63, GPOUT_LOW,
GPOEN_DISABLE,
GPI_SYS_I2SRX_LRCK)>,
<GPIOMUX(38, GPOUT_LOW,
GPOEN_DISABLE,
GPI_SYS_I2STX1_BCLK)>,
<GPIOMUX(63, GPOUT_LOW,
GPOEN_DISABLE,
GPI_SYS_I2STX1_LRCK)>,
<GPIOMUX(61, GPOUT_LOW,
GPOEN_DISABLE,
GPI_SYS_I2SRX_SDIN0)>;
input-enable;
};
};
i2stx1_pins: i2stx1-0 {
sd-pins {
pinmux = <GPIOMUX(44, GPOUT_SYS_I2STX1_SDO0,
GPOEN_ENABLE,
GPI_NONE)>;
bias-disable;
input-disable;
};
};
mclk_ext_pins: mclk-ext-0 {
mclk-ext-pins {
pinmux = <GPIOMUX(4, GPOUT_LOW,
GPOEN_DISABLE,
GPI_SYS_MCLK_EXT)>;
input-enable;
};
};
mmc0_pins: mmc0-0 {
rst-pins {
pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST,
GPOEN_ENABLE,
GPI_NONE)>;
bias-pull-up;
drive-strength = <12>;
input-disable;
input-schmitt-disable;
slew-rate = <0>;
};
mmc-pins {
pinmux = <PINMUX(64, 0)>,
<PINMUX(65, 0)>,
<PINMUX(66, 0)>,
<PINMUX(67, 0)>,
<PINMUX(68, 0)>,
<PINMUX(69, 0)>,
<PINMUX(70, 0)>,
<PINMUX(71, 0)>,
<PINMUX(72, 0)>,
<PINMUX(73, 0)>;
bias-pull-up;
drive-strength = <12>;
input-enable;
};
};
mmc1_pins: mmc1-0 {
clk-pins {
pinmux = <GPIOMUX(10, GPOUT_SYS_SDIO1_CLK,
GPOEN_ENABLE,
GPI_NONE)>;
bias-pull-up;
drive-strength = <12>;
input-disable;
input-schmitt-disable;
slew-rate = <0>;
};
mmc-pins {
pinmux = <GPIOMUX(9, GPOUT_SYS_SDIO1_CMD,
GPOEN_SYS_SDIO1_CMD,
GPI_SYS_SDIO1_CMD)>,
<GPIOMUX(11, GPOUT_SYS_SDIO1_DATA0,
GPOEN_SYS_SDIO1_DATA0,
GPI_SYS_SDIO1_DATA0)>,
<GPIOMUX(12, GPOUT_SYS_SDIO1_DATA1,
GPOEN_SYS_SDIO1_DATA1,
GPI_SYS_SDIO1_DATA1)>,
<GPIOMUX(7, GPOUT_SYS_SDIO1_DATA2,
GPOEN_SYS_SDIO1_DATA2,
GPI_SYS_SDIO1_DATA2)>,
<GPIOMUX(8, GPOUT_SYS_SDIO1_DATA3,
GPOEN_SYS_SDIO1_DATA3,
GPI_SYS_SDIO1_DATA3)>;
bias-pull-up;
drive-strength = <12>;
input-enable;
input-schmitt-enable;
slew-rate = <0>;
};
};
pwmdac_pins: pwmdac-0 {
pwmdac-pins {
pinmux = <GPIOMUX(33, GPOUT_SYS_PWMDAC_LEFT,
GPOEN_ENABLE,
GPI_NONE)>,
<GPIOMUX(34, GPOUT_SYS_PWMDAC_RIGHT,
GPOEN_ENABLE,
GPI_NONE)>;
bias-disable;
drive-strength = <2>;
input-disable;
input-schmitt-disable;
slew-rate = <0>;
};
};
pwm_pins: pwm-0 {
pwm-pins {
pinmux = <GPIOMUX(46, GPOUT_SYS_PWM_CHANNEL0,
GPOEN_SYS_PWM0_CHANNEL0,
GPI_NONE)>,
<GPIOMUX(59, GPOUT_SYS_PWM_CHANNEL1,
GPOEN_SYS_PWM0_CHANNEL1,
GPI_NONE)>;
bias-disable;
drive-strength = <12>;
input-disable;
input-schmitt-disable;
slew-rate = <0>;
};
};
spi0_pins: spi0-0 {
mosi-pins {
pinmux = <GPIOMUX(52, GPOUT_SYS_SPI0_TXD,
GPOEN_ENABLE,
GPI_NONE)>;
bias-disable;
input-disable;
input-schmitt-disable;
};
miso-pins {
pinmux = <GPIOMUX(53, GPOUT_LOW,
GPOEN_DISABLE,
GPI_SYS_SPI0_RXD)>;
bias-pull-up;
input-enable;
input-schmitt-enable;
};
sck-pins {
pinmux = <GPIOMUX(48, GPOUT_SYS_SPI0_CLK,
GPOEN_ENABLE,
GPI_SYS_SPI0_CLK)>;
bias-disable;
input-disable;
input-schmitt-disable;
};
ss-pins {
pinmux = <GPIOMUX(49, GPOUT_SYS_SPI0_FSS,
GPOEN_ENABLE,
GPI_SYS_SPI0_FSS)>;
bias-disable;
input-disable;
input-schmitt-disable;
};
};
tdm_pins: tdm-0 {
tx-pins {
pinmux = <GPIOMUX(44, GPOUT_SYS_TDM_TXD,
GPOEN_ENABLE,
GPI_NONE)>;
bias-pull-up;
drive-strength = <2>;
input-disable;
input-schmitt-disable;
slew-rate = <0>;
};
rx-pins {
pinmux = <GPIOMUX(61, GPOUT_HIGH,
GPOEN_DISABLE,
GPI_SYS_TDM_RXD)>;
input-enable;
};
sync-pins {
pinmux = <GPIOMUX(63, GPOUT_HIGH,
GPOEN_DISABLE,
GPI_SYS_TDM_SYNC)>;
input-enable;
};
pcmclk-pins {
pinmux = <GPIOMUX(38, GPOUT_HIGH,
GPOEN_DISABLE,
GPI_SYS_TDM_CLK)>;
input-enable;
};
};
uart0_pins: uart0-0 {
tx-pins {
pinmux = <GPIOMUX(5, GPOUT_SYS_UART0_TX,
GPOEN_ENABLE,
GPI_NONE)>;
bias-disable;
drive-strength = <12>;
input-disable;
input-schmitt-disable;
slew-rate = <0>;
};
rx-pins {
pinmux = <GPIOMUX(6, GPOUT_LOW,
GPOEN_DISABLE,
GPI_SYS_UART0_RX)>;
bias-disable; /* external pull-up */
drive-strength = <2>;
input-enable;
input-schmitt-enable;
slew-rate = <0>;
};
};
};
&tdm {
pinctrl-names = "default";
pinctrl-0 = <&tdm_pins>;
status = "okay";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
status = "okay";
};
&usb0 {
dr_mode = "peripheral";
status = "okay";
};
&U74_1 {
cpu-supply = <&vdd_cpu>;
};
&U74_2 {
cpu-supply = <&vdd_cpu>;
};
&U74_3 {
cpu-supply = <&vdd_cpu>;
};
&U74_4 {
cpu-supply = <&vdd_cpu>;
};

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/* SPDX-License-Identifier: GPL-2.0 OR MIT */
/*
* Copyright 2022 Emil Renner Berthing <kernel@esmil.dk>
* Copyright 2022 StarFive Technology Co., Ltd.
*/
#ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__
#define __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__
/* PLL clocks */
#define JH7110_PLLCLK_PLL0_OUT 0
#define JH7110_PLLCLK_PLL1_OUT 1
#define JH7110_PLLCLK_PLL2_OUT 2
#define JH7110_PLLCLK_END 3
/* SYSCRG clocks */
#define JH7110_SYSCLK_CPU_ROOT 0
#define JH7110_SYSCLK_CPU_CORE 1
#define JH7110_SYSCLK_CPU_BUS 2
#define JH7110_SYSCLK_GPU_ROOT 3
#define JH7110_SYSCLK_PERH_ROOT 4
#define JH7110_SYSCLK_BUS_ROOT 5
#define JH7110_SYSCLK_NOCSTG_BUS 6
#define JH7110_SYSCLK_AXI_CFG0 7
#define JH7110_SYSCLK_STG_AXIAHB 8
#define JH7110_SYSCLK_AHB0 9
#define JH7110_SYSCLK_AHB1 10
#define JH7110_SYSCLK_APB_BUS 11
#define JH7110_SYSCLK_APB0 12
#define JH7110_SYSCLK_PLL0_DIV2 13
#define JH7110_SYSCLK_PLL1_DIV2 14
#define JH7110_SYSCLK_PLL2_DIV2 15
#define JH7110_SYSCLK_AUDIO_ROOT 16
#define JH7110_SYSCLK_MCLK_INNER 17
#define JH7110_SYSCLK_MCLK 18
#define JH7110_SYSCLK_MCLK_OUT 19
#define JH7110_SYSCLK_ISP_2X 20
#define JH7110_SYSCLK_ISP_AXI 21
#define JH7110_SYSCLK_GCLK0 22
#define JH7110_SYSCLK_GCLK1 23
#define JH7110_SYSCLK_GCLK2 24
#define JH7110_SYSCLK_CORE 25
#define JH7110_SYSCLK_CORE1 26
#define JH7110_SYSCLK_CORE2 27
#define JH7110_SYSCLK_CORE3 28
#define JH7110_SYSCLK_CORE4 29
#define JH7110_SYSCLK_DEBUG 30
#define JH7110_SYSCLK_RTC_TOGGLE 31
#define JH7110_SYSCLK_TRACE0 32
#define JH7110_SYSCLK_TRACE1 33
#define JH7110_SYSCLK_TRACE2 34
#define JH7110_SYSCLK_TRACE3 35
#define JH7110_SYSCLK_TRACE4 36
#define JH7110_SYSCLK_TRACE_COM 37
#define JH7110_SYSCLK_NOC_BUS_CPU_AXI 38
#define JH7110_SYSCLK_NOC_BUS_AXICFG0_AXI 39
#define JH7110_SYSCLK_OSC_DIV2 40
#define JH7110_SYSCLK_PLL1_DIV4 41
#define JH7110_SYSCLK_PLL1_DIV8 42
#define JH7110_SYSCLK_DDR_BUS 43
#define JH7110_SYSCLK_DDR_AXI 44
#define JH7110_SYSCLK_GPU_CORE 45
#define JH7110_SYSCLK_GPU_CORE_CLK 46
#define JH7110_SYSCLK_GPU_SYS_CLK 47
#define JH7110_SYSCLK_GPU_APB 48
#define JH7110_SYSCLK_GPU_RTC_TOGGLE 49
#define JH7110_SYSCLK_NOC_BUS_GPU_AXI 50
#define JH7110_SYSCLK_ISP_TOP_CORE 51
#define JH7110_SYSCLK_ISP_TOP_AXI 52
#define JH7110_SYSCLK_NOC_BUS_ISP_AXI 53
#define JH7110_SYSCLK_HIFI4_CORE 54
#define JH7110_SYSCLK_HIFI4_AXI 55
#define JH7110_SYSCLK_AXI_CFG1_MAIN 56
#define JH7110_SYSCLK_AXI_CFG1_AHB 57
#define JH7110_SYSCLK_VOUT_SRC 58
#define JH7110_SYSCLK_VOUT_AXI 59
#define JH7110_SYSCLK_NOC_BUS_DISP_AXI 60
#define JH7110_SYSCLK_VOUT_TOP_AHB 61
#define JH7110_SYSCLK_VOUT_TOP_AXI 62
#define JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK 63
#define JH7110_SYSCLK_VOUT_TOP_MIPIPHY_REF 64
#define JH7110_SYSCLK_JPEGC_AXI 65
#define JH7110_SYSCLK_CODAJ12_AXI 66
#define JH7110_SYSCLK_CODAJ12_CORE 67
#define JH7110_SYSCLK_CODAJ12_APB 68
#define JH7110_SYSCLK_VDEC_AXI 69
#define JH7110_SYSCLK_WAVE511_AXI 70
#define JH7110_SYSCLK_WAVE511_BPU 71
#define JH7110_SYSCLK_WAVE511_VCE 72
#define JH7110_SYSCLK_WAVE511_APB 73
#define JH7110_SYSCLK_VDEC_JPG 74
#define JH7110_SYSCLK_VDEC_MAIN 75
#define JH7110_SYSCLK_NOC_BUS_VDEC_AXI 76
#define JH7110_SYSCLK_VENC_AXI 77
#define JH7110_SYSCLK_WAVE420L_AXI 78
#define JH7110_SYSCLK_WAVE420L_BPU 79
#define JH7110_SYSCLK_WAVE420L_VCE 80
#define JH7110_SYSCLK_WAVE420L_APB 81
#define JH7110_SYSCLK_NOC_BUS_VENC_AXI 82
#define JH7110_SYSCLK_AXI_CFG0_MAIN_DIV 83
#define JH7110_SYSCLK_AXI_CFG0_MAIN 84
#define JH7110_SYSCLK_AXI_CFG0_HIFI4 85
#define JH7110_SYSCLK_AXIMEM2_AXI 86
#define JH7110_SYSCLK_QSPI_AHB 87
#define JH7110_SYSCLK_QSPI_APB 88
#define JH7110_SYSCLK_QSPI_REF_SRC 89
#define JH7110_SYSCLK_QSPI_REF 90
#define JH7110_SYSCLK_SDIO0_AHB 91
#define JH7110_SYSCLK_SDIO1_AHB 92
#define JH7110_SYSCLK_SDIO0_SDCARD 93
#define JH7110_SYSCLK_SDIO1_SDCARD 94
#define JH7110_SYSCLK_USB_125M 95
#define JH7110_SYSCLK_NOC_BUS_STG_AXI 96
#define JH7110_SYSCLK_GMAC1_AHB 97
#define JH7110_SYSCLK_GMAC1_AXI 98
#define JH7110_SYSCLK_GMAC_SRC 99
#define JH7110_SYSCLK_GMAC1_GTXCLK 100
#define JH7110_SYSCLK_GMAC1_RMII_RTX 101
#define JH7110_SYSCLK_GMAC1_PTP 102
#define JH7110_SYSCLK_GMAC1_RX 103
#define JH7110_SYSCLK_GMAC1_RX_INV 104
#define JH7110_SYSCLK_GMAC1_TX 105
#define JH7110_SYSCLK_GMAC1_TX_INV 106
#define JH7110_SYSCLK_GMAC1_GTXC 107
#define JH7110_SYSCLK_GMAC0_GTXCLK 108
#define JH7110_SYSCLK_GMAC0_PTP 109
#define JH7110_SYSCLK_GMAC_PHY 110
#define JH7110_SYSCLK_GMAC0_GTXC 111
#define JH7110_SYSCLK_IOMUX_APB 112
#define JH7110_SYSCLK_MAILBOX_APB 113
#define JH7110_SYSCLK_INT_CTRL_APB 114
#define JH7110_SYSCLK_CAN0_APB 115
#define JH7110_SYSCLK_CAN0_TIMER 116
#define JH7110_SYSCLK_CAN0_CAN 117
#define JH7110_SYSCLK_CAN1_APB 118
#define JH7110_SYSCLK_CAN1_TIMER 119
#define JH7110_SYSCLK_CAN1_CAN 120
#define JH7110_SYSCLK_PWM_APB 121
#define JH7110_SYSCLK_WDT_APB 122
#define JH7110_SYSCLK_WDT_CORE 123
#define JH7110_SYSCLK_TIMER_APB 124
#define JH7110_SYSCLK_TIMER0 125
#define JH7110_SYSCLK_TIMER1 126
#define JH7110_SYSCLK_TIMER2 127
#define JH7110_SYSCLK_TIMER3 128
#define JH7110_SYSCLK_TEMP_APB 129
#define JH7110_SYSCLK_TEMP_CORE 130
#define JH7110_SYSCLK_SPI0_APB 131
#define JH7110_SYSCLK_SPI1_APB 132
#define JH7110_SYSCLK_SPI2_APB 133
#define JH7110_SYSCLK_SPI3_APB 134
#define JH7110_SYSCLK_SPI4_APB 135
#define JH7110_SYSCLK_SPI5_APB 136
#define JH7110_SYSCLK_SPI6_APB 137
#define JH7110_SYSCLK_I2C0_APB 138
#define JH7110_SYSCLK_I2C1_APB 139
#define JH7110_SYSCLK_I2C2_APB 140
#define JH7110_SYSCLK_I2C3_APB 141
#define JH7110_SYSCLK_I2C4_APB 142
#define JH7110_SYSCLK_I2C5_APB 143
#define JH7110_SYSCLK_I2C6_APB 144
#define JH7110_SYSCLK_UART0_APB 145
#define JH7110_SYSCLK_UART0_CORE 146
#define JH7110_SYSCLK_UART1_APB 147
#define JH7110_SYSCLK_UART1_CORE 148
#define JH7110_SYSCLK_UART2_APB 149
#define JH7110_SYSCLK_UART2_CORE 150
#define JH7110_SYSCLK_UART3_APB 151
#define JH7110_SYSCLK_UART3_CORE 152
#define JH7110_SYSCLK_UART4_APB 153
#define JH7110_SYSCLK_UART4_CORE 154
#define JH7110_SYSCLK_UART5_APB 155
#define JH7110_SYSCLK_UART5_CORE 156
#define JH7110_SYSCLK_PWMDAC_APB 157
#define JH7110_SYSCLK_PWMDAC_CORE 158
#define JH7110_SYSCLK_SPDIF_APB 159
#define JH7110_SYSCLK_SPDIF_CORE 160
#define JH7110_SYSCLK_I2STX0_APB 161
#define JH7110_SYSCLK_I2STX0_BCLK_MST 162
#define JH7110_SYSCLK_I2STX0_BCLK_MST_INV 163
#define JH7110_SYSCLK_I2STX0_LRCK_MST 164
#define JH7110_SYSCLK_I2STX0_BCLK 165
#define JH7110_SYSCLK_I2STX0_BCLK_INV 166
#define JH7110_SYSCLK_I2STX0_LRCK 167
#define JH7110_SYSCLK_I2STX1_APB 168
#define JH7110_SYSCLK_I2STX1_BCLK_MST 169
#define JH7110_SYSCLK_I2STX1_BCLK_MST_INV 170
#define JH7110_SYSCLK_I2STX1_LRCK_MST 171
#define JH7110_SYSCLK_I2STX1_BCLK 172
#define JH7110_SYSCLK_I2STX1_BCLK_INV 173
#define JH7110_SYSCLK_I2STX1_LRCK 174
#define JH7110_SYSCLK_I2SRX_APB 175
#define JH7110_SYSCLK_I2SRX_BCLK_MST 176
#define JH7110_SYSCLK_I2SRX_BCLK_MST_INV 177
#define JH7110_SYSCLK_I2SRX_LRCK_MST 178
#define JH7110_SYSCLK_I2SRX_BCLK 179
#define JH7110_SYSCLK_I2SRX_BCLK_INV 180
#define JH7110_SYSCLK_I2SRX_LRCK 181
#define JH7110_SYSCLK_PDM_DMIC 182
#define JH7110_SYSCLK_PDM_APB 183
#define JH7110_SYSCLK_TDM_AHB 184
#define JH7110_SYSCLK_TDM_APB 185
#define JH7110_SYSCLK_TDM_INTERNAL 186
#define JH7110_SYSCLK_TDM_TDM 187
#define JH7110_SYSCLK_TDM_TDM_INV 188
#define JH7110_SYSCLK_JTAG_CERTIFICATION_TRNG 189
#define JH7110_SYSCLK_END 190
/* AONCRG clocks */
#define JH7110_AONCLK_OSC_DIV4 0
#define JH7110_AONCLK_APB_FUNC 1
#define JH7110_AONCLK_GMAC0_AHB 2
#define JH7110_AONCLK_GMAC0_AXI 3
#define JH7110_AONCLK_GMAC0_RMII_RTX 4
#define JH7110_AONCLK_GMAC0_TX 5
#define JH7110_AONCLK_GMAC0_TX_INV 6
#define JH7110_AONCLK_GMAC0_RX 7
#define JH7110_AONCLK_GMAC0_RX_INV 8
#define JH7110_AONCLK_OTPC_APB 9
#define JH7110_AONCLK_RTC_APB 10
#define JH7110_AONCLK_RTC_INTERNAL 11
#define JH7110_AONCLK_RTC_32K 12
#define JH7110_AONCLK_RTC_CAL 13
#define JH7110_AONCLK_END 14
/* STGCRG clocks */
#define JH7110_STGCLK_HIFI4_CLK_CORE 0
#define JH7110_STGCLK_USB0_APB 1
#define JH7110_STGCLK_USB0_UTMI_APB 2
#define JH7110_STGCLK_USB0_AXI 3
#define JH7110_STGCLK_USB0_LPM 4
#define JH7110_STGCLK_USB0_STB 5
#define JH7110_STGCLK_USB0_APP_125 6
#define JH7110_STGCLK_USB0_REFCLK 7
#define JH7110_STGCLK_PCIE0_AXI_MST0 8
#define JH7110_STGCLK_PCIE0_APB 9
#define JH7110_STGCLK_PCIE0_TL 10
#define JH7110_STGCLK_PCIE1_AXI_MST0 11
#define JH7110_STGCLK_PCIE1_APB 12
#define JH7110_STGCLK_PCIE1_TL 13
#define JH7110_STGCLK_PCIE_SLV_MAIN 14
#define JH7110_STGCLK_SEC_AHB 15
#define JH7110_STGCLK_SEC_MISC_AHB 16
#define JH7110_STGCLK_GRP0_MAIN 17
#define JH7110_STGCLK_GRP0_BUS 18
#define JH7110_STGCLK_GRP0_STG 19
#define JH7110_STGCLK_GRP1_MAIN 20
#define JH7110_STGCLK_GRP1_BUS 21
#define JH7110_STGCLK_GRP1_STG 22
#define JH7110_STGCLK_GRP1_HIFI 23
#define JH7110_STGCLK_E2_RTC 24
#define JH7110_STGCLK_E2_CORE 25
#define JH7110_STGCLK_E2_DBG 26
#define JH7110_STGCLK_DMA1P_AXI 27
#define JH7110_STGCLK_DMA1P_AHB 28
#define JH7110_STGCLK_END 29
/* ISPCRG clocks */
#define JH7110_ISPCLK_DOM4_APB_FUNC 0
#define JH7110_ISPCLK_MIPI_RX0_PXL 1
#define JH7110_ISPCLK_DVP_INV 2
#define JH7110_ISPCLK_M31DPHY_CFG_IN 3
#define JH7110_ISPCLK_M31DPHY_REF_IN 4
#define JH7110_ISPCLK_M31DPHY_TX_ESC_LAN0 5
#define JH7110_ISPCLK_VIN_APB 6
#define JH7110_ISPCLK_VIN_SYS 7
#define JH7110_ISPCLK_VIN_PIXEL_IF0 8
#define JH7110_ISPCLK_VIN_PIXEL_IF1 9
#define JH7110_ISPCLK_VIN_PIXEL_IF2 10
#define JH7110_ISPCLK_VIN_PIXEL_IF3 11
#define JH7110_ISPCLK_VIN_P_AXI_WR 12
#define JH7110_ISPCLK_ISPV2_TOP_WRAPPER_C 13
#define JH7110_ISPCLK_END 14
/* VOUTCRG clocks */
#define JH7110_VOUTCLK_APB 0
#define JH7110_VOUTCLK_DC8200_PIX 1
#define JH7110_VOUTCLK_DSI_SYS 2
#define JH7110_VOUTCLK_TX_ESC 3
#define JH7110_VOUTCLK_DC8200_AXI 4
#define JH7110_VOUTCLK_DC8200_CORE 5
#define JH7110_VOUTCLK_DC8200_AHB 6
#define JH7110_VOUTCLK_DC8200_PIX0 7
#define JH7110_VOUTCLK_DC8200_PIX1 8
#define JH7110_VOUTCLK_DOM_VOUT_TOP_LCD 9
#define JH7110_VOUTCLK_DSITX_APB 10
#define JH7110_VOUTCLK_DSITX_SYS 11
#define JH7110_VOUTCLK_DSITX_DPI 12
#define JH7110_VOUTCLK_DSITX_TXESC 13
#define JH7110_VOUTCLK_MIPITX_DPHY_TXESC 14
#define JH7110_VOUTCLK_HDMI_TX_MCLK 15
#define JH7110_VOUTCLK_HDMI_TX_BCLK 16
#define JH7110_VOUTCLK_HDMI_TX_SYS 17
#define JH7110_VOUTCLK_END 18
#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ */

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/* SPDX-License-Identifier: GPL-2.0 OR MIT */
/*
* Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
*/
#ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7100_AUDIO_H__
#define __DT_BINDINGS_CLOCK_STARFIVE_JH7100_AUDIO_H__
#define JH7100_AUDCLK_ADC_MCLK 0
#define JH7100_AUDCLK_I2S1_MCLK 1
#define JH7100_AUDCLK_I2SADC_APB 2
#define JH7100_AUDCLK_I2SADC_BCLK 3
#define JH7100_AUDCLK_I2SADC_BCLK_N 4
#define JH7100_AUDCLK_I2SADC_LRCLK 5
#define JH7100_AUDCLK_PDM_APB 6
#define JH7100_AUDCLK_PDM_MCLK 7
#define JH7100_AUDCLK_I2SVAD_APB 8
#define JH7100_AUDCLK_SPDIF 9
#define JH7100_AUDCLK_SPDIF_APB 10
#define JH7100_AUDCLK_PWMDAC_APB 11
#define JH7100_AUDCLK_DAC_MCLK 12
#define JH7100_AUDCLK_I2SDAC_APB 13
#define JH7100_AUDCLK_I2SDAC_BCLK 14
#define JH7100_AUDCLK_I2SDAC_BCLK_N 15
#define JH7100_AUDCLK_I2SDAC_LRCLK 16
#define JH7100_AUDCLK_I2S1_APB 17
#define JH7100_AUDCLK_I2S1_BCLK 18
#define JH7100_AUDCLK_I2S1_BCLK_N 19
#define JH7100_AUDCLK_I2S1_LRCLK 20
#define JH7100_AUDCLK_I2SDAC16K_APB 21
#define JH7100_AUDCLK_APB0_BUS 22
#define JH7100_AUDCLK_DMA1P_AHB 23
#define JH7100_AUDCLK_USB_APB 24
#define JH7100_AUDCLK_USB_LPM 25
#define JH7100_AUDCLK_USB_STB 26
#define JH7100_AUDCLK_APB_EN 27
#define JH7100_AUDCLK_VAD_MEM 28
#define JH7100_AUDCLK_END 29
#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7100_AUDIO_H__ */

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/* SPDX-License-Identifier: GPL-2.0 OR MIT */
/*
* Copyright (C) 2021 Ahmad Fatoum, Pengutronix
*/
#ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7100_H__
#define __DT_BINDINGS_CLOCK_STARFIVE_JH7100_H__
#define JH7100_CLK_CPUNDBUS_ROOT 0
#define JH7100_CLK_DLA_ROOT 1
#define JH7100_CLK_DSP_ROOT 2
#define JH7100_CLK_GMACUSB_ROOT 3
#define JH7100_CLK_PERH0_ROOT 4
#define JH7100_CLK_PERH1_ROOT 5
#define JH7100_CLK_VIN_ROOT 6
#define JH7100_CLK_VOUT_ROOT 7
#define JH7100_CLK_AUDIO_ROOT 8
#define JH7100_CLK_CDECHIFI4_ROOT 9
#define JH7100_CLK_CDEC_ROOT 10
#define JH7100_CLK_VOUTBUS_ROOT 11
#define JH7100_CLK_CPUNBUS_ROOT_DIV 12
#define JH7100_CLK_DSP_ROOT_DIV 13
#define JH7100_CLK_PERH0_SRC 14
#define JH7100_CLK_PERH1_SRC 15
#define JH7100_CLK_PLL0_TESTOUT 16
#define JH7100_CLK_PLL1_TESTOUT 17
#define JH7100_CLK_PLL2_TESTOUT 18
#define JH7100_CLK_PLL2_REF 19
#define JH7100_CLK_CPU_CORE 20
#define JH7100_CLK_CPU_AXI 21
#define JH7100_CLK_AHB_BUS 22
#define JH7100_CLK_APB1_BUS 23
#define JH7100_CLK_APB2_BUS 24
#define JH7100_CLK_DOM3AHB_BUS 25
#define JH7100_CLK_DOM7AHB_BUS 26
#define JH7100_CLK_U74_CORE0 27
#define JH7100_CLK_U74_CORE1 28
#define JH7100_CLK_U74_AXI 29
#define JH7100_CLK_U74RTC_TOGGLE 30
#define JH7100_CLK_SGDMA2P_AXI 31
#define JH7100_CLK_DMA2PNOC_AXI 32
#define JH7100_CLK_SGDMA2P_AHB 33
#define JH7100_CLK_DLA_BUS 34
#define JH7100_CLK_DLA_AXI 35
#define JH7100_CLK_DLANOC_AXI 36
#define JH7100_CLK_DLA_APB 37
#define JH7100_CLK_VP6_CORE 38
#define JH7100_CLK_VP6BUS_SRC 39
#define JH7100_CLK_VP6_AXI 40
#define JH7100_CLK_VCDECBUS_SRC 41
#define JH7100_CLK_VDEC_BUS 42
#define JH7100_CLK_VDEC_AXI 43
#define JH7100_CLK_VDECBRG_MAIN 44
#define JH7100_CLK_VDEC_BCLK 45
#define JH7100_CLK_VDEC_CCLK 46
#define JH7100_CLK_VDEC_APB 47
#define JH7100_CLK_JPEG_AXI 48
#define JH7100_CLK_JPEG_CCLK 49
#define JH7100_CLK_JPEG_APB 50
#define JH7100_CLK_GC300_2X 51
#define JH7100_CLK_GC300_AHB 52
#define JH7100_CLK_JPCGC300_AXIBUS 53
#define JH7100_CLK_GC300_AXI 54
#define JH7100_CLK_JPCGC300_MAIN 55
#define JH7100_CLK_VENC_BUS 56
#define JH7100_CLK_VENC_AXI 57
#define JH7100_CLK_VENCBRG_MAIN 58
#define JH7100_CLK_VENC_BCLK 59
#define JH7100_CLK_VENC_CCLK 60
#define JH7100_CLK_VENC_APB 61
#define JH7100_CLK_DDRPLL_DIV2 62
#define JH7100_CLK_DDRPLL_DIV4 63
#define JH7100_CLK_DDRPLL_DIV8 64
#define JH7100_CLK_DDROSC_DIV2 65
#define JH7100_CLK_DDRC0 66
#define JH7100_CLK_DDRC1 67
#define JH7100_CLK_DDRPHY_APB 68
#define JH7100_CLK_NOC_ROB 69
#define JH7100_CLK_NOC_COG 70
#define JH7100_CLK_NNE_AHB 71
#define JH7100_CLK_NNEBUS_SRC1 72
#define JH7100_CLK_NNE_BUS 73
#define JH7100_CLK_NNE_AXI 74
#define JH7100_CLK_NNENOC_AXI 75
#define JH7100_CLK_DLASLV_AXI 76
#define JH7100_CLK_DSPX2C_AXI 77
#define JH7100_CLK_HIFI4_SRC 78
#define JH7100_CLK_HIFI4_COREFREE 79
#define JH7100_CLK_HIFI4_CORE 80
#define JH7100_CLK_HIFI4_BUS 81
#define JH7100_CLK_HIFI4_AXI 82
#define JH7100_CLK_HIFI4NOC_AXI 83
#define JH7100_CLK_SGDMA1P_BUS 84
#define JH7100_CLK_SGDMA1P_AXI 85
#define JH7100_CLK_DMA1P_AXI 86
#define JH7100_CLK_X2C_AXI 87
#define JH7100_CLK_USB_BUS 88
#define JH7100_CLK_USB_AXI 89
#define JH7100_CLK_USBNOC_AXI 90
#define JH7100_CLK_USBPHY_ROOTDIV 91
#define JH7100_CLK_USBPHY_125M 92
#define JH7100_CLK_USBPHY_PLLDIV25M 93
#define JH7100_CLK_USBPHY_25M 94
#define JH7100_CLK_AUDIO_DIV 95
#define JH7100_CLK_AUDIO_SRC 96
#define JH7100_CLK_AUDIO_12288 97
#define JH7100_CLK_VIN_SRC 98
#define JH7100_CLK_ISP0_BUS 99
#define JH7100_CLK_ISP0_AXI 100
#define JH7100_CLK_ISP0NOC_AXI 101
#define JH7100_CLK_ISPSLV_AXI 102
#define JH7100_CLK_ISP1_BUS 103
#define JH7100_CLK_ISP1_AXI 104
#define JH7100_CLK_ISP1NOC_AXI 105
#define JH7100_CLK_VIN_BUS 106
#define JH7100_CLK_VIN_AXI 107
#define JH7100_CLK_VINNOC_AXI 108
#define JH7100_CLK_VOUT_SRC 109
#define JH7100_CLK_DISPBUS_SRC 110
#define JH7100_CLK_DISP_BUS 111
#define JH7100_CLK_DISP_AXI 112
#define JH7100_CLK_DISPNOC_AXI 113
#define JH7100_CLK_SDIO0_AHB 114
#define JH7100_CLK_SDIO0_CCLKINT 115
#define JH7100_CLK_SDIO0_CCLKINT_INV 116
#define JH7100_CLK_SDIO1_AHB 117
#define JH7100_CLK_SDIO1_CCLKINT 118
#define JH7100_CLK_SDIO1_CCLKINT_INV 119
#define JH7100_CLK_GMAC_AHB 120
#define JH7100_CLK_GMAC_ROOT_DIV 121
#define JH7100_CLK_GMAC_PTP_REF 122
#define JH7100_CLK_GMAC_GTX 123
#define JH7100_CLK_GMAC_RMII_TX 124
#define JH7100_CLK_GMAC_RMII_RX 125
#define JH7100_CLK_GMAC_TX 126
#define JH7100_CLK_GMAC_TX_INV 127
#define JH7100_CLK_GMAC_RX_PRE 128
#define JH7100_CLK_GMAC_RX_INV 129
#define JH7100_CLK_GMAC_RMII 130
#define JH7100_CLK_GMAC_TOPHYREF 131
#define JH7100_CLK_SPI2AHB_AHB 132
#define JH7100_CLK_SPI2AHB_CORE 133
#define JH7100_CLK_EZMASTER_AHB 134
#define JH7100_CLK_E24_AHB 135
#define JH7100_CLK_E24RTC_TOGGLE 136
#define JH7100_CLK_QSPI_AHB 137
#define JH7100_CLK_QSPI_APB 138
#define JH7100_CLK_QSPI_REF 139
#define JH7100_CLK_SEC_AHB 140
#define JH7100_CLK_AES 141
#define JH7100_CLK_SHA 142
#define JH7100_CLK_PKA 143
#define JH7100_CLK_TRNG_APB 144
#define JH7100_CLK_OTP_APB 145
#define JH7100_CLK_UART0_APB 146
#define JH7100_CLK_UART0_CORE 147
#define JH7100_CLK_UART1_APB 148
#define JH7100_CLK_UART1_CORE 149
#define JH7100_CLK_SPI0_APB 150
#define JH7100_CLK_SPI0_CORE 151
#define JH7100_CLK_SPI1_APB 152
#define JH7100_CLK_SPI1_CORE 153
#define JH7100_CLK_I2C0_APB 154
#define JH7100_CLK_I2C0_CORE 155
#define JH7100_CLK_I2C1_APB 156
#define JH7100_CLK_I2C1_CORE 157
#define JH7100_CLK_GPIO_APB 158
#define JH7100_CLK_UART2_APB 159
#define JH7100_CLK_UART2_CORE 160
#define JH7100_CLK_UART3_APB 161
#define JH7100_CLK_UART3_CORE 162
#define JH7100_CLK_SPI2_APB 163
#define JH7100_CLK_SPI2_CORE 164
#define JH7100_CLK_SPI3_APB 165
#define JH7100_CLK_SPI3_CORE 166
#define JH7100_CLK_I2C2_APB 167
#define JH7100_CLK_I2C2_CORE 168
#define JH7100_CLK_I2C3_APB 169
#define JH7100_CLK_I2C3_CORE 170
#define JH7100_CLK_WDTIMER_APB 171
#define JH7100_CLK_WDT_CORE 172
#define JH7100_CLK_TIMER0_CORE 173
#define JH7100_CLK_TIMER1_CORE 174
#define JH7100_CLK_TIMER2_CORE 175
#define JH7100_CLK_TIMER3_CORE 176
#define JH7100_CLK_TIMER4_CORE 177
#define JH7100_CLK_TIMER5_CORE 178
#define JH7100_CLK_TIMER6_CORE 179
#define JH7100_CLK_VP6INTC_APB 180
#define JH7100_CLK_PWM_APB 181
#define JH7100_CLK_MSI_APB 182
#define JH7100_CLK_TEMP_APB 183
#define JH7100_CLK_TEMP_SENSE 184
#define JH7100_CLK_SYSERR_APB 185
#define JH7100_CLK_PLL0_OUT 186
#define JH7100_CLK_PLL1_OUT 187
#define JH7100_CLK_PLL2_OUT 188
#define JH7100_CLK_END 189
#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7100_H__ */

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/* SPDX-License-Identifier: GPL-2.0 OR MIT */
/*
* Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
*/
#ifndef __DT_BINDINGS_PINCTRL_STARFIVE_JH7100_H__
#define __DT_BINDINGS_PINCTRL_STARFIVE_JH7100_H__
#define PAD_GPIO_OFFSET 0
#define PAD_FUNC_SHARE_OFFSET 64
#define PAD_GPIO(x) (PAD_GPIO_OFFSET + (x))
#define PAD_FUNC_SHARE(x) (PAD_FUNC_SHARE_OFFSET + (x))
/*
* GPIOMUX bits:
* | 31 - 24 | 23 - 16 | 15 - 8 | 7 | 6 | 5 - 0 |
* | dout | doen | din | dout rev | doen rev | gpio nr |
*
* dout: output signal
* doen: output enable signal
* din: optional input signal, 0xff = none
* dout rev: output signal reverse bit
* doen rev: output enable signal reverse bit
* gpio nr: gpio number, 0 - 63
*/
#define GPIOMUX(n, dout, doen, din) ( \
(((dout) & 0x80000000) >> (31 - 7)) | (((dout) & 0xff) << 24) | \
(((doen) & 0x80000000) >> (31 - 6)) | (((doen) & 0xff) << 16) | \
(((din) & 0xff) << 8) | \
((n) & 0x3f))
#define GPO_REVERSE 0x80000000
#define GPO_LOW 0
#define GPO_HIGH 1
#define GPO_ENABLE 0
#define GPO_DISABLE 1
#define GPO_CLK_GMAC_PAPHYREF 2
#define GPO_JTAG_TDO 3
#define GPO_JTAG_TDO_OEN 4
#define GPO_DMIC_CLK_OUT 5
#define GPO_DSP_JTDOEN_PAD 6
#define GPO_DSP_JTDO_PAD 7
#define GPO_I2C0_PAD_SCK_OE 8
#define GPO_I2C0_PAD_SCK_OEN (GPO_I2C0_PAD_SCK_OE | GPO_REVERSE)
#define GPO_I2C0_PAD_SDA_OE 9
#define GPO_I2C0_PAD_SDA_OEN (GPO_I2C0_PAD_SDA_OE | GPO_REVERSE)
#define GPO_I2C1_PAD_SCK_OE 10
#define GPO_I2C1_PAD_SCK_OEN (GPO_I2C1_PAD_SCK_OE | GPO_REVERSE)
#define GPO_I2C1_PAD_SDA_OE 11
#define GPO_I2C1_PAD_SDA_OEN (GPO_I2C1_PAD_SDA_OE | GPO_REVERSE)
#define GPO_I2C2_PAD_SCK_OE 12
#define GPO_I2C2_PAD_SCK_OEN (GPO_I2C2_PAD_SCK_OE | GPO_REVERSE)
#define GPO_I2C2_PAD_SDA_OE 13
#define GPO_I2C2_PAD_SDA_OEN (GPO_I2C2_PAD_SDA_OE | GPO_REVERSE)
#define GPO_I2C3_PAD_SCK_OE 14
#define GPO_I2C3_PAD_SCK_OEN (GPO_I2C3_PAD_SCK_OE | GPO_REVERSE)
#define GPO_I2C3_PAD_SDA_OE 15
#define GPO_I2C3_PAD_SDA_OEN (GPO_I2C3_PAD_SDA_OE | GPO_REVERSE)
#define GPO_I2SRX_BCLK_OUT 16
#define GPO_I2SRX_BCLK_OUT_OEN 17
#define GPO_I2SRX_LRCK_OUT 18
#define GPO_I2SRX_LRCK_OUT_OEN 19
#define GPO_I2SRX_MCLK_OUT 20
#define GPO_I2STX_BCLK_OUT 21
#define GPO_I2STX_BCLK_OUT_OEN 22
#define GPO_I2STX_LRCK_OUT 23
#define GPO_I2STX_LRCK_OUT_OEN 24
#define GPO_I2STX_MCLK_OUT 25
#define GPO_I2STX_SDOUT0 26
#define GPO_I2STX_SDOUT1 27
#define GPO_LCD_PAD_CSM_N 28
#define GPO_PWM_PAD_OE_N_BIT0 29
#define GPO_PWM_PAD_OE_N_BIT1 30
#define GPO_PWM_PAD_OE_N_BIT2 31
#define GPO_PWM_PAD_OE_N_BIT3 32
#define GPO_PWM_PAD_OE_N_BIT4 33
#define GPO_PWM_PAD_OE_N_BIT5 34
#define GPO_PWM_PAD_OE_N_BIT6 35
#define GPO_PWM_PAD_OE_N_BIT7 36
#define GPO_PWM_PAD_OUT_BIT0 37
#define GPO_PWM_PAD_OUT_BIT1 38
#define GPO_PWM_PAD_OUT_BIT2 39
#define GPO_PWM_PAD_OUT_BIT3 40
#define GPO_PWM_PAD_OUT_BIT4 41
#define GPO_PWM_PAD_OUT_BIT5 42
#define GPO_PWM_PAD_OUT_BIT6 43
#define GPO_PWM_PAD_OUT_BIT7 44
#define GPO_PWMDAC_LEFT_OUT 45
#define GPO_PWMDAC_RIGHT_OUT 46
#define GPO_QSPI_CSN1_OUT 47
#define GPO_QSPI_CSN2_OUT 48
#define GPO_QSPI_CSN3_OUT 49
#define GPO_REGISTER23_SCFG_CMSENSOR_RST0 50
#define GPO_REGISTER23_SCFG_CMSENSOR_RST1 51
#define GPO_REGISTER32_SCFG_GMAC_PHY_RSTN 52
#define GPO_SDIO0_PAD_CARD_POWER_EN 53
#define GPO_SDIO0_PAD_CCLK_OUT 54
#define GPO_SDIO0_PAD_CCMD_OE 55
#define GPO_SDIO0_PAD_CCMD_OEN (GPO_SDIO0_PAD_CCMD_OE | GPO_REVERSE)
#define GPO_SDIO0_PAD_CCMD_OUT 56
#define GPO_SDIO0_PAD_CDATA_OE_BIT0 57
#define GPO_SDIO0_PAD_CDATA_OEN_BIT0 (GPO_SDIO0_PAD_CDATA_OE_BIT0 | GPO_REVERSE)
#define GPO_SDIO0_PAD_CDATA_OE_BIT1 58
#define GPO_SDIO0_PAD_CDATA_OEN_BIT1 (GPO_SDIO0_PAD_CDATA_OE_BIT1 | GPO_REVERSE)
#define GPO_SDIO0_PAD_CDATA_OE_BIT2 59
#define GPO_SDIO0_PAD_CDATA_OEN_BIT2 (GPO_SDIO0_PAD_CDATA_OE_BIT2 | GPO_REVERSE)
#define GPO_SDIO0_PAD_CDATA_OE_BIT3 60
#define GPO_SDIO0_PAD_CDATA_OEN_BIT3 (GPO_SDIO0_PAD_CDATA_OE_BIT3 | GPO_REVERSE)
#define GPO_SDIO0_PAD_CDATA_OE_BIT4 61
#define GPO_SDIO0_PAD_CDATA_OEN_BIT4 (GPO_SDIO0_PAD_CDATA_OE_BIT4 | GPO_REVERSE)
#define GPO_SDIO0_PAD_CDATA_OE_BIT5 62
#define GPO_SDIO0_PAD_CDATA_OEN_BIT5 (GPO_SDIO0_PAD_CDATA_OE_BIT5 | GPO_REVERSE)
#define GPO_SDIO0_PAD_CDATA_OE_BIT6 63
#define GPO_SDIO0_PAD_CDATA_OEN_BIT6 (GPO_SDIO0_PAD_CDATA_OE_BIT6 | GPO_REVERSE)
#define GPO_SDIO0_PAD_CDATA_OE_BIT7 64
#define GPO_SDIO0_PAD_CDATA_OEN_BIT7 (GPO_SDIO0_PAD_CDATA_OE_BIT7 | GPO_REVERSE)
#define GPO_SDIO0_PAD_CDATA_OUT_BIT0 65
#define GPO_SDIO0_PAD_CDATA_OUT_BIT1 66
#define GPO_SDIO0_PAD_CDATA_OUT_BIT2 67
#define GPO_SDIO0_PAD_CDATA_OUT_BIT3 68
#define GPO_SDIO0_PAD_CDATA_OUT_BIT4 69
#define GPO_SDIO0_PAD_CDATA_OUT_BIT5 70
#define GPO_SDIO0_PAD_CDATA_OUT_BIT6 71
#define GPO_SDIO0_PAD_CDATA_OUT_BIT7 72
#define GPO_SDIO0_PAD_RST_N 73
#define GPO_SDIO1_PAD_CARD_POWER_EN 74
#define GPO_SDIO1_PAD_CCLK_OUT 75
#define GPO_SDIO1_PAD_CCMD_OE 76
#define GPO_SDIO1_PAD_CCMD_OEN (GPO_SDIO1_PAD_CCMD_OE | GPO_REVERSE)
#define GPO_SDIO1_PAD_CCMD_OUT 77
#define GPO_SDIO1_PAD_CDATA_OE_BIT0 78
#define GPO_SDIO1_PAD_CDATA_OEN_BIT0 (GPO_SDIO1_PAD_CDATA_OE_BIT0 | GPO_REVERSE)
#define GPO_SDIO1_PAD_CDATA_OE_BIT1 79
#define GPO_SDIO1_PAD_CDATA_OEN_BIT1 (GPO_SDIO1_PAD_CDATA_OE_BIT1 | GPO_REVERSE)
#define GPO_SDIO1_PAD_CDATA_OE_BIT2 80
#define GPO_SDIO1_PAD_CDATA_OEN_BIT2 (GPO_SDIO1_PAD_CDATA_OE_BIT2 | GPO_REVERSE)
#define GPO_SDIO1_PAD_CDATA_OE_BIT3 81
#define GPO_SDIO1_PAD_CDATA_OEN_BIT3 (GPO_SDIO1_PAD_CDATA_OE_BIT3 | GPO_REVERSE)
#define GPO_SDIO1_PAD_CDATA_OE_BIT4 82
#define GPO_SDIO1_PAD_CDATA_OEN_BIT4 (GPO_SDIO1_PAD_CDATA_OE_BIT4 | GPO_REVERSE)
#define GPO_SDIO1_PAD_CDATA_OE_BIT5 83
#define GPO_SDIO1_PAD_CDATA_OEN_BIT5 (GPO_SDIO1_PAD_CDATA_OE_BIT5 | GPO_REVERSE)
#define GPO_SDIO1_PAD_CDATA_OE_BIT6 84
#define GPO_SDIO1_PAD_CDATA_OEN_BIT6 (GPO_SDIO1_PAD_CDATA_OE_BIT6 | GPO_REVERSE)
#define GPO_SDIO1_PAD_CDATA_OE_BIT7 85
#define GPO_SDIO1_PAD_CDATA_OEN_BIT7 (GPO_SDIO1_PAD_CDATA_OE_BIT7 | GPO_REVERSE)
#define GPO_SDIO1_PAD_CDATA_OUT_BIT0 86
#define GPO_SDIO1_PAD_CDATA_OUT_BIT1 87
#define GPO_SDIO1_PAD_CDATA_OUT_BIT2 88
#define GPO_SDIO1_PAD_CDATA_OUT_BIT3 89
#define GPO_SDIO1_PAD_CDATA_OUT_BIT4 90
#define GPO_SDIO1_PAD_CDATA_OUT_BIT5 91
#define GPO_SDIO1_PAD_CDATA_OUT_BIT6 92
#define GPO_SDIO1_PAD_CDATA_OUT_BIT7 93
#define GPO_SDIO1_PAD_RST_N 94
#define GPO_SPDIF_TX_SDOUT 95
#define GPO_SPDIF_TX_SDOUT_OEN 96
#define GPO_SPI0_PAD_OE_N 97
#define GPO_SPI0_PAD_SCK_OUT 98
#define GPO_SPI0_PAD_SS_0_N 99
#define GPO_SPI0_PAD_SS_1_N 100
#define GPO_SPI0_PAD_TXD 101
#define GPO_SPI1_PAD_OE_N 102
#define GPO_SPI1_PAD_SCK_OUT 103
#define GPO_SPI1_PAD_SS_0_N 104
#define GPO_SPI1_PAD_SS_1_N 105
#define GPO_SPI1_PAD_TXD 106
#define GPO_SPI2_PAD_OE_N 107
#define GPO_SPI2_PAD_SCK_OUT 108
#define GPO_SPI2_PAD_SS_0_N 109
#define GPO_SPI2_PAD_SS_1_N 110
#define GPO_SPI2_PAD_TXD 111
#define GPO_SPI2AHB_PAD_OE_N_BIT0 112
#define GPO_SPI2AHB_PAD_OE_N_BIT1 113
#define GPO_SPI2AHB_PAD_OE_N_BIT2 114
#define GPO_SPI2AHB_PAD_OE_N_BIT3 115
#define GPO_SPI2AHB_PAD_TXD_BIT0 116
#define GPO_SPI2AHB_PAD_TXD_BIT1 117
#define GPO_SPI2AHB_PAD_TXD_BIT2 118
#define GPO_SPI2AHB_PAD_TXD_BIT3 119
#define GPO_SPI3_PAD_OE_N 120
#define GPO_SPI3_PAD_SCK_OUT 121
#define GPO_SPI3_PAD_SS_0_N 122
#define GPO_SPI3_PAD_SS_1_N 123
#define GPO_SPI3_PAD_TXD 124
#define GPO_UART0_PAD_DTRN 125
#define GPO_UART0_PAD_RTSN 126
#define GPO_UART0_PAD_SOUT 127
#define GPO_UART1_PAD_SOUT 128
#define GPO_UART2_PAD_DTR_N 129
#define GPO_UART2_PAD_RTS_N 130
#define GPO_UART2_PAD_SOUT 131
#define GPO_UART3_PAD_SOUT 132
#define GPO_USB_DRV_BUS 133
#define GPI_CPU_JTAG_TCK 0
#define GPI_CPU_JTAG_TDI 1
#define GPI_CPU_JTAG_TMS 2
#define GPI_CPU_JTAG_TRST 3
#define GPI_DMIC_SDIN_BIT0 4
#define GPI_DMIC_SDIN_BIT1 5
#define GPI_DSP_JTCK_PAD 6
#define GPI_DSP_JTDI_PAD 7
#define GPI_DSP_JTMS_PAD 8
#define GPI_DSP_TRST_PAD 9
#define GPI_I2C0_PAD_SCK_IN 10
#define GPI_I2C0_PAD_SDA_IN 11
#define GPI_I2C1_PAD_SCK_IN 12
#define GPI_I2C1_PAD_SDA_IN 13
#define GPI_I2C2_PAD_SCK_IN 14
#define GPI_I2C2_PAD_SDA_IN 15
#define GPI_I2C3_PAD_SCK_IN 16
#define GPI_I2C3_PAD_SDA_IN 17
#define GPI_I2SRX_BCLK_IN 18
#define GPI_I2SRX_LRCK_IN 19
#define GPI_I2SRX_SDIN_BIT0 20
#define GPI_I2SRX_SDIN_BIT1 21
#define GPI_I2SRX_SDIN_BIT2 22
#define GPI_I2STX_BCLK_IN 23
#define GPI_I2STX_LRCK_IN 24
#define GPI_SDIO0_PAD_CARD_DETECT_N 25
#define GPI_SDIO0_PAD_CARD_WRITE_PRT 26
#define GPI_SDIO0_PAD_CCMD_IN 27
#define GPI_SDIO0_PAD_CDATA_IN_BIT0 28
#define GPI_SDIO0_PAD_CDATA_IN_BIT1 29
#define GPI_SDIO0_PAD_CDATA_IN_BIT2 30
#define GPI_SDIO0_PAD_CDATA_IN_BIT3 31
#define GPI_SDIO0_PAD_CDATA_IN_BIT4 32
#define GPI_SDIO0_PAD_CDATA_IN_BIT5 33
#define GPI_SDIO0_PAD_CDATA_IN_BIT6 34
#define GPI_SDIO0_PAD_CDATA_IN_BIT7 35
#define GPI_SDIO1_PAD_CARD_DETECT_N 36
#define GPI_SDIO1_PAD_CARD_WRITE_PRT 37
#define GPI_SDIO1_PAD_CCMD_IN 38
#define GPI_SDIO1_PAD_CDATA_IN_BIT0 39
#define GPI_SDIO1_PAD_CDATA_IN_BIT1 40
#define GPI_SDIO1_PAD_CDATA_IN_BIT2 41
#define GPI_SDIO1_PAD_CDATA_IN_BIT3 42
#define GPI_SDIO1_PAD_CDATA_IN_BIT4 43
#define GPI_SDIO1_PAD_CDATA_IN_BIT5 44
#define GPI_SDIO1_PAD_CDATA_IN_BIT6 45
#define GPI_SDIO1_PAD_CDATA_IN_BIT7 46
#define GPI_SPDIF_RX_SDIN 47
#define GPI_SPI0_PAD_RXD 48
#define GPI_SPI0_PAD_SS_IN_N 49
#define GPI_SPI1_PAD_RXD 50
#define GPI_SPI1_PAD_SS_IN_N 51
#define GPI_SPI2_PAD_RXD 52
#define GPI_SPI2_PAD_SS_IN_N 53
#define GPI_SPI2AHB_PAD_RXD_BIT0 54
#define GPI_SPI2AHB_PAD_RXD_BIT1 55
#define GPI_SPI2AHB_PAD_RXD_BIT2 56
#define GPI_SPI2AHB_PAD_RXD_BIT3 57
#define GPI_SPI2AHB_PAD_SS_N 58
#define GPI_SPI2AHB_SLV_SCLKIN 59
#define GPI_SPI3_PAD_RXD 60
#define GPI_SPI3_PAD_SS_IN_N 61
#define GPI_UART0_PAD_CTSN 62
#define GPI_UART0_PAD_DCDN 63
#define GPI_UART0_PAD_DSRN 64
#define GPI_UART0_PAD_RIN 65
#define GPI_UART0_PAD_SIN 66
#define GPI_UART1_PAD_SIN 67
#define GPI_UART2_PAD_CTS_N 68
#define GPI_UART2_PAD_DCD_N 69
#define GPI_UART2_PAD_DSR_N 70
#define GPI_UART2_PAD_RI_N 71
#define GPI_UART2_PAD_SIN 72
#define GPI_UART3_PAD_SIN 73
#define GPI_USB_OVER_CURRENT 74
#define GPI_NONE 0xff
#endif /* __DT_BINDINGS_PINCTRL_STARFIVE_JH7100_H__ */

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/* SPDX-License-Identifier: GPL-2.0 OR MIT */
/*
* Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
* Copyright (C) 2022 StarFive Technology Co., Ltd.
*/
#ifndef __DT_BINDINGS_PINCTRL_STARFIVE_JH7110_H__
#define __DT_BINDINGS_PINCTRL_STARFIVE_JH7110_H__
/* sys_iomux pins */
#define PAD_GPIO0 0
#define PAD_GPIO1 1
#define PAD_GPIO2 2
#define PAD_GPIO3 3
#define PAD_GPIO4 4
#define PAD_GPIO5 5
#define PAD_GPIO6 6
#define PAD_GPIO7 7
#define PAD_GPIO8 8
#define PAD_GPIO9 9
#define PAD_GPIO10 10
#define PAD_GPIO11 11
#define PAD_GPIO12 12
#define PAD_GPIO13 13
#define PAD_GPIO14 14
#define PAD_GPIO15 15
#define PAD_GPIO16 16
#define PAD_GPIO17 17
#define PAD_GPIO18 18
#define PAD_GPIO19 19
#define PAD_GPIO20 20
#define PAD_GPIO21 21
#define PAD_GPIO22 22
#define PAD_GPIO23 23
#define PAD_GPIO24 24
#define PAD_GPIO25 25
#define PAD_GPIO26 26
#define PAD_GPIO27 27
#define PAD_GPIO28 28
#define PAD_GPIO29 29
#define PAD_GPIO30 30
#define PAD_GPIO31 31
#define PAD_GPIO32 32
#define PAD_GPIO33 33
#define PAD_GPIO34 34
#define PAD_GPIO35 35
#define PAD_GPIO36 36
#define PAD_GPIO37 37
#define PAD_GPIO38 38
#define PAD_GPIO39 39
#define PAD_GPIO40 40
#define PAD_GPIO41 41
#define PAD_GPIO42 42
#define PAD_GPIO43 43
#define PAD_GPIO44 44
#define PAD_GPIO45 45
#define PAD_GPIO46 46
#define PAD_GPIO47 47
#define PAD_GPIO48 48
#define PAD_GPIO49 49
#define PAD_GPIO50 50
#define PAD_GPIO51 51
#define PAD_GPIO52 52
#define PAD_GPIO53 53
#define PAD_GPIO54 54
#define PAD_GPIO55 55
#define PAD_GPIO56 56
#define PAD_GPIO57 57
#define PAD_GPIO58 58
#define PAD_GPIO59 59
#define PAD_GPIO60 60
#define PAD_GPIO61 61
#define PAD_GPIO62 62
#define PAD_GPIO63 63
#define PAD_SD0_CLK 64
#define PAD_SD0_CMD 65
#define PAD_SD0_DATA0 66
#define PAD_SD0_DATA1 67
#define PAD_SD0_DATA2 68
#define PAD_SD0_DATA3 69
#define PAD_SD0_DATA4 70
#define PAD_SD0_DATA5 71
#define PAD_SD0_DATA6 72
#define PAD_SD0_DATA7 73
#define PAD_SD0_STRB 74
#define PAD_GMAC1_MDC 75
#define PAD_GMAC1_MDIO 76
#define PAD_GMAC1_RXD0 77
#define PAD_GMAC1_RXD1 78
#define PAD_GMAC1_RXD2 79
#define PAD_GMAC1_RXD3 80
#define PAD_GMAC1_RXDV 81
#define PAD_GMAC1_RXC 82
#define PAD_GMAC1_TXD0 83
#define PAD_GMAC1_TXD1 84
#define PAD_GMAC1_TXD2 85
#define PAD_GMAC1_TXD3 86
#define PAD_GMAC1_TXEN 87
#define PAD_GMAC1_TXC 88
#define PAD_QSPI_SCLK 89
#define PAD_QSPI_CS0 90
#define PAD_QSPI_DATA0 91
#define PAD_QSPI_DATA1 92
#define PAD_QSPI_DATA2 93
#define PAD_QSPI_DATA3 94
/* aon_iomux pins */
#define PAD_TESTEN 0
#define PAD_RGPIO0 1
#define PAD_RGPIO1 2
#define PAD_RGPIO2 3
#define PAD_RGPIO3 4
#define PAD_RSTN 5
#define PAD_GMAC0_MDC 6
#define PAD_GMAC0_MDIO 7
#define PAD_GMAC0_RXD0 8
#define PAD_GMAC0_RXD1 9
#define PAD_GMAC0_RXD2 10
#define PAD_GMAC0_RXD3 11
#define PAD_GMAC0_RXDV 12
#define PAD_GMAC0_RXC 13
#define PAD_GMAC0_TXD0 14
#define PAD_GMAC0_TXD1 15
#define PAD_GMAC0_TXD2 16
#define PAD_GMAC0_TXD3 17
#define PAD_GMAC0_TXEN 18
#define PAD_GMAC0_TXC 19
#define GPOUT_LOW 0
#define GPOUT_HIGH 1
#define GPOEN_ENABLE 0
#define GPOEN_DISABLE 1
#define GPI_NONE 255
#endif

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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (C) 2022-2023 StarFive Technology Co., Ltd.
* Author: Walker Chen <walker.chen@starfivetech.com>
*/
#ifndef __DT_BINDINGS_POWER_JH7110_POWER_H__
#define __DT_BINDINGS_POWER_JH7110_POWER_H__
#define JH7110_PD_SYSTOP 0
#define JH7110_PD_CPU 1
#define JH7110_PD_GPUA 2
#define JH7110_PD_VDEC 3
#define JH7110_PD_VOUT 4
#define JH7110_PD_ISP 5
#define JH7110_PD_VENC 6
/* AON Power Domain */
#define JH7110_AON_PD_DPHY_TX 0
#define JH7110_AON_PD_DPHY_RX 1
#endif

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/* SPDX-License-Identifier: GPL-2.0 OR MIT */
/*
* Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
* Copyright (C) 2022 StarFive Technology Co., Ltd.
*/
#ifndef __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__
#define __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__
/* SYSCRG resets */
#define JH7110_SYSRST_JTAG_APB 0
#define JH7110_SYSRST_SYSCON_APB 1
#define JH7110_SYSRST_IOMUX_APB 2
#define JH7110_SYSRST_BUS 3
#define JH7110_SYSRST_DEBUG 4
#define JH7110_SYSRST_CORE0 5
#define JH7110_SYSRST_CORE1 6
#define JH7110_SYSRST_CORE2 7
#define JH7110_SYSRST_CORE3 8
#define JH7110_SYSRST_CORE4 9
#define JH7110_SYSRST_CORE0_ST 10
#define JH7110_SYSRST_CORE1_ST 11
#define JH7110_SYSRST_CORE2_ST 12
#define JH7110_SYSRST_CORE3_ST 13
#define JH7110_SYSRST_CORE4_ST 14
#define JH7110_SYSRST_TRACE0 15
#define JH7110_SYSRST_TRACE1 16
#define JH7110_SYSRST_TRACE2 17
#define JH7110_SYSRST_TRACE3 18
#define JH7110_SYSRST_TRACE4 19
#define JH7110_SYSRST_TRACE_COM 20
#define JH7110_SYSRST_GPU_APB 21
#define JH7110_SYSRST_GPU_DOMA 22
#define JH7110_SYSRST_NOC_BUS_APB 23
#define JH7110_SYSRST_NOC_BUS_AXICFG0_AXI 24
#define JH7110_SYSRST_NOC_BUS_CPU_AXI 25
#define JH7110_SYSRST_NOC_BUS_DISP_AXI 26
#define JH7110_SYSRST_NOC_BUS_GPU_AXI 27
#define JH7110_SYSRST_NOC_BUS_ISP_AXI 28
#define JH7110_SYSRST_NOC_BUS_DDRC 29
#define JH7110_SYSRST_NOC_BUS_STG_AXI 30
#define JH7110_SYSRST_NOC_BUS_VDEC_AXI 31
#define JH7110_SYSRST_NOC_BUS_VENC_AXI 32
#define JH7110_SYSRST_AXI_CFG1_AHB 33
#define JH7110_SYSRST_AXI_CFG1_MAIN 34
#define JH7110_SYSRST_AXI_CFG0_MAIN 35
#define JH7110_SYSRST_AXI_CFG0_MAIN_DIV 36
#define JH7110_SYSRST_AXI_CFG0_HIFI4 37
#define JH7110_SYSRST_DDR_AXI 38
#define JH7110_SYSRST_DDR_OSC 39
#define JH7110_SYSRST_DDR_APB 40
#define JH7110_SYSRST_ISP_TOP 41
#define JH7110_SYSRST_ISP_TOP_AXI 42
#define JH7110_SYSRST_VOUT_TOP_SRC 43
#define JH7110_SYSRST_CODAJ12_AXI 44
#define JH7110_SYSRST_CODAJ12_CORE 45
#define JH7110_SYSRST_CODAJ12_APB 46
#define JH7110_SYSRST_WAVE511_AXI 47
#define JH7110_SYSRST_WAVE511_BPU 48
#define JH7110_SYSRST_WAVE511_VCE 49
#define JH7110_SYSRST_WAVE511_APB 50
#define JH7110_SYSRST_VDEC_JPG 51
#define JH7110_SYSRST_VDEC_MAIN 52
#define JH7110_SYSRST_AXIMEM0_AXI 53
#define JH7110_SYSRST_WAVE420L_AXI 54
#define JH7110_SYSRST_WAVE420L_BPU 55
#define JH7110_SYSRST_WAVE420L_VCE 56
#define JH7110_SYSRST_WAVE420L_APB 57
#define JH7110_SYSRST_AXIMEM1_AXI 58
#define JH7110_SYSRST_AXIMEM2_AXI 59
#define JH7110_SYSRST_INTMEM 60
#define JH7110_SYSRST_QSPI_AHB 61
#define JH7110_SYSRST_QSPI_APB 62
#define JH7110_SYSRST_QSPI_REF 63
#define JH7110_SYSRST_SDIO0_AHB 64
#define JH7110_SYSRST_SDIO1_AHB 65
#define JH7110_SYSRST_GMAC1_AXI 66
#define JH7110_SYSRST_GMAC1_AHB 67
#define JH7110_SYSRST_MAILBOX_APB 68
#define JH7110_SYSRST_SPI0_APB 69
#define JH7110_SYSRST_SPI1_APB 70
#define JH7110_SYSRST_SPI2_APB 71
#define JH7110_SYSRST_SPI3_APB 72
#define JH7110_SYSRST_SPI4_APB 73
#define JH7110_SYSRST_SPI5_APB 74
#define JH7110_SYSRST_SPI6_APB 75
#define JH7110_SYSRST_I2C0_APB 76
#define JH7110_SYSRST_I2C1_APB 77
#define JH7110_SYSRST_I2C2_APB 78
#define JH7110_SYSRST_I2C3_APB 79
#define JH7110_SYSRST_I2C4_APB 80
#define JH7110_SYSRST_I2C5_APB 81
#define JH7110_SYSRST_I2C6_APB 82
#define JH7110_SYSRST_UART0_APB 83
#define JH7110_SYSRST_UART0_CORE 84
#define JH7110_SYSRST_UART1_APB 85
#define JH7110_SYSRST_UART1_CORE 86
#define JH7110_SYSRST_UART2_APB 87
#define JH7110_SYSRST_UART2_CORE 88
#define JH7110_SYSRST_UART3_APB 89
#define JH7110_SYSRST_UART3_CORE 90
#define JH7110_SYSRST_UART4_APB 91
#define JH7110_SYSRST_UART4_CORE 92
#define JH7110_SYSRST_UART5_APB 93
#define JH7110_SYSRST_UART5_CORE 94
#define JH7110_SYSRST_SPDIF_APB 95
#define JH7110_SYSRST_PWMDAC_APB 96
#define JH7110_SYSRST_PDM_DMIC 97
#define JH7110_SYSRST_PDM_APB 98
#define JH7110_SYSRST_I2SRX_APB 99
#define JH7110_SYSRST_I2SRX_BCLK 100
#define JH7110_SYSRST_I2STX0_APB 101
#define JH7110_SYSRST_I2STX0_BCLK 102
#define JH7110_SYSRST_I2STX1_APB 103
#define JH7110_SYSRST_I2STX1_BCLK 104
#define JH7110_SYSRST_TDM_AHB 105
#define JH7110_SYSRST_TDM_CORE 106
#define JH7110_SYSRST_TDM_APB 107
#define JH7110_SYSRST_PWM_APB 108
#define JH7110_SYSRST_WDT_APB 109
#define JH7110_SYSRST_WDT_CORE 110
#define JH7110_SYSRST_CAN0_APB 111
#define JH7110_SYSRST_CAN0_CORE 112
#define JH7110_SYSRST_CAN0_TIMER 113
#define JH7110_SYSRST_CAN1_APB 114
#define JH7110_SYSRST_CAN1_CORE 115
#define JH7110_SYSRST_CAN1_TIMER 116
#define JH7110_SYSRST_TIMER_APB 117
#define JH7110_SYSRST_TIMER0 118
#define JH7110_SYSRST_TIMER1 119
#define JH7110_SYSRST_TIMER2 120
#define JH7110_SYSRST_TIMER3 121
#define JH7110_SYSRST_INT_CTRL_APB 122
#define JH7110_SYSRST_TEMP_APB 123
#define JH7110_SYSRST_TEMP_CORE 124
#define JH7110_SYSRST_JTAG_CERTIFICATION 125
#define JH7110_SYSRST_END 126
/* AONCRG resets */
#define JH7110_AONRST_GMAC0_AXI 0
#define JH7110_AONRST_GMAC0_AHB 1
#define JH7110_AONRST_IOMUX 2
#define JH7110_AONRST_PMU_APB 3
#define JH7110_AONRST_PMU_WKUP 4
#define JH7110_AONRST_RTC_APB 5
#define JH7110_AONRST_RTC_CAL 6
#define JH7110_AONRST_RTC_32K 7
#define JH7110_AONRST_END 8
/* STGCRG resets */
#define JH7110_STGRST_SYSCON 0
#define JH7110_STGRST_HIFI4_CORE 1
#define JH7110_STGRST_HIFI4_AXI 2
#define JH7110_STGRST_SEC_AHB 3
#define JH7110_STGRST_E24_CORE 4
#define JH7110_STGRST_DMA1P_AXI 5
#define JH7110_STGRST_DMA1P_AHB 6
#define JH7110_STGRST_USB0_AXI 7
#define JH7110_STGRST_USB0_APB 8
#define JH7110_STGRST_USB0_UTMI_APB 9
#define JH7110_STGRST_USB0_PWRUP 10
#define JH7110_STGRST_PCIE0_AXI_MST0 11
#define JH7110_STGRST_PCIE0_AXI_SLV0 12
#define JH7110_STGRST_PCIE0_AXI_SLV 13
#define JH7110_STGRST_PCIE0_BRG 14
#define JH7110_STGRST_PCIE0_CORE 15
#define JH7110_STGRST_PCIE0_APB 16
#define JH7110_STGRST_PCIE1_AXI_MST0 17
#define JH7110_STGRST_PCIE1_AXI_SLV0 18
#define JH7110_STGRST_PCIE1_AXI_SLV 19
#define JH7110_STGRST_PCIE1_BRG 20
#define JH7110_STGRST_PCIE1_CORE 21
#define JH7110_STGRST_PCIE1_APB 22
#define JH7110_STGRST_END 23
/* ISPCRG resets */
#define JH7110_ISPRST_ISPV2_TOP_WRAPPER_P 0
#define JH7110_ISPRST_ISPV2_TOP_WRAPPER_C 1
#define JH7110_ISPRST_M31DPHY_HW 2
#define JH7110_ISPRST_M31DPHY_B09_AON 3
#define JH7110_ISPRST_VIN_APB 4
#define JH7110_ISPRST_VIN_PIXEL_IF0 5
#define JH7110_ISPRST_VIN_PIXEL_IF1 6
#define JH7110_ISPRST_VIN_PIXEL_IF2 7
#define JH7110_ISPRST_VIN_PIXEL_IF3 8
#define JH7110_ISPRST_VIN_SYS 9
#define JH7110_ISPRST_VIN_P_AXI_RD 10
#define JH7110_ISPRST_VIN_P_AXI_WR 11
#define JH7110_ISPRST_END 12
/* VOUTCRG resets */
#define JH7110_VOUTRST_DC8200_AXI 0
#define JH7110_VOUTRST_DC8200_AHB 1
#define JH7110_VOUTRST_DC8200_CORE 2
#define JH7110_VOUTRST_DSITX_DPI 3
#define JH7110_VOUTRST_DSITX_APB 4
#define JH7110_VOUTRST_DSITX_RXESC 5
#define JH7110_VOUTRST_DSITX_SYS 6
#define JH7110_VOUTRST_DSITX_TXBYTEHS 7
#define JH7110_VOUTRST_DSITX_TXESC 8
#define JH7110_VOUTRST_HDMI_TX_HDMI 9
#define JH7110_VOUTRST_MIPITX_DPHY_SYS 10
#define JH7110_VOUTRST_MIPITX_DPHY_TXBYTEHS 11
#define JH7110_VOUTRST_END 12
#endif /* __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__ */

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/* SPDX-License-Identifier: GPL-2.0 OR MIT */
/*
* Copyright (C) 2021 Emil Renner Berthing
*/
#ifndef __DT_BINDINGS_RESET_STARFIVE_JH7100_AUDIO_H__
#define __DT_BINDINGS_RESET_STARFIVE_JH7100_AUDIO_H__
#define JH7100_AUDRSTN_APB_BUS 0
#define JH7100_AUDRSTN_I2SADC_APB 1
#define JH7100_AUDRSTN_I2SADC_SRST 2
#define JH7100_AUDRSTN_PDM_APB 3
#define JH7100_AUDRSTN_I2SVAD_APB 4
#define JH7100_AUDRSTN_I2SVAD_SRST 5
#define JH7100_AUDRSTN_SPDIF_APB 6
#define JH7100_AUDRSTN_PWMDAC_APB 7
#define JH7100_AUDRSTN_I2SDAC_APB 8
#define JH7100_AUDRSTN_I2SDAC_SRST 9
#define JH7100_AUDRSTN_I2S1_APB 10
#define JH7100_AUDRSTN_I2S1_SRST 11
#define JH7100_AUDRSTN_I2SDAC16K_APB 12
#define JH7100_AUDRSTN_I2SDAC16K_SRST 13
#define JH7100_AUDRSTN_DMA1P_AHB 14
#define JH7100_AUDRSTN_USB_APB 15
#define JH7100_AUDRST_USB_AXI 16
#define JH7100_AUDRST_USB_PWRUP_RST_N 17
#define JH7100_AUDRST_USB_PONRST 18
#define JH7100_AUDRSTN_END 19
#endif /* __DT_BINDINGS_RESET_STARFIVE_JH7100_AUDIO_H__ */

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/* SPDX-License-Identifier: GPL-2.0 OR MIT */
/*
* Copyright (C) 2021 Ahmad Fatoum, Pengutronix
*/
#ifndef __DT_BINDINGS_RESET_STARFIVE_JH7100_H__
#define __DT_BINDINGS_RESET_STARFIVE_JH7100_H__
#define JH7100_RSTN_DOM3AHB_BUS 0
#define JH7100_RSTN_DOM7AHB_BUS 1
#define JH7100_RST_U74 2
#define JH7100_RSTN_U74_AXI 3
#define JH7100_RSTN_SGDMA2P_AHB 4
#define JH7100_RSTN_SGDMA2P_AXI 5
#define JH7100_RSTN_DMA2PNOC_AXI 6
#define JH7100_RSTN_DLA_AXI 7
#define JH7100_RSTN_DLANOC_AXI 8
#define JH7100_RSTN_DLA_APB 9
#define JH7100_RST_VP6_DRESET 10
#define JH7100_RST_VP6_BRESET 11
#define JH7100_RSTN_VP6_AXI 12
#define JH7100_RSTN_VDECBRG_MAIN 13
#define JH7100_RSTN_VDEC_AXI 14
#define JH7100_RSTN_VDEC_BCLK 15
#define JH7100_RSTN_VDEC_CCLK 16
#define JH7100_RSTN_VDEC_APB 17
#define JH7100_RSTN_JPEG_AXI 18
#define JH7100_RSTN_JPEG_CCLK 19
#define JH7100_RSTN_JPEG_APB 20
#define JH7100_RSTN_JPCGC300_MAIN 21
#define JH7100_RSTN_GC300_2X 22
#define JH7100_RSTN_GC300_AXI 23
#define JH7100_RSTN_GC300_AHB 24
#define JH7100_RSTN_VENC_AXI 25
#define JH7100_RSTN_VENCBRG_MAIN 26
#define JH7100_RSTN_VENC_BCLK 27
#define JH7100_RSTN_VENC_CCLK 28
#define JH7100_RSTN_VENC_APB 29
#define JH7100_RSTN_DDRPHY_APB 30
#define JH7100_RSTN_NOC_ROB 31
#define JH7100_RSTN_NOC_COG 32
#define JH7100_RSTN_HIFI4_AXI 33
#define JH7100_RSTN_HIFI4NOC_AXI 34
#define JH7100_RST_HIFI4_DRESET 35
#define JH7100_RST_HIFI4_BRESET 36
#define JH7100_RSTN_USB_AXI 37
#define JH7100_RSTN_USBNOC_AXI 38
#define JH7100_RSTN_SGDMA1P_AXI 39
#define JH7100_RSTN_DMA1P_AXI 40
#define JH7100_RSTN_X2C_AXI 41
#define JH7100_RSTN_NNE_AHB 42
#define JH7100_RSTN_NNE_AXI 43
#define JH7100_RSTN_NNENOC_AXI 44
#define JH7100_RSTN_DLASLV_AXI 45
#define JH7100_RSTN_DSPX2C_AXI 46
#define JH7100_RSTN_VIN_SRC 47
#define JH7100_RSTN_ISPSLV_AXI 48
#define JH7100_RSTN_VIN_AXI 49
#define JH7100_RSTN_VINNOC_AXI 50
#define JH7100_RSTN_ISP0_AXI 51
#define JH7100_RSTN_ISP0NOC_AXI 52
#define JH7100_RSTN_ISP1_AXI 53
#define JH7100_RSTN_ISP1NOC_AXI 54
#define JH7100_RSTN_VOUT_SRC 55
#define JH7100_RSTN_DISP_AXI 56
#define JH7100_RSTN_DISPNOC_AXI 57
#define JH7100_RSTN_SDIO0_AHB 58
#define JH7100_RSTN_SDIO1_AHB 59
#define JH7100_RSTN_GMAC_AHB 60
#define JH7100_RSTN_SPI2AHB_AHB 61
#define JH7100_RSTN_SPI2AHB_CORE 62
#define JH7100_RSTN_EZMASTER_AHB 63
#define JH7100_RST_E24 64
#define JH7100_RSTN_QSPI_AHB 65
#define JH7100_RSTN_QSPI_CORE 66
#define JH7100_RSTN_QSPI_APB 67
#define JH7100_RSTN_SEC_AHB 68
#define JH7100_RSTN_AES 69
#define JH7100_RSTN_PKA 70
#define JH7100_RSTN_SHA 71
#define JH7100_RSTN_TRNG_APB 72
#define JH7100_RSTN_OTP_APB 73
#define JH7100_RSTN_UART0_APB 74
#define JH7100_RSTN_UART0_CORE 75
#define JH7100_RSTN_UART1_APB 76
#define JH7100_RSTN_UART1_CORE 77
#define JH7100_RSTN_SPI0_APB 78
#define JH7100_RSTN_SPI0_CORE 79
#define JH7100_RSTN_SPI1_APB 80
#define JH7100_RSTN_SPI1_CORE 81
#define JH7100_RSTN_I2C0_APB 82
#define JH7100_RSTN_I2C0_CORE 83
#define JH7100_RSTN_I2C1_APB 84
#define JH7100_RSTN_I2C1_CORE 85
#define JH7100_RSTN_GPIO_APB 86
#define JH7100_RSTN_UART2_APB 87
#define JH7100_RSTN_UART2_CORE 88
#define JH7100_RSTN_UART3_APB 89
#define JH7100_RSTN_UART3_CORE 90
#define JH7100_RSTN_SPI2_APB 91
#define JH7100_RSTN_SPI2_CORE 92
#define JH7100_RSTN_SPI3_APB 93
#define JH7100_RSTN_SPI3_CORE 94
#define JH7100_RSTN_I2C2_APB 95
#define JH7100_RSTN_I2C2_CORE 96
#define JH7100_RSTN_I2C3_APB 97
#define JH7100_RSTN_I2C3_CORE 98
#define JH7100_RSTN_WDTIMER_APB 99
#define JH7100_RSTN_WDT 100
#define JH7100_RSTN_TIMER0 101
#define JH7100_RSTN_TIMER1 102
#define JH7100_RSTN_TIMER2 103
#define JH7100_RSTN_TIMER3 104
#define JH7100_RSTN_TIMER4 105
#define JH7100_RSTN_TIMER5 106
#define JH7100_RSTN_TIMER6 107
#define JH7100_RSTN_VP6INTC_APB 108
#define JH7100_RSTN_PWM_APB 109
#define JH7100_RSTN_MSI_APB 110
#define JH7100_RSTN_TEMP_APB 111
#define JH7100_RSTN_TEMP_SENSE 112
#define JH7100_RSTN_SYSERR_APB 113
#define JH7100_RSTN_END 114
#endif /* __DT_BINDINGS_RESET_STARFIVE_JH7100_H__ */

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/* SPDX-License-Identifier: GPL-2.0 OR MIT */
/*
* Copyright (C) 2021 samin <samin.guo@starfivetech.com>
*/
#ifndef __DT_BINDINGS_RESET_STARFIVE_JH7110_H__
#define __DT_BINDINGS_RESET_STARFIVE_JH7110_H__
/*
* group[0]: syscrg: assert0
*/
#define RSTN_U0_JTAG2APB_PRESETN 0
#define RSTN_U0_SYS_SYSCON_PRESETN 1
#define RSTN_U0_SYS_IOMUX_PRESETN 2
#define RSTN_U0_U7MC_RST_BUS 3
#define RSTN_U0_U7MC_DEBUG 4
#define RSTN_U0_U7MC_CORE0 5
#define RSTN_U0_U7MC_CORE1 6
#define RSTN_U0_U7MC_CORE2 7
#define RSTN_U0_U7MC_CORE3 8
#define RSTN_U0_U7MC_CORE4 9
#define RSTN_U0_U7MC_CORE0_ST 10
#define RSTN_U0_U7MC_CORE1_ST 11
#define RSTN_U0_U7MC_CORE2_ST 12
#define RSTN_U0_U7MC_CORE3_ST 13
#define RSTN_U0_U7MC_CORE4_ST 14
#define RSTN_U0_U7MC_TRACE_RST0 15
#define RSTN_U0_U7MC_TRACE_RST1 16
#define RSTN_U0_U7MC_TRACE_RST2 17
#define RSTN_U0_U7MC_TRACE_RST3 18
#define RSTN_U0_U7MC_TRACE_RST4 19
#define RSTN_U0_U7MC_TRACE_COM 20
#define RSTN_U0_IMG_GPU_APB 21
#define RSTN_U0_IMG_GPU_DOMA 22
#define RSTN_U0_NOC_BUS_APB_BUS_N 23
#define RSTN_U0_NOC_BUS_AXICFG0_AXI_N 24
#define RSTN_U0_NOC_BUS_CPU_AXI_N 25
#define RSTN_U0_NOC_BUS_DISP_AXI_N 26
#define RSTN_U0_NOC_BUS_GPU_AXI_N 27
#define RSTN_U0_NOC_BUS_ISP_AXI_N 28
#define RSTN_U0_NOC_BUS_DDRC_N 29
#define RSTN_U0_NOC_BUS_STG_AXI_N 30
#define RSTN_U0_NOC_BUS_VDEC_AXI_N 31
/*
* group[1]: syscrg: assert1
*/
#define RSTN_U0_NOC_BUS_VENC_AXI_N 32
#define RSTN_U0_AXI_CFG1_DEC_AHB 33
#define RSTN_U0_AXI_CFG1_DEC_MAIN 34
#define RSTN_U0_AXI_CFG0_DEC_MAIN 35
#define RSTN_U0_AXI_CFG0_DEC_MAIN_DIV 36
#define RSTN_U0_AXI_CFG0_DEC_HIFI4 37
#define RSTN_U0_DDR_AXI 38
#define RSTN_U0_DDR_OSC 39
#define RSTN_U0_DDR_APB 40
#define RSTN_U0_DOM_ISP_TOP_N 41
#define RSTN_U0_DOM_ISP_TOP_AXI 42
#define RSTN_U0_DOM_VOUT_TOP_SRC 43
#define RSTN_U0_CODAJ12_AXI 44
#define RSTN_U0_CODAJ12_CORE 45
#define RSTN_U0_CODAJ12_APB 46
#define RSTN_U0_WAVE511_AXI 47
#define RSTN_U0_WAVE511_BPU 48
#define RSTN_U0_WAVE511_VCE 49
#define RSTN_U0_WAVE511_APB 50
#define RSTN_U0_VDEC_JPG_ARB_JPG 51
#define RSTN_U0_VDEC_JPG_ARB_MAIN 52
#define RSTN_U0_AXIMEM_128B_AXI 53
#define RSTN_U0_WAVE420L_AXI 54
#define RSTN_U0_WAVE420L_BPU 55
#define RSTN_U0_WAVE420L_VCE 56
#define RSTN_U0_WAVE420L_APB 57
#define RSTN_U1_AXIMEM_128B_AXI 58
#define RSTN_U2_AXIMEM_128B_AXI 59
#define RSTN_U0_INTMEM_ROM_SRAM_ROM 60
#define RSTN_U0_CDNS_QSPI_AHB 61
#define RSTN_U0_CDNS_QSPI_APB 62
#define RSTN_U0_CDNS_QSPI_REF 63
/*
* group[2]: syscrg: assert2
*/
#define RSTN_U0_DW_SDIO_AHB 64
#define RSTN_U1_DW_SDIO_AHB 65
#define RSTN_U1_DW_GMAC5_AXI64_A_I 66
#define RSTN_U1_DW_GMAC5_AXI64_H_N 67
#define RSTN_U0_MAILBOX_RRESETN 68
#define RSTN_U0_SSP_SPI_APB 69
#define RSTN_U1_SSP_SPI_APB 70
#define RSTN_U2_SSP_SPI_APB 71
#define RSTN_U3_SSP_SPI_APB 72
#define RSTN_U4_SSP_SPI_APB 73
#define RSTN_U5_SSP_SPI_APB 74
#define RSTN_U6_SSP_SPI_APB 75
#define RSTN_U0_DW_I2C_APB 76
#define RSTN_U1_DW_I2C_APB 77
#define RSTN_U2_DW_I2C_APB 78
#define RSTN_U3_DW_I2C_APB 79
#define RSTN_U4_DW_I2C_APB 80
#define RSTN_U5_DW_I2C_APB 81
#define RSTN_U6_DW_I2C_APB 82
#define RSTN_U0_DW_UART_APB 83
#define RSTN_U0_DW_UART_CORE 84
#define RSTN_U1_DW_UART_APB 85
#define RSTN_U1_DW_UART_CORE 86
#define RSTN_U2_DW_UART_APB 87
#define RSTN_U2_DW_UART_CORE 88
#define RSTN_U3_DW_UART_APB 89
#define RSTN_U3_DW_UART_CORE 90
#define RSTN_U4_DW_UART_APB 91
#define RSTN_U4_DW_UART_CORE 92
#define RSTN_U5_DW_UART_APB 93
#define RSTN_U5_DW_UART_CORE 94
#define RSTN_U0_CDNS_SPDIF_APB 95
/*
* group[3]: syscrg: assert3
*/
#define RSTN_U0_PWMDAC_APB 96
#define RSTN_U0_PDM_4MIC_DMIC 97
#define RSTN_U0_PDM_4MIC_APB 98
#define RSTN_U0_I2SRX_3CH_APB 99
#define RSTN_U0_I2SRX_3CH_BCLK 100
#define RSTN_U0_I2STX_4CH_APB 101
#define RSTN_U0_I2STX_4CH_BCLK 102
#define RSTN_U1_I2STX_4CH_APB 103
#define RSTN_U1_I2STX_4CH_BCLK 104
#define RSTN_U0_TDM16SLOT_AHB 105
#define RSTN_U0_TDM16SLOT_TDM 106
#define RSTN_U0_TDM16SLOT_APB 107
#define RSTN_U0_PWM_8CH_APB 108
#define RSTN_U0_DSKIT_WDT_APB 109
#define RSTN_U0_DSKIT_WDT_CORE 110
#define RSTN_U0_CAN_CTRL_APB 111
#define RSTN_U0_CAN_CTRL_CORE 112
#define RSTN_U0_CAN_CTRL_TIMER 113
#define RSTN_U1_CAN_CTRL_APB 114
#define RSTN_U1_CAN_CTRL_CORE 115
#define RSTN_U1_CAN_CTRL_TIMER 116
#define RSTN_U0_TIMER_APB 117
#define RSTN_U0_TIMER_TIMER0 118
#define RSTN_U0_TIMER_TIMER1 119
#define RSTN_U0_TIMER_TIMER2 120
#define RSTN_U0_TIMER_TIMER3 121
#define RSTN_U0_INT_CTRL_APB 122
#define RSTN_U0_TEMP_SENSOR_APB 123
#define RSTN_U0_TEMP_SENSOR_TEMP 124
#define RSTN_U0_JTAG_CERTIFICATION_N 125
/*
* group[4]: stgcrg
*/
#define RSTN_U0_STG_SYSCON_PRESETN 128
#define RSTN_U0_HIFI4_CORE 129
#define RSTN_U0_HIFI4_AXI 130
#define RSTN_U0_SEC_TOP_HRESETN 131
#define RSTN_U0_E24_CORE 132
#define RSTN_U0_DW_DMA1P_AXI 133
#define RSTN_U0_DW_DMA1P_AHB 134
#define RSTN_U0_CDN_USB_AXI 135
#define RSTN_U0_CDN_USB_APB 136
#define RSTN_U0_CDN_USB_UTMI_APB 137
#define RSTN_U0_CDN_USB_PWRUP 138
#define RSTN_U0_PLDA_PCIE_AXI_MST0 139
#define RSTN_U0_PLDA_PCIE_AXI_SLV0 140
#define RSTN_U0_PLDA_PCIE_AXI_SLV 141
#define RSTN_U0_PLDA_PCIE_BRG 142
#define RSTN_U0_PLDA_PCIE_CORE 143
#define RSTN_U0_PLDA_PCIE_APB 144
#define RSTN_U1_PLDA_PCIE_AXI_MST0 145
#define RSTN_U1_PLDA_PCIE_AXI_SLV0 146
#define RSTN_U1_PLDA_PCIE_AXI_SLV 147
#define RSTN_U1_PLDA_PCIE_BRG 148
#define RSTN_U1_PLDA_PCIE_CORE 149
#define RSTN_U1_PLDA_PCIE_APB 150
/*
* group[5]: aoncrg
*/
#define RSTN_U0_DW_GMAC5_AXI64_AXI 160
#define RSTN_U0_DW_GMAC5_AXI64_AHB 161
#define RSTN_U0_AON_IOMUX_PRESETN 162
#define RSTN_U0_PMU_APB 163
#define RSTN_U0_PMU_WKUP 164
#define RSTN_U0_RTC_HMS_APB 165
#define RSTN_U0_RTC_HMS_CAL 166
#define RSTN_U0_RTC_HMS_OSC32K 167
/*
* group[6]: ispcrg
*/
#define RSTN_U0_ISPV2_TOP_WRAPPER_P 192
#define RSTN_U0_ISPV2_TOP_WRAPPER_C 193
#define RSTN_U0_M31DPHY_HW 194
#define RSTN_U0_M31DPHY_B09_ALWAYS_ON 195
#define RSTN_U0_VIN_N_PCLK 196
#define RSTN_U0_VIN_N_PIXEL_CLK_IF0 197
#define RSTN_U0_VIN_N_PIXEL_CLK_IF1 198
#define RSTN_U0_VIN_N_PIXEL_CLK_IF2 199
#define RSTN_U0_VIN_N_PIXEL_CLK_IF3 200
#define RSTN_U0_VIN_N_SYS_CLK 201
#define RSTN_U0_VIN_P_AXIRD 202
#define RSTN_U0_VIN_P_AXIWR 203
/*
* group[7]: voutcrg
*/
#define RSTN_U0_DC8200_AXI 224
#define RSTN_U0_DC8200_AHB 225
#define RSTN_U0_DC8200_CORE 226
#define RSTN_U0_CDNS_DSITX_DPI 227
#define RSTN_U0_CDNS_DSITX_APB 228
#define RSTN_U0_CDNS_DSITX_RXESC 229
#define RSTN_U0_CDNS_DSITX_SYS 230
#define RSTN_U0_CDNS_DSITX_TXBYTEHS 231
#define RSTN_U0_CDNS_DSITX_TXESC 232
#define RSTN_U0_HDMI_TX_HDMI 233
#define RSTN_U0_MIPITX_DPHY_SYS 234
#define RSTN_U0_MIPITX_DPHY_TXBYTEHS 235
#define RSTN_JH7110_RESET_END 236
#endif /* __DT_BINDINGS_RESET_STARFIVE_JH7110_H__ */