Per-cpu "physical" trap save area.
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@ -1,4 +1,4 @@
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# $NetBSD: genassym.cf,v 1.23 2010/03/31 12:56:14 skrll Exp $
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# $NetBSD: genassym.cf,v 1.24 2010/04/02 19:33:16 skrll Exp $
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# $OpenBSD: genassym.cf,v 1.18 2001/09/20 18:31:14 mickey Exp $
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@ -91,6 +91,7 @@ define CI_IPENDING offsetof(struct cpu_info, ci_ipending)
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#define CI_SOFTLWPS offsetof(struct cpu_info, ci_softlwps)
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define CI_MTX_COUNT offsetof(struct cpu_info, ci_mtx_count)
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#define CI_CURLWP offsetof(struct cpu_info, ci_curlwp)
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define CI_TRAPSAVE offsetof(struct cpu_info, ci_trapsave)
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define MTX_IPL offsetof(struct kmutex, mtx_ipl)
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define MTX_LOCK offsetof(struct kmutex, mtx_lock)
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@ -109,7 +110,6 @@ define RW_WRITER RW_WRITER
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# saved state fields
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struct trapframe
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member TF_FLAGS tf_flags
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member TF_PHYS tf_sar
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member TF_R1 tf_r1
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member TF_R2 tf_rp
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member TF_R3 tf_r3
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@ -1,4 +1,4 @@
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/* $NetBSD: cpu.h,v 1.42 2010/03/31 12:56:14 skrll Exp $ */
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/* $NetBSD: cpu.h,v 1.43 2010/04/02 19:33:16 skrll Exp $ */
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/* $OpenBSD: cpu.h,v 1.55 2008/07/23 17:39:35 kettenis Exp $ */
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@ -232,8 +232,11 @@ struct cpu_info {
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volatile int ci_cpl;
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volatile int ci_ipending; /* The pending interrupts. */
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u_int ci_intr_depth; /* Nonzero iff running an interrupt. */
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register_t ci_trapsave[16];/* the "phys" part of frame */
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};
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extern struct cpu_info cpu_info_store;
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/*
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@ -1,4 +1,4 @@
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/* $NetBSD: trap.S,v 1.47 2010/03/16 16:20:19 skrll Exp $ */
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/* $NetBSD: trap.S,v 1.48 2010/04/02 19:33:16 skrll Exp $ */
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/*-
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* Copyright (c) 2002 The NetBSD Foundation, Inc.
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@ -106,10 +106,6 @@
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*/
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.section .data
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.align 64
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L$trap_tmp_save:
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.block TF_PHYS
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.size L$trap_tmp_save, .-L$trap_tmp_save
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/* Normal stack alignment */
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.align 64
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@ -422,13 +418,13 @@ syscall_return:
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mtctl %r0, %eiem
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/*
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* 1a. Copy a `phys' part of the frame into temp store
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* (see a note for trapall)
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* hopefully no page fault would happen on or after the copy,
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* and interrupts are disabled.
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* Copy the `phys' part of the frame into CPU local temporary store (see
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* a note for trapall). Hopefully no page fault would happen on or after
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* the copy, and interrupts are disabled.
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*/
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ldil L%L$trap_tmp_save, %t2
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ldo R%L$trap_tmp_save(%t2), %t2
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mfctl CR_CURLWP, %t2
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ldw L_CPU(%t2), %t2
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ldo CI_TRAPSAVE(%t2), %t2
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ldw 0(%t3), %r1 ! ldw 4(%t3), %t1 ! stw %r1, 0(%t2) ! stw %t1, 4(%t2)
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ldw 8(%t3), %r1 ! ldw 12(%t3), %t1 ! stw %r1, 8(%t2) ! stw %t1, 12(%t2)
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@ -509,9 +505,12 @@ syscall_return:
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#endif
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ldw TF_CR0(%sr3, %t3), %t1
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mtctl %t1, %rctr
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ldw TF_CR30(%sr3, %t3), %t1
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mtctl %t1, CR_FPPADDR
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mfctl CR_CURLWP, %t3
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ldw L_CPU(%sr3, %t3), %t3
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/*
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* Clear the system mask, this puts us back into physical mode. Reload
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* the trapframe pointer with the correspondent PA value. %sp will be
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@ -519,9 +518,8 @@ syscall_return:
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* anyway.
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*/
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ssm 0, %r0
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ldil L%L$trap_tmp_save, %t3
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ldo R%L$trap_tmp_save(%t3), %t3
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nop ! nop ! nop ! nop ! nop
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ldo CI_TRAPSAVE(%t3), %t3
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nop ! nop ! nop ! nop ! nop ! nop
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rsm RESET_PSW, %r0
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/* finally we can restore the space and offset queues and the ipsw */
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@ -1913,14 +1911,15 @@ ENTRY_NOPROFILE(TLABEL(all),0)
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/* do not overwrite %tr4(%cr28) it contains the contents of r24 */
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mtctl %t3, %tr2
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ldil L%L$trap_tmp_save, %t3
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ldo R%L$trap_tmp_save(%t3), %t3
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stw %t1, TF_R22(%t3) /* use ,bc */
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stw %t2, TF_R21(%t3)
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mfctl CR_CURLWP, %t3
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ldw L_CPU(%t3), %t3
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stw %t1, CI_TRAPSAVE + TF_R22(%t3) /* use ,bc */
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stw %t2, CI_TRAPSAVE + TF_R21(%t3)
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mfctl %tr2, %t1
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stw %sp, TF_R30(%t3) /* sp */
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stw %t1, TF_R20(%t3) /* t3 */
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stw %sp, CI_TRAPSAVE + TF_R30(%t3) /* sp */
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stw %t1, CI_TRAPSAVE + TF_R20(%t3) /* t3 */
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/*
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* Now, save away other volatile state that prevents us from turning
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@ -1930,16 +1929,15 @@ ENTRY_NOPROFILE(TLABEL(all),0)
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mfctl %eiem, %t1
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mfctl %ipsw, %t2
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stw %t1, TF_CR15(%t3) /* use ,bc */
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stw %t2, TF_CR22(%t3)
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stw %t1, CI_TRAPSAVE + TF_CR15(%t3) /* use ,bc */
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stw %t2, CI_TRAPSAVE + TF_CR22(%t3)
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mfsp %sr3, %t1
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mfctl %pidr1, %t2
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stw %t1, TF_SR3(%t3)
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stw %t2, TF_CR8(%t3)
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stw %t1, CI_TRAPSAVE + TF_SR3(%t3)
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stw %t2, CI_TRAPSAVE + TF_CR8(%t3)
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/* Setup kernel context */
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ldi HPPA_PID_KERNEL,%t1
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mtctl %t1, %pidr1
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mtsp %r0, %sr3
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@ -1954,8 +1952,8 @@ ENTRY_NOPROFILE(TLABEL(all),0)
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mfctl %pcsq, %t1
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mtctl %r0, %pcsq
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mfctl %pcsq, %t2
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stw %t1, TF_IISQH(%t3) /* use ,bc */
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stw %t2, TF_IISQT(%t3)
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stw %t1, CI_TRAPSAVE + TF_IISQH(%t3) /* use ,bc */
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stw %t2, CI_TRAPSAVE + TF_IISQT(%t3)
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mtctl %r0, %pcsq
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/*
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@ -1994,7 +1992,7 @@ L$trap_from_kernel:
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* of TLB or protection fault on the kernel stack.
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*/
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mtctl %t1, %tr2
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ldw TF_R30(%t3), %t1
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ldw CI_TRAPSAVE + TF_R30(%t3), %t1
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mfctl %ior, %t2
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dep %r0, 31, PGSHIFT, %t1
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dep %r0, 31, PGSHIFT, %t2
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@ -2023,24 +2021,24 @@ L$trap_have_stack:
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ldil L%trapnowvirt, %t2
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ldo R%trapnowvirt(%t2), %t2
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mtctl %t2, %pcoq
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stw %t1, TF_IIOQH(%t3)
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stw %t1, CI_TRAPSAVE + TF_IIOQH(%t3)
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ldo 4(%t2), %t2
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mfctl %pcoq, %t1
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stw %t1, TF_IIOQT(%t3)
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stw %t1, CI_TRAPSAVE + TF_IIOQT(%t3)
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mtctl %t2, %pcoq
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/* save the interruption space and offset registers */
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mfctl %isr, %t1
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mfctl %ior, %t2
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stw %t1, TF_CR20(%t3) /* use ,bc */
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stw %t2, TF_CR21(%t3)
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stw %t1, CI_TRAPSAVE + TF_CR20(%t3) /* use ,bc */
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stw %t2, CI_TRAPSAVE + TF_CR21(%t3)
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/* save the interruption instruction register */
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mfctl %iir, %t2
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stw %t2, TF_CR19(%t3)
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stw %t2, CI_TRAPSAVE + TF_CR19(%t3)
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/* save the trap type and flags */
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stw %r1, TF_FLAGS(%t3)
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stw %r1, CI_TRAPSAVE + TF_FLAGS(%t3)
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/* gotta get it before R is up */
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mfctl %rctr, %t1
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@ -2122,8 +2120,10 @@ trapnowvirt:
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/*
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* Copy partially saved state from the store into the frame
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*/
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ldil L%L$trap_tmp_save, %t2
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ldo R%L$trap_tmp_save(%t2), %t2
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mfctl CR_CURLWP, %t2
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ldw L_CPU(%t2), %t2
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ldo CI_TRAPSAVE(%t2), %t2
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/* use ,bc each line */
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ldw 0(%t2), %r1 ! ldw 4(%t2), %t1 ! stw %r1, 0(%t3) ! stw %t1, 4(%t3)
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ldw 8(%t2), %r1 ! ldw 12(%t2), %t1 ! stw %r1, 8(%t3) ! stw %t1, 12(%t3)
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