add RK3188plus freq scaling, and a 1.4GHz mode. anything above 1GHz with all 4 cores enabled seems to have trouble locking apll, needs more work
This commit is contained in:
jmcneill
parent
4062be8536
commit
457507773a
@ -1,4 +1,4 @@
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/* $NetBSD: rockchip_board.c,v 1.7 2014/12/30 17:15:31 jmcneill Exp $ */
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/* $NetBSD: rockchip_board.c,v 1.8 2014/12/31 16:16:35 jmcneill Exp $ */
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/*-
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* Copyright (c) 2014 Jared D. McNeill <jmcneill@invisible.ca>
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@ -29,7 +29,7 @@
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#include "opt_rockchip.h"
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: rockchip_board.c,v 1.7 2014/12/30 17:15:31 jmcneill Exp $");
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__KERNEL_RCSID(0, "$NetBSD: rockchip_board.c,v 1.8 2014/12/31 16:16:35 jmcneill Exp $");
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#include <sys/param.h>
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#include <sys/bus.h>
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@ -37,6 +37,7 @@ __KERNEL_RCSID(0, "$NetBSD: rockchip_board.c,v 1.7 2014/12/30 17:15:31 jmcneill
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#include <sys/device.h>
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#include <arm/bootconfig.h>
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#include <arm/cpufunc.h>
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#include <arm/rockchip/rockchip_reg.h>
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#include <arm/rockchip/rockchip_crureg.h>
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@ -131,15 +132,17 @@ rk3188_apll_set_rate(u_int rate)
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{
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bus_space_tag_t bst = &rockchip_bs_tag;
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bus_space_handle_t bsh;
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uint32_t apll_con0, apll_con1, clksel0_con, clksel1_con;
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uint32_t apll_con0, apll_con1, apll_con2, clksel0_con, clksel1_con;
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uint32_t reset_mask, reset;
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u_int no, nr, nf, core_div, core_periph_div, core_axi_div,
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aclk_div, hclk_div, pclk_div, ahb2apb_div;
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u_int cpu_aclk_div_con;
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const bool rk3188plus_p = rockchip_is_chip(ROCKCHIP_CHIPVER_RK3188PLUS);
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rockchip_get_cru_bsh(&bsh);
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#ifdef ROCKCHIP_CLOCK_DEBUG
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printf("%s: rate=%u\n", __func__, rate);
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printf("%s: rate=%u rk3188plus_p=%d\n", __func__, rate, rk3188plus_p);
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#endif
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switch (rate) {
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@ -155,6 +158,18 @@ rk3188_apll_set_rate(u_int rate)
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pclk_div = 4;
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ahb2apb_div = 2;
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break;
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case 1416000000:
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nr = 1;
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nf = 59;
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no = 1;
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core_div = 1;
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core_periph_div = 8;
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core_axi_div = 4;
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aclk_div = 4;
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hclk_div = 2;
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pclk_div = 4;
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ahb2apb_div = 2;
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break;
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case 1008000000:
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nr = 1;
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nf = 42;
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@ -186,6 +201,14 @@ rk3188_apll_set_rate(u_int rate)
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return EINVAL;
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}
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if (rk3188plus_p) {
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reset_mask = CRU_PLL_CON3_RESET_MASK;
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reset = CRU_PLL_CON3_RESET;
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} else {
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reset_mask = CRU_PLL_CON3_POWER_DOWN_MASK;
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reset = CRU_PLL_CON3_POWER_DOWN;
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}
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apll_con0 = CRU_PLL_CON0_CLKR_MASK | CRU_PLL_CON0_CLKOD_MASK;
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apll_con0 |= __SHIFTIN(no - 1, CRU_PLL_CON0_CLKOD);
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apll_con0 |= __SHIFTIN(nr - 1, CRU_PLL_CON0_CLKR);
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@ -193,10 +216,16 @@ rk3188_apll_set_rate(u_int rate)
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apll_con1 = CRU_PLL_CON1_CLKF_MASK;
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apll_con1 |= __SHIFTIN(nf - 1, CRU_PLL_CON1_CLKF);
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if (rk3188plus_p) {
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apll_con2 = CRU_PLL_CON2_BWADJ_MASK;
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apll_con2 |= __SHIFTIN(nf >> 1, CRU_PLL_CON2_BWADJ);
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} else {
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apll_con2 = 0;
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}
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clksel0_con = RK3188_CRU_CLKSEL_CON0_A9_CORE_DIV_CON_MASK |
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CRU_CLKSEL_CON0_CORE_PERI_DIV_CON_MASK |
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CRU_CLKSEL_CON0_A9_CORE_DIV_CON_MASK |
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CRU_CLKSEL_CON0_CPU_CLK_PLL_SEL;
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CRU_CLKSEL_CON0_A9_CORE_DIV_CON_MASK;
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clksel0_con |= __SHIFTIN(core_div - 1,
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RK3188_CRU_CLKSEL_CON0_A9_CORE_DIV_CON);
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clksel0_con |= __SHIFTIN(ffs(core_periph_div) - 2,
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@ -204,11 +233,10 @@ rk3188_apll_set_rate(u_int rate)
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clksel0_con |= __SHIFTIN(aclk_div - 1,
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CRU_CLKSEL_CON0_A9_CORE_DIV_CON);
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clksel1_con = RK3188_CRU_CLKSEL_CON1_CPU_ACLK_DIV_CON_MASK |
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CRU_CLKSEL_CON1_AHB2APB_PCLKEN_DIV_CON_MASK |
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clksel1_con = CRU_CLKSEL_CON1_AHB2APB_PCLKEN_DIV_CON_MASK |
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CRU_CLKSEL_CON1_CPU_PCLK_DIV_CON_MASK |
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CRU_CLKSEL_CON1_CPU_HCLK_DIV_CON_MASK;
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switch (core_axi_div) {
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case 1: cpu_aclk_div_con = 0; break;
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case 2: cpu_aclk_div_con = 1; break;
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@ -217,8 +245,6 @@ rk3188_apll_set_rate(u_int rate)
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case 8: cpu_aclk_div_con = 4; break;
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default: panic("bad core_axi_div");
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}
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clksel1_con |= __SHIFTIN(cpu_aclk_div_con,
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RK3188_CRU_CLKSEL_CON1_CPU_ACLK_DIV_CON);
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clksel1_con |= __SHIFTIN(ffs(ahb2apb_div) - 1,
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CRU_CLKSEL_CON1_AHB2APB_PCLKEN_DIV_CON);
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clksel1_con |= __SHIFTIN(ffs(hclk_div) - 1,
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@ -237,40 +263,48 @@ rk3188_apll_set_rate(u_int rate)
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bus_space_read_4(bst, bsh, CRU_CLKSEL_CON_REG(1)));
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#endif
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/* Change from normal to slow mode */
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bus_space_write_4(bst, bsh, CRU_MODE_CON_REG,
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CRU_MODE_CON_APLL_WORK_MODE_MASK |
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__SHIFTIN(CRU_MODE_CON_APLL_WORK_MODE_SLOW,
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CRU_MODE_CON_APLL_WORK_MODE));
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/* Set CPU clk src to GPLL */
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const u_int curcpufreq = rockchip_cpu_get_rate();
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const u_int gpllfreq = rockchip_gpll_get_rate();
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bus_space_write_4(bst, bsh, CRU_CLKSEL_CON_REG(0),
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RK3188_CRU_CLKSEL_CON0_A9_CORE_DIV_CON_MASK|
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CRU_CLKSEL_CON0_CPU_CLK_PLL_SEL_MASK|
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__SHIFTIN(howmany(curcpufreq, gpllfreq) - 1,
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RK3188_CRU_CLKSEL_CON0_A9_CORE_DIV_CON)|
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CRU_CLKSEL_CON0_CPU_CLK_PLL_SEL);
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/* Power down */
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bus_space_write_4(bst, bsh, CRU_APLL_CON3_REG,
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CRU_PLL_CON3_POWER_DOWN_MASK | CRU_PLL_CON3_POWER_DOWN);
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bus_space_write_4(bst, bsh, CRU_APLL_CON3_REG, reset_mask | reset);
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/* Update APLL regs */
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bus_space_write_4(bst, bsh, CRU_APLL_CON0_REG, apll_con0);
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bus_space_write_4(bst, bsh, CRU_APLL_CON1_REG, apll_con1);
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if (apll_con2)
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bus_space_write_4(bst, bsh, CRU_APLL_CON2_REG, apll_con2);
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/* Wait for PLL lock */
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for (volatile int i = 5000; i >= 0; i--)
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;
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/* Power up */
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bus_space_write_4(bst, bsh, CRU_APLL_CON3_REG,
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CRU_PLL_CON3_POWER_DOWN_MASK);
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bus_space_write_4(bst, bsh, CRU_APLL_CON3_REG, reset_mask);
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for (volatile int i = 50000; i >= 0; i--)
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;
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/* Update CLKSEL regs */
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bus_space_write_4(bst, bsh, CRU_CLKSEL_CON_REG(0), clksel0_con);
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bus_space_write_4(bst, bsh, CRU_CLKSEL_CON_REG(1), clksel1_con);
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for (volatile int i = 50000; i >= 0; i--)
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;
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/* Set CPU clk src to APLL */
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bus_space_write_4(bst, bsh, CRU_CLKSEL_CON_REG(0),
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CRU_CLKSEL_CON0_CPU_CLK_PLL_SEL_MASK);
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/* Change from slow mode to normal mode */
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bus_space_write_4(bst, bsh, CRU_MODE_CON_REG,
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CRU_MODE_CON_APLL_WORK_MODE_MASK |
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__SHIFTIN(CRU_MODE_CON_APLL_WORK_MODE_NORMAL,
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CRU_MODE_CON_APLL_WORK_MODE));
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bus_space_write_4(bst, bsh, CRU_CLKSEL_CON_REG(0),
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RK3188_CRU_CLKSEL_CON1_CPU_ACLK_DIV_CON_MASK |
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__SHIFTIN(cpu_aclk_div_con,
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RK3188_CRU_CLKSEL_CON1_CPU_ACLK_DIV_CON));
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#ifdef ROCKCHIP_CLOCK_DEBUG
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printf("after: APLL_CON0: %#x\n",
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