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change *_TLBUpdate for the MIPS3-style two-entry TLBs to only update existing 

entries and not create new ones.  the problem with creating an entry is that
we only have the data for one side of the entry, so the other side could be
out of sync with the software PTEs, which the fault handlers are not prepared
to deal with.  fixes PR 14801.
This commit is contained in:
chs 2005-04-30 15:56:32 +00:00
parent 05f59f904d
commit 45523254b2
1 changed files with 8 additions and 49 deletions
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57
sys/arch/mips/mips/mipsX_subr.S
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@ -1,4 +1,4 @@
/* $NetBSD: mipsX_subr.S,v 1.15 2005/02/26 00:06:28 simonb Exp $ */ /* $NetBSD: mipsX_subr.S,v 1.16 2005/04/30 15:56:32 chs Exp $ */
/* /*
* Copyright 2002 Wasabi Systems, Inc. * Copyright 2002 Wasabi Systems, Inc.
@ -1598,13 +1598,13 @@ END(MIPSX(SetPID))
* *
* mipsN_TLBUpdate -- * mipsN_TLBUpdate --
* *
* Update the TLB if highreg is found; otherwise, enter the data. * Update the TLB if highreg is found; otherwise do nothing.
* *
* mips3_TLBUpdate(virpageadr, lowregx) * mips3_TLBUpdate(virpageadr, lowregx)
* unsigned virpageadr, lowregx; * unsigned virpageadr, lowregx;
* *
* Results: * Results:
* < 0 if loaded >= 0 if updated. * < 0 if skipped, >= 0 if updated.
* *
* Side effects: * Side effects:
* None. * None.
@ -1628,7 +1628,7 @@ LEAF(MIPSX(TLBUpdate))
COP0_SYNC COP0_SYNC
_SLL a1, a1, WIRED_SHIFT # Clear top 34 bits of EntryLo _SLL a1, a1, WIRED_SHIFT # Clear top 34 bits of EntryLo
_SRL a1, a1, WIRED_SHIFT _SRL a1, a1, WIRED_SHIFT
bne t1, zero, 2f # Decide even odd bne t1, zero, 1f # Decide even odd
mfc0 v0, MIPS_COP_0_TLB_INDEX # See what we got mfc0 v0, MIPS_COP_0_TLB_INDEX # See what we got
# EVEN # EVEN
nop nop
@ -1652,31 +1652,9 @@ LEAF(MIPSX(TLBUpdate))
b 4f b 4f
nop nop
1: 1:
#if defined(MIPS3) && defined(MIPS3_4100) /* VR4100 core */
lw v0, _C_LABEL(default_pg_mask) # default_pg_mask declared
mtc0 v0, MIPS_COP_0_TLB_PG_MASK # in mips_machdep.c
#else
mtc0 zero, MIPS_COP_0_TLB_PG_MASK # init mask.
#endif
COP0_SYNC
_MTC0 a0, MIPS_COP_0_TLB_HI # init high reg.
COP0_SYNC
_MTC0 a1, MIPS_COP_0_TLB_LO0 # init low reg0.
COP0_SYNC
_MTC0 a2, MIPS_COP_0_TLB_LO1 # init low reg1.
COP0_SYNC
nop
nop # required for QED5230
tlbwr # enter into a random slot
COP0_SYNC
nop # required for QED5230
nop # required for QED5230
b 4f
nop
# ODD # ODD
2:
nop nop
bltz v0, 3f # index < 0 => !found bltz v0, 4f # index < 0 => !found
nop nop
nop # required for QED5230 nop # required for QED5230
@ -1693,30 +1671,11 @@ LEAF(MIPSX(TLBUpdate))
COP0_SYNC COP0_SYNC
nop # required for QED5230 nop # required for QED5230
nop # required for QED5230 nop # required for QED5230
b 4f
nop nop
3: 4:
#if defined(MIPS3) && defined(MIPS3_4100) /* VR4100 core */ nop # Make sure pipeline
lw v0, _C_LABEL(default_pg_mask) # default_pg_mask declared
mtc0 v0, MIPS_COP_0_TLB_PG_MASK # in mips_machdep.c
#else
mtc0 zero, MIPS_COP_0_TLB_PG_MASK # init mask.
#endif
COP0_SYNC
_MTC0 a0, MIPS_COP_0_TLB_HI # init high reg.
COP0_SYNC
_MTC0 a2, MIPS_COP_0_TLB_LO0 # init low reg0.
COP0_SYNC
_MTC0 a1, MIPS_COP_0_TLB_LO1 # init low reg1.
COP0_SYNC
nop
nop # required for QED5230
tlbwr # enter into a random slot
COP0_SYNC
4: # Make shure pipeline
nop # advances before we nop # advances before we
nop # uses the tlb. nop # use the TLB.
nop
nop nop
_MTC0 t0, MIPS_COP_0_TLB_HI # restore PID _MTC0 t0, MIPS_COP_0_TLB_HI # restore PID
COP0_SYNC COP0_SYNC