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Correct a comment: NetBSD uses an undefined instruction as a breakpoint,

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not a SWI.
This commit is contained in:
bjh21 2001-10-22 19:07:10 +00:00
parent 27c601625f
commit 44b78e0623
1 changed files with 4 additions and 5 deletions
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9
gnu/dist/toolchain/gdb/config/arm/tm-arm.h vendored
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@ -92,11 +92,10 @@ extern CORE_ADDR arm_saved_pc_after_call (struct frame_info *);
Even this may only true if the condition predicate is true. The
following use a condition predicate of ALWAYS so it is always TRUE.
There are other ways of forcing a breakpoint. ARM Linux, RISC iX,
and NetBSD will all use a software interrupt rather than an
undefined instruction to force a trap. This can be handled by
redefining some or all of the following in a target dependent
fashion. */
There are other ways of forcing a breakpoint. ARM Linux and
RISC iX will use a software interrupt rather than an undefined
instruction to force a trap. This can be handled by redefining
some or all of the following in a target dependent fashion. */
#define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
#define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}