Switch to using the common m68k stuff for a couple of things:
. cache control functions <m68k/cacheops.h> . sigreturn code <m68k/m68k/sigreturn.s> Also a few of other things found while scouting around for vm_offset_t changes.
This commit is contained in:
scw
parent
573f3aee5c
commit
445aefc354
@ -1,4 +1,4 @@
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/* $NetBSD: db_memrw.c,v 1.2 1997/10/09 08:40:04 jtc Exp $ */
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/* $NetBSD: db_memrw.c,v 1.3 1998/08/16 15:33:48 scw Exp $ */
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/*-
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* Copyright (c) 1996 The NetBSD Foundation, Inc.
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@ -64,6 +64,7 @@
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#include <machine/pte.h>
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#include <machine/db_machdep.h>
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#include <machine/cpu.h>
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#include <m68k/cacheops.h>
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#include <ddb/db_access.h>
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@ -1,4 +1,4 @@
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/* $NetBSD: locore.s,v 1.37 1998/07/04 22:18:32 jonathan Exp $ */
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/* $NetBSD: locore.s,v 1.38 1998/08/16 15:33:48 scw Exp $ */
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/*
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* Copyright (c) 1988 University of Utah.
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@ -401,8 +401,10 @@ Lenab1:
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jbsr _m68881_restore | restore it (does not kill a1)
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addql #4,sp
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Lenab2:
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#if (defined(M68020)||defined(M68040)||defined(M68060))
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/* flush TLB and turn on caches */
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jbsr _TBIA | invalidate TLB
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#endif
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cmpl #MMU_68040,_mmutype | 68040?
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jeq Lnocache0 | yes, cache already on
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movl #CACHE_ON,d0
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@ -769,42 +771,12 @@ _trace:
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moveq #T_TRACE,d0
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jra fault
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/*
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* The sigreturn() syscall comes here. It requires special handling
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* because we must open a hole in the stack to fill in the (possibly much
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* larger) original stack frame.
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* Use common m68k sigreturn routine.
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*/
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sigreturn:
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lea sp@(-84),sp | leave enough space for largest frame
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movl sp@(84),sp@ | move up current 8 byte frame
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movl sp@(88),sp@(4)
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movl #84,sp@- | default: adjust by 84 bytes
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moveml #0xFFFF,sp@- | save user registers
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movl usp,a0 | save the user SP
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movl a0,sp@(FR_SP) | in the savearea
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movl #SYS_sigreturn,sp@- | push syscall number
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jbsr _syscall | handle it
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addql #4,sp | pop syscall#
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movl sp@(FR_SP),a0 | grab and restore
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movl a0,usp | user SP
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lea sp@(FR_HW),a1 | pointer to HW frame
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movw sp@(FR_ADJ),d0 | do we need to adjust the stack?
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jeq Lsigr1 | no, just continue
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moveq #92,d1 | total size
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subw d0,d1 | - hole size = frame size
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lea a1@(92),a0 | destination
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addw d1,a1 | source
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lsrw #1,d1 | convert to word count
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subqw #1,d1 | minus 1 for dbf
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Lsigrlp:
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movw a1@-,a0@- | copy a word
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dbf d1,Lsigrlp | continue
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movl a0,a1 | new HW frame base
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Lsigr1:
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movl a1,sp@(FR_SP) | new SP value
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moveml sp@+,#0x7FFF | restore user registers
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movl sp@,sp | and our SP
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jra rei | all done
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#include <m68k/m68k/sigreturn.s>
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/*
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* Interrupt handlers.
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@ -1261,197 +1233,6 @@ Lsldone:
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rts
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#endif
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/*
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* Invalidate entire TLB.
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*/
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ENTRY(TBIA)
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__TBIA:
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#if defined(M68040)
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cmpl #MMU_68040,_mmutype | 68040?
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jne Lmotommu3 | no, skip
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.word 0xf518 | yes, pflusha
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rts
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Lmotommu3:
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#endif
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tstl _mmutype | what mmu?
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jpl Lmc68851a | 68851 implies no d-cache
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movl #DC_CLEAR,d0
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movc d0,cacr | invalidate on-chip d-cache
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Lmc68851a:
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rts
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/*
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* Invalidate any TLB entry for given VA (TB Invalidate Single)
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*/
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ENTRY(TBIS)
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#ifdef DEBUG
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tstl fulltflush | being conservative?
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jne __TBIA | yes, flush entire TLB
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#endif
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#if defined(M68040)
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cmpl #MMU_68040,_mmutype | 68040?
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jne Lmotommu4 | no, skip
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movl sp@(4),a0
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movc dfc,d1
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moveq #1,d0 | user space
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movc d0,dfc
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.word 0xf508 | pflush a0@
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moveq #5,d0 | super space
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movc d0,dfc
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.word 0xf508 | pflush a0@
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movc d1,dfc
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rts
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Lmotommu4:
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#endif
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tstl _mmutype | is 68851?
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jpl Lmc68851b |
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movl sp@(4),a0 | get addr to flush
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pflush #0,#0,a0@ | flush address from both sides
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movl #DC_CLEAR,d0
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movc d0,cacr | invalidate on-chip data cache
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rts
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Lmc68851b:
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pflushs #0,#0,a0@ | flush address from both sides
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rts
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/*
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* Invalidate supervisor side of TLB
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*/
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ENTRY(TBIAS)
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#ifdef DEBUG
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tstl fulltflush | being conservative?
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jne __TBIA | yes, flush everything
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#endif
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#if defined(M68040)
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cmpl #MMU_68040,_mmutype | 68040?
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jne Lmotommu5 | no, skip
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.word 0xf518 | yes, pflusha (for now) XXX
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rts
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Lmotommu5:
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#endif
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pflush #4,#4 | flush supervisor TLB entries
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movl #DC_CLEAR,d0
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movc d0,cacr | invalidate on-chip d-cache
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rts
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/*
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* Invalidate user side of TLB
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*/
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ENTRY(TBIAU)
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#ifdef DEBUG
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tstl fulltflush | being conservative?
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jne __TBIA | yes, flush everything
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#endif
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#if defined(M68040)
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cmpl #MMU_68040,_mmutype | 68040?
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jne Lmotommu6 | no, skip
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.word 0xf518 | yes, pflusha (for now) XXX
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rts
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Lmotommu6:
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#endif
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pflush #0,#4 | flush user TLB entries
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movl #DC_CLEAR,d0
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movc d0,cacr | invalidate on-chip d-cache
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rts
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/*
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* Invalidate instruction cache
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*/
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ENTRY(ICIA)
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#if defined(M68040)
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ENTRY(ICPA)
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cmpl #MMU_68040,_mmutype | 68040
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jne Lmotommu7 | no, skip
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.word 0xf498 | cinva ic
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rts
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Lmotommu7:
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#endif
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movl #IC_CLEAR,d0
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movc d0,cacr | invalidate i-cache
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rts
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/*
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* Invalidate data cache.
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* NOTE: we do not flush 68030 on-chip cache as there are no aliasing
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* problems with DC_WA. The only cases we have to worry about are context
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* switch and TLB changes, both of which are handled "in-line" in resume
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* and TBI*.
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*/
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ENTRY(DCIA)
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__DCIA:
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#if defined(M68040)
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cmpl #MMU_68040,_mmutype | 68040
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jne Lmotommu8 | no, skip
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/* XXX implement */
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rts
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Lmotommu8:
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#endif
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rts
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ENTRY(DCIS)
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__DCIS:
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#if defined(M68040)
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cmpl #MMU_68040,_mmutype | 68040
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jne Lmotommu9 | no, skip
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/* XXX implement */
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rts
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Lmotommu9:
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#endif
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rts
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ENTRY(DCIU)
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__DCIU:
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#if defined(M68040)
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cmpl #MMU_68040,_mmutype | 68040
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jne LmotommuA | no, skip
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/* XXX implement */
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rts
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LmotommuA:
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#endif
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rts
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#if defined(M68040)
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ENTRY(ICPL)
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movl sp@(4),a0 | address
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.word 0xf488 | cinvl ic,a0@
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rts
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ENTRY(ICPP)
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movl sp@(4),a0 | address
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.word 0xf490 | cinvp ic,a0@
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rts
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ENTRY(DCPL)
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movl sp@(4),a0 | address
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.word 0xf448 | cinvl dc,a0@
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rts
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ENTRY(DCPP)
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movl sp@(4),a0 | address
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.word 0xf450 | cinvp dc,a0@
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rts
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ENTRY(DCPA)
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.word 0xf458 | cinva dc
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rts
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ENTRY(DCFL)
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movl sp@(4),a0 | address
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.word 0xf468 | cpushl dc,a0@
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rts
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ENTRY(DCFP)
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movl sp@(4),a0 | address
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.word 0xf470 | cpushp dc,a0@
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rts
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#endif
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ENTRY(PCIA)
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#if defined(M68040)
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ENTRY(DCFA)
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cmpl #MMU_68040,_mmutype | 68040
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jne LmotommuB | no, skip
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.word 0xf478 | cpusha dc
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rts
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LmotommuB:
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#endif
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movl #DC_CLEAR,d0
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movc d0,cacr | invalidate on-chip d-cache
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rts
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ENTRY(ecacheon)
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rts
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@ -1,4 +1,4 @@
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/* $NetBSD: pmap.c,v 1.20 1998/06/25 23:58:06 thorpej Exp $ */
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/* $NetBSD: pmap.c,v 1.21 1998/08/16 15:33:48 scw Exp $ */
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/*
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* Copyright (c) 1991, 1993
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@ -115,6 +115,7 @@
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#endif
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#include <machine/cpu.h>
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#include <m68k/cacheops.h>
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#ifdef PMAPSTATS
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struct {
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@ -196,8 +197,6 @@ int pmapvacflush = 0;
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int dowriteback = 1; /* 68040: enable writeback caching */
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int dokwriteback = 1; /* 68040: enable writeback caching of kernel AS */
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#endif
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extern vm_offset_t pager_sva, pager_eva;
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#endif
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/*
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@ -1708,7 +1707,9 @@ void pmap_update()
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if (pmapdebug & PDB_FOLLOW)
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printf("pmap_update()\n");
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#endif
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#if (defined(M68020)||defined(M68040)||defined(M68060))
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TBIA();
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#endif
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}
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/*
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@ -1,4 +1,4 @@
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/* $NetBSD: sys_machdep.c,v 1.10 1998/06/25 23:58:07 thorpej Exp $ */
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/* $NetBSD: sys_machdep.c,v 1.11 1998/08/16 15:33:48 scw Exp $ */
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/*
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* Copyright (c) 1982, 1986, 1993
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@ -54,6 +54,9 @@
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#include <sys/syscallargs.h>
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#include <machine/cpu.h>
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#include <m68k/cacheops.h>
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#ifdef TRACE
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int nvualarm;
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@ -112,8 +115,6 @@ vdoualarm(arg)
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}
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#endif
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#include <machine/cpu.h>
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/* XXX should be in an include file somewhere */
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#define CC_PURGE 1
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#define CC_FLUSH 2
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@ -1,4 +1,4 @@
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/* $NetBSD: trap.c,v 1.21 1998/07/04 22:18:33 jonathan Exp $ */
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/* $NetBSD: trap.c,v 1.22 1998/08/16 15:33:48 scw Exp $ */
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/*
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* Copyright (c) 1988 University of Utah.
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@ -83,6 +83,8 @@
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extern struct emul emul_sunos;
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#endif
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#include <m68k/cacheops.h>
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int astpending;
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char *trap_type[] = {
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@ -1,4 +1,4 @@
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/* $NetBSD: vm_machdep.c,v 1.13 1998/07/28 18:34:55 thorpej Exp $ */
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/* $NetBSD: vm_machdep.c,v 1.14 1998/08/16 15:33:48 scw Exp $ */
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/*
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* Copyright (c) 1988 University of Utah.
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@ -65,6 +65,7 @@
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#include <machine/cpu.h>
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#include <machine/pte.h>
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#include <machine/reg.h>
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#include <m68k/cacheops.h>
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/*
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* Finish a fork operation, with process p2 nearly set up.
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