Attach two new devices to the AMD Elan SC520 System Controller,
elansc(4). elanpex(4) is for PCI exception reporting. I've already found some kernel bugs by reading the exceptions reported. Beware that it will spam the console a lot while the kernel and pcictl(8) probe non-existing addresses in PCI configuration space. elanpar(4) protects the kernel text from writes by the CPU and by PCI bus masters. As you might guess, this is not compatible with setting breakpoints using a debugger; detach the device using 'drvctl -d elanpar0' before you try to set breakpoints. In the future, I hope to extend elanpar(4) to provide general-purpose RAM write-protection.
This commit is contained in:
dyoung
parent
9cfd7f5c79
commit
42bde7e9fa
@ -1,4 +1,4 @@
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# $NetBSD: ALL,v 1.155 2008/01/16 09:37:05 ad Exp $
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# $NetBSD: ALL,v 1.156 2008/01/21 08:04:51 dyoung Exp $
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# From NetBSD: GENERIC,v 1.787 2006/10/01 18:37:54 bouyer Exp
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#
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# ALL machine description file
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@ -17,7 +17,7 @@ include "arch/i386/conf/std.i386"
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options INCLUDE_CONFIG_FILE # embed config file in kernel binary
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#ident "ALL-$Revision: 1.155 $"
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#ident "ALL-$Revision: 1.156 $"
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maxusers 32 # estimated number of users
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@ -435,6 +435,8 @@ options PCI_INTR_FIXUP # fixup PCI interrupt routing
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# System Controllers
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elansc* at pci? dev ? function ? # AMD Elan SC520 System Controller
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gpio* at elansc?
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elanpar* at elansc?
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elanpex* at elansc?
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# PCI bridges
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amdpcib* at pci? dev ? function ? # AMD 8111 PCI-ISA w/ HPET
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@ -1,4 +1,4 @@
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# $NetBSD: files.i386,v 1.330 2008/01/16 09:37:07 ad Exp $
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# $NetBSD: files.i386,v 1.331 2008/01/21 08:04:51 dyoung Exp $
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#
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# new style config file for i386 architecture
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#
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@ -176,10 +176,18 @@ file arch/i386/pci/pcic_pci_machdep.c pcic_pci
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include "arch/x86/pci/files.pci"
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# AMD Elan SC520 System Controller (PCI-Host bridge)
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device elansc: sysmon_wdog, gpiobus
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define elanparbus { }
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define elanpexbus { }
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device elansc: sysmon_wdog, gpiobus, elanparbus, elanpexbus
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attach elansc at pci
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file arch/i386/pci/elan520.c elansc
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device elanpar
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attach elanpar at elanparbus
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device elanpex
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attach elanpex at elanpexbus
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# AMD Geode CS5535 Companion IDE controller
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device gcscide: ata, ata_dma, ata_udma, pciide_common, wdc_common
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attach gcscide at pci
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@ -1,4 +1,4 @@
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/* $NetBSD: elan520.c,v 1.21 2008/01/08 04:47:44 dyoung Exp $ */
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/* $NetBSD: elan520.c,v 1.22 2008/01/21 08:04:51 dyoung Exp $ */
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/*-
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* Copyright (c) 2002 The NetBSD Foundation, Inc.
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@ -47,10 +47,11 @@
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: elan520.c,v 1.21 2008/01/08 04:47:44 dyoung Exp $");
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__KERNEL_RCSID(0, "$NetBSD: elan520.c,v 1.22 2008/01/21 08:04:51 dyoung Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/time.h>
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#include <sys/device.h>
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#include <sys/gpio.h>
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#include <sys/mutex.h>
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@ -73,8 +74,16 @@ __KERNEL_RCSID(0, "$NetBSD: elan520.c,v 1.21 2008/01/08 04:47:44 dyoung Exp $");
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#include <dev/sysmon/sysmonvar.h>
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#define ELAN_IRQ 1
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#define IDT_PROT_SIZE PAGE_SIZE
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struct elansc_softc {
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struct device sc_dev;
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device_t sc_par;
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device_t sc_pex;
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pci_chipset_tag_t sc_pc;
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pcitag_t sc_tag;
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bus_space_tag_t sc_memt;
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bus_space_handle_t sc_memh;
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int sc_echobug;
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@ -82,6 +91,13 @@ struct elansc_softc {
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kmutex_t sc_mtx;
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struct sysmon_wdog sc_smw;
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void *sc_eih;
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void *sc_pih;
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void *sc_sh;
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uint8_t sc_mpicmode;
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uint8_t sc_picicr;
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int sc_idtpar;
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int sc_textpar;
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#if NGPIO > 0
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/* GPIO interface */
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struct gpio_chipset_tag sc_gpio_gc;
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@ -89,17 +105,33 @@ struct elansc_softc {
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#endif
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};
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int elansc_wpvnmi = 1;
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int elansc_pcinmi = 1;
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int elansc_do_protect_idt = 0;
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#if NGPIO > 0
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static int elansc_gpio_pin_read(void *, int);
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static void elansc_gpio_pin_write(void *, int, int);
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static void elansc_gpio_pin_ctl(void *, int, int);
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#endif
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static void elansc_print_par(device_t, int, uint32_t);
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static void elanpex_intr_establish(device_t, struct elansc_softc *);
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static void elanpar_intr_establish(device_t, struct elansc_softc *);
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static void elanpex_intr_disestablish(struct elansc_softc *);
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static void elanpar_intr_disestablish(struct elansc_softc *);
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static void
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elansc_childdetached(device_t self, device_t child)
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{
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/* elansc does not presently keep a pointer to children such
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* as the gpio, so there is nothing to do.
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struct elansc_softc *sc = device_private(self);
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if (child == sc->sc_par)
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sc->sc_par = NULL;
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if (child == sc->sc_pex)
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sc->sc_pex = NULL;
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/* elansc does not presently keep a pointer to
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* the gpio, so there is nothing to do if it is detached.
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*/
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}
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@ -252,6 +284,345 @@ static const char *elansc_speeds[] = {
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"(reserved 11)",
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};
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static int
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elanpar_intr(void *arg)
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{
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struct elansc_softc *sc = arg;
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uint16_t wpvsta;
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unsigned win;
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uint32_t par;
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const char *wpvstr;
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wpvsta = bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_WPVSTA);
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if ((wpvsta & MMCR_WPVSTA_WPV_STA) == 0)
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return 0;
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win = __SHIFTOUT(wpvsta, MMCR_WPVSTA_WPV_WINDOW);
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par = bus_space_read_4(sc->sc_memt, sc->sc_memh, MMCR_PAR(win));
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bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WPVSTA,
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MMCR_WPVSTA_WPV_STA);
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switch (wpvsta & MMCR_WPVSTA_WPV_MSTR) {
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case MMCR_WPVSTA_WPV_MSTR_CPU:
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wpvstr = "cpu";
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break;
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case MMCR_WPVSTA_WPV_MSTR_PCI:
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wpvstr = "pci";
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break;
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case MMCR_WPVSTA_WPV_MSTR_GP:
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wpvstr = "gp";
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break;
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default:
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wpvstr = "unknown";
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break;
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}
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aprint_error_dev(sc->sc_par,
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"%s violated write-protect window %u\n", wpvstr, win);
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elansc_print_par(sc->sc_par, win, par);
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return 0;
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}
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static int
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elanpex_intr(void *arg)
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{
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static struct {
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const char *string;
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bool nonfatal;
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} cmd[16] = {
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[0] = {.string = "not latched"}
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, [1] = {.string = "special cycle"}
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, [2] = {.string = "i/o read"}
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, [3] = {.string = "i/o write"}
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, [4] = {.string = "4"}
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, [5] = {.string = "5"}
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, [6] = {.string = "memory rd"}
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, [7] = {.string = "memory wr"}
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, [8] = {.string = "8"}
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, [9] = {.string = "9"}
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, [10] = {.string = "cfg rd", .nonfatal = true}
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, [11] = {.string = "cfg wr"}
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, [12] = {.string = "memory rd mul"}
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, [13] = {.string = "dual-address cycle"}
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, [14] = {.string = "memory rd line"}
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, [15] = {.string = "memory wr & inv"}
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};
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static const struct {
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uint16_t bit;
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const char *msg;
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} mmsg[] = {
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{MMCR_HBMSTIRQSTA_M_RTRTO_IRQ_STA, "retry timeout"}
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, {MMCR_HBMSTIRQSTA_M_TABRT_IRQ_STA, "target abort"}
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, {MMCR_HBMSTIRQSTA_M_MABRT_IRQ_STA, "abort"}
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, {MMCR_HBMSTIRQSTA_M_SERR_IRQ_STA, "system error"}
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, {MMCR_HBMSTIRQSTA_M_RPER_IRQ_STA, "received parity error"}
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, {MMCR_HBMSTIRQSTA_M_DPER_IRQ_STA, "detected parity error"}
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}, tmsg[] = {
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{MMCR_HBTGTIRQSTA_T_DLYTO_IRQ_STA, "delayed txn timeout"}
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, {MMCR_HBTGTIRQSTA_T_APER_IRQ_STA, "address parity"}
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, {MMCR_HBTGTIRQSTA_T_DPER_IRQ_STA, "data parity"}
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};
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uint8_t pciarbsta;
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uint16_t mstcmd, mstirq, tgtid, tgtirq;
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uint32_t mstaddr;
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uint16_t mstack = 0, tgtack = 0;
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int fatal = 0, i, handled = 0;
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struct elansc_softc *sc = arg;
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pciarbsta = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_PCIARBSTA);
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mstirq = bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_HBMSTIRQSTA);
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mstaddr = bus_space_read_4(sc->sc_memt, sc->sc_memh, MMCR_MSTINTADD);
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tgtirq = bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_HBTGTIRQSTA);
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if ((pciarbsta & MMCR_PCIARBSTA_GNT_TO_STA) != 0) {
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aprint_error_dev(sc->sc_pex,
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"grant time-out, GNT%" __PRIuBITS "# asserted\n",
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__SHIFTOUT(pciarbsta, MMCR_PCIARBSTA_GNT_TO_ID));
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bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_PCIARBSTA,
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MMCR_PCIARBSTA_GNT_TO_STA);
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handled = true;
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}
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mstcmd = __SHIFTOUT(mstirq, MMCR_HBMSTIRQSTA_M_CMD_IRQ_ID);
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for (i = 0; i < __arraycount(mmsg); i++) {
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if ((mstirq & mmsg[i].bit) == 0)
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continue;
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aprint_error_dev(sc->sc_pex,
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"%s %08" PRIx32 " master %s\n",
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cmd[mstcmd].string, mstaddr, mmsg[i].msg);
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mstack |= mmsg[i].bit;
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if (!cmd[mstcmd].nonfatal)
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fatal = true;
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}
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tgtid = __SHIFTOUT(tgtirq, MMCR_HBTGTIRQSTA_T_IRQ_ID);
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for (i = 0; i < __arraycount(tmsg); i++) {
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if ((tgtirq & tmsg[i].bit) == 0)
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continue;
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aprint_error_dev(sc->sc_pex, "%1x target %s\n", tgtid,
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tmsg[i].msg);
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tgtack |= tmsg[i].bit;
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}
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/* acknowledge interrupts */
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if (tgtack != 0) {
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handled = true;
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bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_HBTGTIRQSTA,
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tgtack);
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}
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if (mstack != 0) {
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handled = true;
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bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_HBMSTIRQSTA,
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mstack);
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}
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return fatal ? 0 : (handled ? 1 : 0);
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}
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#define elansc_print_1(__dev, __sc, __reg) \
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do { \
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aprint_debug_dev(__dev, \
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"%s: %s %02" PRIx8 "\n", __func__, #__reg, \
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bus_space_read_1((__sc)->sc_memt, (__sc)->sc_memh, __reg)); \
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} while (/*CONSTCOND*/0)
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static void
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elansc_print_par(device_t dev, int i, uint32_t par)
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{
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uint32_t addr, sz, unit;
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const char *tgtstr;
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switch (par & MMCR_PAR_TARGET) {
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default:
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case MMCR_PAR_TARGET_OFF:
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tgtstr = "off";
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break;
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case MMCR_PAR_TARGET_GPIO:
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tgtstr = "gpio";
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break;
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case MMCR_PAR_TARGET_GPMEM:
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tgtstr = "gpmem";
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break;
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case MMCR_PAR_TARGET_PCI:
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tgtstr = "pci";
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break;
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case MMCR_PAR_TARGET_BOOTCS:
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tgtstr = "bootcs";
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break;
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case MMCR_PAR_TARGET_ROMCS1:
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tgtstr = "romcs1";
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break;
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case MMCR_PAR_TARGET_ROMCS2:
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tgtstr = "romcs2";
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break;
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case MMCR_PAR_TARGET_SDRAM:
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tgtstr = "sdram";
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break;
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}
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if ((par & MMCR_PAR_TARGET) == MMCR_PAR_TARGET_GPIO) {
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unit = 1;
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sz = __SHIFTOUT(par, MMCR_PAR_IO_SZ);
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addr = __SHIFTOUT(par, MMCR_PAR_IO_ST_ADR);
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} else if ((par & MMCR_PAR_PG_SZ) != 0) {
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unit = 64 * 1024;
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sz = __SHIFTOUT(par, MMCR_PAR_64KB_SZ);
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addr = __SHIFTOUT(par, MMCR_PAR_64KB_ST_ADR);
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} else {
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unit = 4 * 1024;
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sz = __SHIFTOUT(par, MMCR_PAR_4KB_SZ);
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addr = __SHIFTOUT(par, MMCR_PAR_4KB_ST_ADR);
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}
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aprint_debug_dev(dev,
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"PAR[%d] %08" PRIx32 " tgt %s attr %1" __PRIxBITS
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" start %08" PRIx32 " size %" PRIu32 "\n",
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i, par, tgtstr, __SHIFTOUT(par, MMCR_PAR_ATTR),
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addr * unit, (sz + 1) * unit);
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}
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static void
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elansc_print_all_par(device_t dev,
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bus_space_tag_t memt, bus_space_handle_t memh)
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{
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int i;
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uint32_t par;
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for (i = 0; i < 16; i++) {
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par = bus_space_read_4(memt, memh, MMCR_PAR(i));
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elansc_print_par(dev, i, par);
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}
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}
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static int
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elansc_alloc_par(bus_space_tag_t memt, bus_space_handle_t memh)
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{
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int i;
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uint32_t par;
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for (i = 0; i < 16; i++) {
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par = bus_space_read_4(memt, memh, MMCR_PAR(i));
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if ((par & MMCR_PAR_TARGET) == MMCR_PAR_TARGET_OFF)
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break;
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}
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if (i == 16)
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return -1;
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return i;
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}
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static void
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elansc_disable_par(bus_space_tag_t memt, bus_space_handle_t memh, int idx)
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{
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uint32_t par;
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par = bus_space_read_4(memt, memh, MMCR_PAR(idx));
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par &= ~MMCR_PAR_TARGET;
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par |= MMCR_PAR_TARGET_OFF;
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bus_space_write_4(memt, memh, MMCR_PAR(idx), par);
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}
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static int
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elansc_protect_text(device_t self, struct elansc_softc *sc)
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{
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int i;
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uint32_t par;
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uint32_t protsize, unprotsize;
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const uint32_t sfkb = 64 * 1024;
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paddr_t start_pa, end_pa;
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extern char kernel_text, etext;
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bus_space_tag_t memt;
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bus_space_handle_t memh;
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memt = sc->sc_memt;
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memh = sc->sc_memh;
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if (!pmap_extract(pmap_kernel(), (vaddr_t)&kernel_text, &start_pa) ||
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!pmap_extract(pmap_kernel(), (vaddr_t)&etext, &end_pa))
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return -1;
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if (&etext - &kernel_text != end_pa - start_pa) {
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aprint_error_dev(self, "kernel text may not be contiguous\n");
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return -1;
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}
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if ((i = elansc_alloc_par(memt, memh)) == -1) {
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aprint_error_dev(self, "cannot allocate PAR\n");
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return -1;
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}
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par = bus_space_read_4(memt, memh, MMCR_PAR(i));
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aprint_debug_dev(self,
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"protect kernel text at physical addresses %p - %p\n",
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(void *)start_pa, (void *)end_pa);
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unprotsize = sfkb - start_pa % sfkb;
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start_pa += unprotsize;
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unprotsize += end_pa % sfkb;
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end_pa -= end_pa % sfkb;
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||||
|
||||
aprint_debug_dev(self,
|
||||
"actually protect kernel text at physical addresses %p - %p\n",
|
||||
(void *)start_pa, (void *)end_pa);
|
||||
|
||||
aprint_verbose_dev(self,
|
||||
"%" PRIu32 " bytes of kernel text are unprotected\n", unprotsize);
|
||||
|
||||
protsize = end_pa - start_pa;
|
||||
|
||||
/* clear PG_SZ, attribute, target, size, address. */
|
||||
par = MMCR_PAR_TARGET_SDRAM | MMCR_PAR_ATTR_NOWRITE | MMCR_PAR_PG_SZ;
|
||||
par |= __SHIFTIN(protsize / sfkb - 1, MMCR_PAR_64KB_SZ);
|
||||
par |= __SHIFTIN(start_pa / sfkb, MMCR_PAR_64KB_ST_ADR);
|
||||
bus_space_write_4(memt, memh, MMCR_PAR(i), par);
|
||||
return i;
|
||||
}
|
||||
|
||||
static int
|
||||
elansc_protect_idt(struct elansc_softc *sc)
|
||||
{
|
||||
int i;
|
||||
uint32_t par;
|
||||
extern paddr_t idt_paddr;
|
||||
bus_space_tag_t memt;
|
||||
bus_space_handle_t memh;
|
||||
|
||||
memt = sc->sc_memt;
|
||||
memh = sc->sc_memh;
|
||||
|
||||
if (elansc_do_protect_idt == 0)
|
||||
return -1;
|
||||
|
||||
if ((i = elansc_alloc_par(memt, memh)) == -1)
|
||||
return -1;
|
||||
|
||||
par = bus_space_read_4(memt, memh, MMCR_PAR(i));
|
||||
|
||||
aprint_debug_dev(sc->sc_par, "protect IDT at paddr %p\n",
|
||||
(const void *)idt_paddr);
|
||||
|
||||
/* clear PG_SZ, attribute, target, size, address. */
|
||||
par = MMCR_PAR_TARGET_SDRAM | MMCR_PAR_ATTR_NOWRITE;
|
||||
par |= __SHIFTIN(IDT_PROT_SIZE / PAGE_SIZE - 1, MMCR_PAR_4KB_SZ);
|
||||
par |= __SHIFTIN(idt_paddr / PAGE_SIZE, MMCR_PAR_4KB_ST_ADR);
|
||||
bus_space_write_4(memt, memh, MMCR_PAR(i), par);
|
||||
return i;
|
||||
}
|
||||
|
||||
static void
|
||||
elanpex_intr_ack(bus_space_tag_t memt, bus_space_handle_t memh)
|
||||
{
|
||||
bus_space_write_1(memt, memh, MMCR_PCIARBSTA,
|
||||
MMCR_PCIARBSTA_GNT_TO_STA);
|
||||
bus_space_write_2(memt, memh, MMCR_HBTGTIRQSTA, MMCR_TGTIRQ_ACT);
|
||||
bus_space_write_2(memt, memh, MMCR_HBMSTIRQSTA, MMCR_MSTIRQ_ACT);
|
||||
}
|
||||
|
||||
static bool
|
||||
elansc_suspend(device_t dev)
|
||||
{
|
||||
@ -314,19 +685,312 @@ elansc_detach(device_t self, int flags)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void *
|
||||
elansc_intr_establish(device_t dev, int (*handler)(void *), void *arg)
|
||||
{
|
||||
struct pic *pic;
|
||||
void *ih;
|
||||
|
||||
if ((pic = intr_findpic(ELAN_IRQ)) == NULL) {
|
||||
aprint_error_dev(dev, "PIC for irq %d not found\n",
|
||||
ELAN_IRQ);
|
||||
return NULL;
|
||||
} else if ((ih = intr_establish(ELAN_IRQ, pic, ELAN_IRQ,
|
||||
IST_LEVEL, IPL_HIGH, handler, arg)) == NULL) {
|
||||
aprint_error_dev(dev,
|
||||
"could not establish interrupt\n");
|
||||
return NULL;
|
||||
}
|
||||
aprint_verbose_dev(dev, "interrupting at irq %d\n", ELAN_IRQ);
|
||||
return ih;
|
||||
}
|
||||
|
||||
static bool
|
||||
elanpex_resume(device_t self)
|
||||
{
|
||||
struct elansc_softc *sc = device_private(device_parent(self));
|
||||
|
||||
elanpex_intr_establish(self, sc);
|
||||
return sc->sc_eih != NULL;
|
||||
}
|
||||
|
||||
static bool
|
||||
elanpex_suspend(device_t self)
|
||||
{
|
||||
struct elansc_softc *sc = device_private(device_parent(self));
|
||||
|
||||
elanpex_intr_disestablish(sc);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool
|
||||
elanpar_resume(device_t self)
|
||||
{
|
||||
struct elansc_softc *sc = device_private(device_parent(self));
|
||||
|
||||
elanpar_intr_establish(self, sc);
|
||||
return sc->sc_pih != NULL;
|
||||
}
|
||||
|
||||
static bool
|
||||
elanpar_suspend(device_t self)
|
||||
{
|
||||
struct elansc_softc *sc = device_private(device_parent(self));
|
||||
|
||||
elanpar_intr_disestablish(sc->sc_pih);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
static void
|
||||
elanpex_intr_establish(device_t self, struct elansc_softc *sc)
|
||||
{
|
||||
uint8_t sysarbctl;
|
||||
uint16_t pcihostmap, mstirq, tgtirq;
|
||||
|
||||
pcihostmap = bus_space_read_2(sc->sc_memt, sc->sc_memh,
|
||||
MMCR_PCIHOSTMAP);
|
||||
/* Priority P2 (Master PIC IR1) */
|
||||
pcihostmap &= ~MMCR_PCIHOSTMAP_PCI_IRQ_MAP;
|
||||
pcihostmap |= __SHIFTIN(__BIT(ELAN_IRQ), MMCR_PCIHOSTMAP_PCI_IRQ_MAP);
|
||||
if (elansc_pcinmi)
|
||||
pcihostmap |= MMCR_PCIHOSTMAP_PCI_NMI_ENB;
|
||||
bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_PCIHOSTMAP,
|
||||
pcihostmap);
|
||||
|
||||
elanpex_intr_ack(sc->sc_memt, sc->sc_memh);
|
||||
|
||||
sysarbctl = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_SYSARBCTL);
|
||||
mstirq = bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_HBMSTIRQCTL);
|
||||
tgtirq = bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_HBTGTIRQCTL);
|
||||
|
||||
sysarbctl |= MMCR_SYSARBCTL_GNT_TO_INT_ENB;
|
||||
|
||||
mstirq |= MMCR_HBMSTIRQCTL_M_RTRTO_IRQ_ENB;
|
||||
mstirq |= MMCR_HBMSTIRQCTL_M_TABRT_IRQ_ENB;
|
||||
mstirq |= MMCR_HBMSTIRQCTL_M_MABRT_IRQ_ENB;
|
||||
mstirq |= MMCR_HBMSTIRQCTL_M_SERR_IRQ_ENB;
|
||||
mstirq |= MMCR_HBMSTIRQCTL_M_RPER_IRQ_ENB;
|
||||
mstirq |= MMCR_HBMSTIRQCTL_M_DPER_IRQ_ENB;
|
||||
|
||||
tgtirq |= MMCR_HBTGTIRQCTL_T_DLYTO_IRQ_ENB;
|
||||
tgtirq |= MMCR_HBTGTIRQCTL_T_APER_IRQ_ENB;
|
||||
tgtirq |= MMCR_HBTGTIRQCTL_T_DPER_IRQ_ENB;
|
||||
|
||||
if (elansc_pcinmi) {
|
||||
sc->sc_eih = nmi_establish(elanpex_intr, sc);
|
||||
|
||||
mstirq |= MMCR_HBMSTIRQCTL_M_RTRTO_IRQ_SEL;
|
||||
mstirq |= MMCR_HBMSTIRQCTL_M_TABRT_IRQ_SEL;
|
||||
mstirq |= MMCR_HBMSTIRQCTL_M_MABRT_IRQ_SEL;
|
||||
mstirq |= MMCR_HBMSTIRQCTL_M_SERR_IRQ_SEL;
|
||||
mstirq |= MMCR_HBMSTIRQCTL_M_RPER_IRQ_SEL;
|
||||
mstirq |= MMCR_HBMSTIRQCTL_M_DPER_IRQ_SEL;
|
||||
|
||||
tgtirq |= MMCR_HBTGTIRQCTL_T_DLYTO_IRQ_SEL;
|
||||
tgtirq |= MMCR_HBTGTIRQCTL_T_APER_IRQ_SEL;
|
||||
tgtirq |= MMCR_HBTGTIRQCTL_T_DPER_IRQ_SEL;
|
||||
} else
|
||||
sc->sc_eih = elansc_intr_establish(self, elanpex_intr, sc);
|
||||
|
||||
bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_SYSARBCTL, sysarbctl);
|
||||
bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_HBMSTIRQCTL, mstirq);
|
||||
bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_HBTGTIRQCTL, tgtirq);
|
||||
}
|
||||
|
||||
static void
|
||||
elanpex_attach(device_t parent, device_t self, void *aux)
|
||||
{
|
||||
struct elansc_softc *sc = device_private(parent);
|
||||
|
||||
aprint_naive(": PCI Exceptions\n");
|
||||
aprint_normal(": AMD Elan SC520 PCI Exceptions\n");
|
||||
|
||||
elanpex_intr_establish(self, sc);
|
||||
|
||||
aprint_debug_dev(self, "HBMSTIRQCTL %04x\n",
|
||||
bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_HBMSTIRQCTL));
|
||||
|
||||
aprint_debug_dev(self, "HBTGTIRQCTL %04x\n",
|
||||
bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_HBTGTIRQCTL));
|
||||
|
||||
aprint_debug_dev(self, "PCIHOSTMAP %04x\n",
|
||||
bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_PCIHOSTMAP));
|
||||
|
||||
pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG,
|
||||
pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG) |
|
||||
PCI_COMMAND_PARITY_ENABLE|PCI_COMMAND_SERR_ENABLE);
|
||||
|
||||
if (!pmf_device_register(self, elanpex_suspend, elanpex_resume))
|
||||
aprint_error_dev(self, "could not establish power hooks\n");
|
||||
}
|
||||
|
||||
static void
|
||||
elanpex_intr_disestablish(struct elansc_softc *sc)
|
||||
{
|
||||
uint8_t sysarbctl;
|
||||
uint16_t pcihostmap, mstirq, tgtirq;
|
||||
|
||||
sysarbctl = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_SYSARBCTL);
|
||||
sysarbctl &= ~MMCR_SYSARBCTL_GNT_TO_INT_ENB;
|
||||
bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_SYSARBCTL, sysarbctl);
|
||||
|
||||
mstirq = bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_HBMSTIRQCTL);
|
||||
mstirq &= ~MMCR_HBMSTIRQCTL_M_RTRTO_IRQ_ENB;
|
||||
mstirq &= ~MMCR_HBMSTIRQCTL_M_TABRT_IRQ_ENB;
|
||||
mstirq &= ~MMCR_HBMSTIRQCTL_M_MABRT_IRQ_ENB;
|
||||
mstirq &= ~MMCR_HBMSTIRQCTL_M_SERR_IRQ_ENB;
|
||||
mstirq &= ~MMCR_HBMSTIRQCTL_M_RPER_IRQ_ENB;
|
||||
mstirq &= ~MMCR_HBMSTIRQCTL_M_DPER_IRQ_ENB;
|
||||
bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_HBMSTIRQCTL, mstirq);
|
||||
|
||||
tgtirq = bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_HBTGTIRQCTL);
|
||||
tgtirq &= ~MMCR_HBTGTIRQCTL_T_DLYTO_IRQ_ENB;
|
||||
tgtirq &= ~MMCR_HBTGTIRQCTL_T_APER_IRQ_ENB;
|
||||
tgtirq &= ~MMCR_HBTGTIRQCTL_T_DPER_IRQ_ENB;
|
||||
bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_HBTGTIRQCTL, tgtirq);
|
||||
|
||||
pcihostmap = bus_space_read_2(sc->sc_memt, sc->sc_memh,
|
||||
MMCR_PCIHOSTMAP);
|
||||
/* Priority P2 (Master PIC IR1) */
|
||||
pcihostmap &= ~MMCR_PCIHOSTMAP_PCI_IRQ_MAP;
|
||||
bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_PCIHOSTMAP,
|
||||
pcihostmap);
|
||||
|
||||
if (elansc_pcinmi)
|
||||
nmi_disestablish(sc->sc_eih);
|
||||
else
|
||||
intr_disestablish(sc->sc_eih);
|
||||
sc->sc_eih = NULL;
|
||||
|
||||
}
|
||||
|
||||
static int
|
||||
elanpex_detach(device_t self, int flags)
|
||||
{
|
||||
struct elansc_softc *sc = device_private(device_parent(self));
|
||||
|
||||
pmf_device_deregister(self);
|
||||
elanpex_intr_disestablish(sc);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void
|
||||
elanpar_intr_establish(device_t self, struct elansc_softc *sc)
|
||||
{
|
||||
uint8_t adddecctl, wpvmap;
|
||||
|
||||
wpvmap = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_WPVMAP);
|
||||
wpvmap &= ~MMCR_WPVMAP_INT_MAP;
|
||||
if (elansc_wpvnmi)
|
||||
wpvmap |= MMCR_WPVMAP_INT_NMI;
|
||||
else
|
||||
wpvmap |= __SHIFTIN(__BIT(ELAN_IRQ), MMCR_WPVMAP_INT_MAP);
|
||||
bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_WPVMAP, wpvmap);
|
||||
|
||||
/* clear interrupt status */
|
||||
bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WPVSTA,
|
||||
MMCR_WPVSTA_WPV_STA);
|
||||
|
||||
/* establish interrupt */
|
||||
if (elansc_wpvnmi)
|
||||
sc->sc_pih = nmi_establish(elanpar_intr, sc);
|
||||
else
|
||||
sc->sc_pih = elansc_intr_establish(self, elanpar_intr, sc);
|
||||
|
||||
adddecctl = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_ADDDECCTL);
|
||||
adddecctl |= MMCR_ADDDECCTL_WPV_INT_ENB;
|
||||
bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_ADDDECCTL, adddecctl);
|
||||
}
|
||||
|
||||
static void
|
||||
elanpar_attach(device_t parent, device_t self, void *aux)
|
||||
{
|
||||
struct elansc_softc *sc = device_private(parent);
|
||||
|
||||
aprint_naive(": Programmable Address Regions\n");
|
||||
aprint_normal(": AMD Elan SC520 Programmable Address Regions\n");
|
||||
|
||||
elansc_print_1(self, sc, MMCR_WPVMAP);
|
||||
elansc_print_all_par(self, sc->sc_memt, sc->sc_memh);
|
||||
|
||||
sc->sc_idtpar = elansc_protect_idt(sc);
|
||||
sc->sc_textpar = elansc_protect_text(self, sc);
|
||||
|
||||
elanpar_intr_establish(self, sc);
|
||||
|
||||
elansc_print_1(self, sc, MMCR_ADDDECCTL);
|
||||
|
||||
if (!pmf_device_register(self, elanpar_suspend, elanpar_resume))
|
||||
aprint_error_dev(self, "could not establish power hooks\n");
|
||||
}
|
||||
|
||||
static void
|
||||
elanpar_intr_disestablish(struct elansc_softc *sc)
|
||||
{
|
||||
uint8_t adddecctl, wpvmap;
|
||||
|
||||
/* disable interrupt, acknowledge it, disestablish our
|
||||
* handler, unmap it
|
||||
*/
|
||||
adddecctl = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_ADDDECCTL);
|
||||
adddecctl &= ~MMCR_ADDDECCTL_WPV_INT_ENB;
|
||||
bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_ADDDECCTL, adddecctl);
|
||||
|
||||
bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WPVSTA,
|
||||
MMCR_WPVSTA_WPV_STA);
|
||||
|
||||
if (elansc_wpvnmi)
|
||||
nmi_disestablish(sc->sc_pih);
|
||||
else
|
||||
intr_disestablish(sc->sc_pih);
|
||||
sc->sc_pih = NULL;
|
||||
|
||||
wpvmap = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_WPVMAP);
|
||||
wpvmap &= ~MMCR_WPVMAP_INT_MAP;
|
||||
bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_WPVMAP, wpvmap);
|
||||
}
|
||||
|
||||
static int
|
||||
elanpar_detach(device_t self, int flags)
|
||||
{
|
||||
struct elansc_softc *sc = device_private(device_parent(self));
|
||||
|
||||
pmf_device_deregister(self);
|
||||
|
||||
if (sc->sc_textpar != -1) {
|
||||
elansc_disable_par(sc->sc_memt, sc->sc_memh, sc->sc_textpar);
|
||||
sc->sc_textpar = -1;
|
||||
}
|
||||
if (sc->sc_idtpar != -1) {
|
||||
elansc_disable_par(sc->sc_memt, sc->sc_memh, sc->sc_idtpar);
|
||||
sc->sc_idtpar = -1;
|
||||
}
|
||||
|
||||
elanpar_intr_disestablish(sc);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void
|
||||
elansc_attach(device_t parent, device_t self, void *aux)
|
||||
{
|
||||
struct elansc_softc *sc = device_private(self);
|
||||
struct pci_attach_args *pa = aux;
|
||||
uint16_t rev;
|
||||
uint8_t ressta, cpuctl;
|
||||
uint8_t cpuctl, picicr, ressta;
|
||||
#if 0
|
||||
struct pci_conf_state pcf;
|
||||
#endif
|
||||
#if NGPIO > 0
|
||||
struct gpiobus_attach_args gba;
|
||||
int pin;
|
||||
int reg, shift;
|
||||
int pin, reg, shift;
|
||||
uint16_t data;
|
||||
#endif
|
||||
sc->sc_pc = pa->pa_pc;
|
||||
sc->sc_tag = pa->pa_tag;
|
||||
|
||||
aprint_naive(": System Controller\n");
|
||||
aprint_normal(": AMD Elan SC520 System Controller\n");
|
||||
@ -377,13 +1041,39 @@ elansc_attach(device_t parent, device_t self, void *aux)
|
||||
"WARNING: LAST RESET DUE TO WATCHDOG EXPIRATION!\n");
|
||||
bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_RESSTA, ressta);
|
||||
|
||||
elansc_print_1(self, sc, MMCR_MPICMODE);
|
||||
elansc_print_1(self, sc, MMCR_SL1PICMODE);
|
||||
elansc_print_1(self, sc, MMCR_SL2PICMODE);
|
||||
elansc_print_1(self, sc, MMCR_PICICR);
|
||||
|
||||
sc->sc_mpicmode = bus_space_read_1(sc->sc_memt, sc->sc_memh,
|
||||
MMCR_MPICMODE);
|
||||
bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_MPICMODE,
|
||||
sc->sc_mpicmode | __BIT(ELAN_IRQ));
|
||||
|
||||
sc->sc_picicr = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_PICICR);
|
||||
picicr = sc->sc_picicr;
|
||||
if (elansc_pcinmi || elansc_wpvnmi)
|
||||
picicr |= MMCR_PICICR_NMI_ENB;
|
||||
#if 0
|
||||
/* PC/AT compatibility */
|
||||
picicr |= MMCR_PICICR_S1_GINT_MODE|MMCR_PICICR_M_GINT_MODE;
|
||||
#endif
|
||||
bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_PICICR, picicr);
|
||||
|
||||
elansc_print_1(self, sc, MMCR_PICICR);
|
||||
elansc_print_1(self, sc, MMCR_MPICMODE);
|
||||
|
||||
mutex_enter(&sc->sc_mtx);
|
||||
/* Set up the watchdog registers with some defaults. */
|
||||
elansc_wdogctl_write(sc, WDTMRCTL_WRST_ENB | WDTMRCTL_EXP_SEL30);
|
||||
|
||||
/* ...and clear it. */
|
||||
elansc_wdogctl_reset(sc);
|
||||
mutex_exit(&sc->sc_mtx);
|
||||
|
||||
pmf_device_register(self, elansc_suspend, elansc_resume);
|
||||
if (!pmf_device_register(self, elansc_suspend, elansc_resume))
|
||||
aprint_error_dev(self, "could not establish power hooks\n");
|
||||
|
||||
#if NGPIO > 0
|
||||
/* Initialize GPIO pins array */
|
||||
@ -416,6 +1106,8 @@ elansc_attach(device_t parent, device_t self, void *aux)
|
||||
gba.gba_pins = sc->sc_gpio_pins;
|
||||
gba.gba_npins = ELANSC_PIO_NPINS;
|
||||
|
||||
sc->sc_par = config_found_ia(&sc->sc_dev, "elanparbus", NULL, NULL);
|
||||
sc->sc_pex = config_found_ia(&sc->sc_dev, "elanpexbus", NULL, NULL);
|
||||
/* Attach GPIO framework */
|
||||
config_found_ia(&sc->sc_dev, "gpiobus", &gba, gpiobus_print);
|
||||
#endif /* NGPIO */
|
||||
@ -434,6 +1126,28 @@ elansc_attach(device_t parent, device_t self, void *aux)
|
||||
}
|
||||
}
|
||||
|
||||
static int
|
||||
elanpex_match(device_t parent, struct cfdata *match, void *aux)
|
||||
{
|
||||
struct elansc_softc *sc = device_private(parent);
|
||||
|
||||
return sc->sc_pex == NULL;
|
||||
}
|
||||
|
||||
static int
|
||||
elanpar_match(device_t parent, struct cfdata *match, void *aux)
|
||||
{
|
||||
struct elansc_softc *sc = device_private(parent);
|
||||
|
||||
return sc->sc_par == NULL;
|
||||
}
|
||||
|
||||
CFATTACH_DECL_NEW(elanpar, sizeof(struct device),
|
||||
elanpar_match, elanpar_attach, elanpar_detach, NULL);
|
||||
|
||||
CFATTACH_DECL_NEW(elanpex, sizeof(struct device),
|
||||
elanpex_match, elanpex_attach, elanpex_detach, NULL);
|
||||
|
||||
CFATTACH_DECL2(elansc, sizeof(struct elansc_softc),
|
||||
elansc_match, elansc_attach, elansc_detach, NULL, NULL,
|
||||
elansc_childdetached);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user