diff --git a/sys/arch/arm/arm/cpufunc.c b/sys/arch/arm/arm/cpufunc.c index 55093e80d838..8e3a3c42767c 100644 --- a/sys/arch/arm/arm/cpufunc.c +++ b/sys/arch/arm/arm/cpufunc.c @@ -1,4 +1,4 @@ -/* $NetBSD: cpufunc.c,v 1.35 2002/03/24 15:37:46 bjh21 Exp $ */ +/* $NetBSD: cpufunc.c,v 1.36 2002/03/26 19:29:44 thorpej Exp $ */ /* * arm7tdmi support code Copyright (c) 2001 John Fremlin @@ -58,11 +58,24 @@ #include -#ifdef CPU_XSCALE +#ifdef CPU_XSCALE_80200 #include #include #endif +#ifdef CPU_XSCALE_80321 +#include +#include +#endif + +#if (defined(CPU_XSCALE_80200) + defined(CPU_XSCALE_80321)) > 1 +#error "Too many XScale core CPUs defined" +#endif + +#if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) +#include +#endif + /* PRIMARY CACHE VARIABLES */ int arm_picache_size; int arm_picache_line_size; @@ -487,7 +500,7 @@ struct cpu_functions sa110_cpufuncs = { }; #endif /* CPU_SA110 */ -#ifdef CPU_XSCALE +#if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) struct cpu_functions xscale_cpufuncs = { /* CPU functions */ @@ -542,7 +555,7 @@ struct cpu_functions xscale_cpufuncs = { xscale_setup /* cpu setup */ }; -#endif /* CPU_XSCALE */ +#endif /* CPU_XSCALE_80200 || CPU_XSCALE_80321 */ /* * Global constants also used by locore.s @@ -553,7 +566,7 @@ u_int cputype; u_int cpu_reset_needs_v4_MMU_disable; /* flag used in locore.s */ #if defined(CPU_ARM7TDMI) || defined(CPU_ARM8) || defined(CPU_ARM9) || \ - defined(CPU_XSCALE) + defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) static void get_cachetype_cp15 __P((void)); static void @@ -764,11 +777,17 @@ set_cpufuncs() return 0; } #endif /* CPU_SA110 */ -#ifdef CPU_XSCALE - if (cputype == CPU_ID_I80200) { +#if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) + if (cputype == CPU_ID_XSCALE) { +#if defined(CPU_XSCALE_80200) int rev = cpufunc_id() & CPU_ID_REVISION_MASK; +#endif - i80200_intr_init(); +#if defined(CPU_XSCALE_80200) + i80200_icu_init(); +#elif defined(CPU_XSCALE_80321) + i80321_icu_init(); +#endif /* * Reset the Performance Monitoring Unit to a @@ -782,7 +801,8 @@ set_cpufuncs() : "r" (PMNC_P|PMNC_C|PMNC_PMN0_IF|PMNC_PMN1_IF| PMNC_CC_IF)); -#ifdef XSCALE_CCLKCFG +#if defined(CPU_XSCALE_80200) +#if defined(XSCALE_CCLKCFG) /* * Crank CCLKCFG to maximum legal value. */ @@ -799,10 +819,12 @@ set_cpufuncs() __asm __volatile("mcr p13, 0, %0, c0, c1, 0" : : "r" (BCUCTL_E0|BCUCTL_E1|BCUCTL_EV)); +#endif /* CPU_XSCALE_80200 */ pte_cache_mode = PT_C; /* Select write-through cacheing. */ cpufuncs = xscale_cpufuncs; +#if defined(CPU_XSCALE_80200) /* * i80200 errata: Step-A0 and A1 have a bug where * D$ dirty bits are not cleared on "invalidate by @@ -812,12 +834,13 @@ set_cpufuncs() */ if (rev == 0 || rev == 1) cpufuncs.cf_dcache_inv_range = xscale_cache_purgeD_rng; +#endif /* CPU_XSCALE_80200 */ cpu_reset_needs_v4_MMU_disable = 1; /* XScale needs it */ get_cachetype_cp15(); return 0; } -#endif /* CPU_XSCALE */ +#endif /* CPU_XSCALE_80200 || CPU_XSCALE_80321 */ /* * Bzzzz. And the answer was ... */ @@ -1187,7 +1210,7 @@ late_abort_fixup(arg) #if defined(CPU_ARM6) || defined(CPU_ARM7) || defined(CPU_ARM7TDMI) || \ defined(CPU_ARM8) || defined (CPU_ARM9) || defined(CPU_SA110) || \ - defined(CPU_XSCALE) + defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) #define IGN 0 #define OR 1 @@ -1539,7 +1562,7 @@ sa110_setup(args) } #endif /* CPU_SA110 */ -#ifdef CPU_XSCALE +#if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) struct cpu_option xscale_options[] = { #ifdef COMPAT_12 { "branchpredict", BIC, OR, CPU_CONTROL_BPRD_ENABLE }, @@ -1601,4 +1624,4 @@ xscale_setup(args) __asm ("mcr p15, 0, %0, c1, c0, 1" :: "r" (0)); #endif } -#endif /* CPU_XSCALE */ +#endif /* CPU_XSCALE_80200 */ diff --git a/sys/arch/arm/arm32/cpu.c b/sys/arch/arm/arm32/cpu.c index 17ea6a981d3e..4b677c106bd7 100644 --- a/sys/arch/arm/arm32/cpu.c +++ b/sys/arch/arm/arm32/cpu.c @@ -1,4 +1,4 @@ -/* $NetBSD: cpu.c,v 1.30 2002/03/24 22:02:58 thorpej Exp $ */ +/* $NetBSD: cpu.c,v 1.31 2002/03/26 19:29:45 thorpej Exp $ */ /* * Copyright (c) 1995 Mark Brinicombe. @@ -46,7 +46,7 @@ #include -__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.30 2002/03/24 22:02:58 thorpej Exp $"); +__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.31 2002/03/26 19:29:45 thorpej Exp $"); #include #include @@ -198,7 +198,7 @@ static const char *sa1110_steppings[16] = { "rev 12", "rev 13", "rev 14", "rev 15", }; -static const char *i80200_steppings[16] = { +static const char *xscale_steppings[16] = { "step A-0", "step A-1", "step B-0", "step C-0", "rev 4", "rev 5", "rev 6", "rev 7", "rev 8", "rev 9", "rev 10", "rev 11", @@ -270,8 +270,8 @@ const struct cpuidtab cpuids[] = { { CPU_ID_SA1110, CPU_CLASS_SA1, "SA-1110", sa1110_steppings }, - { CPU_ID_I80200, CPU_CLASS_XSCALE, "i80200", - i80200_steppings }, + { CPU_ID_XSCALE, CPU_CLASS_XSCALE, "XScale", + xscale_steppings }, { CPU_ID_ARM1022ES, CPU_CLASS_ARM10E, "ARM1022ES", generic_steppings }, @@ -296,7 +296,7 @@ const struct cpu_classtab cpu_classes[] = { { "ARM9TDMI", NULL }, /* CPU_CLASS_ARM9TDMI */ { "ARM9E-S", NULL }, /* CPU_CLASS_ARM9ES */ { "SA-1", "CPU_SA110" }, /* CPU_CLASS_SA1 */ - { "XScale", "CPU_XSCALE" }, /* CPU_CLASS_XSCALE */ + { "XScale", "CPU_XSCALE_..." }, /* CPU_CLASS_XSCALE */ { "ARM10E", NULL }, /* CPU_CLASS_ARM10E */ }; @@ -446,7 +446,7 @@ identify_arm_cpu(struct device *dv, struct cpu_info *ci) #ifdef CPU_SA110 case CPU_CLASS_SA1: #endif -#ifdef CPU_XSCALE +#if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) case CPU_CLASS_XSCALE: #endif break; diff --git a/sys/arch/arm/conf/files.arm b/sys/arch/arm/conf/files.arm index 7f0e2d5e4585..d20e7413278b 100644 --- a/sys/arch/arm/conf/files.arm +++ b/sys/arch/arm/conf/files.arm @@ -1,4 +1,4 @@ -# $NetBSD: files.arm,v 1.55 2002/03/24 15:49:40 bjh21 Exp $ +# $NetBSD: files.arm,v 1.56 2002/03/26 19:29:45 thorpej Exp $ # temporary define to allow easy moving to ../arch/arm/arm32 defflag ARM32 @@ -7,7 +7,8 @@ defflag ARM32 defflag opt_cputypes.h CPU_ARM2 CPU_ARM250 CPU_ARM3 defflag opt_cputypes.h CPU_ARM6 CPU_ARM7 CPU_ARM7TDMI CPU_ARM8 CPU_ARM9 CPU_SA110 CPU_SA1100 CPU_SA1110 - CPU_XSCALE + CPU_XSCALE_80200 CPU_XSCALE_80321 + defparam opt_cpuoptions.h XSCALE_CCLKCFG @@ -65,10 +66,12 @@ file arch/arm/arm/cpufunc_asm_arm7tdmi.S cpu_arm7tdmi file arch/arm/arm/cpufunc_asm_arm8.S cpu_arm8 file arch/arm/arm/cpufunc_asm_arm9.S cpu_arm9 file arch/arm/arm/cpufunc_asm_armv4.S cpu_arm9 | cpu_sa110 | - cpu_xscale + cpu_xscale_80200 | + cpu_xscale_80321 file arch/arm/arm/cpufunc_asm_sa1.S cpu_sa110 file arch/arm/arm/cpufunc_asm_sa11x0.S cpu_sa110 # XXX -file arch/arm/arm/cpufunc_asm_xscale.S cpu_xscale +file arch/arm/arm/cpufunc_asm_xscale.S cpu_xscale_80200 | + cpu_xscale_80321 file arch/arm/arm/process_machdep.c file arch/arm/arm/procfs_machdep.c procfs file arch/arm/arm/sig_machdep.c diff --git a/sys/arch/arm/include/armreg.h b/sys/arch/arm/include/armreg.h index ba828bf8f844..8db00e2a169b 100644 --- a/sys/arch/arm/include/armreg.h +++ b/sys/arch/arm/include/armreg.h @@ -1,4 +1,4 @@ -/* $NetBSD: armreg.h,v 1.11 2002/03/16 14:41:17 bjh21 Exp $ */ +/* $NetBSD: armreg.h,v 1.12 2002/03/26 19:29:45 thorpej Exp $ */ /* * Copyright (c) 1998, 2001 Ben Harris @@ -187,7 +187,7 @@ #define CPU_ID_SA110 0x4401a100 #define CPU_ID_SA1100 0x4401a110 #define CPU_ID_SA1110 0x6901b110 -#define CPU_ID_I80200 0x69052000 /* XScale core */ +#define CPU_ID_XSCALE 0x69052000 /* XScale core */ #define CPU_ID_PXA250 0x69052100 #define CPU_ID_PXA210 0x69052120 diff --git a/sys/arch/arm/include/cpufunc.h b/sys/arch/arm/include/cpufunc.h index bd835e32a4d3..2f84bc503521 100644 --- a/sys/arch/arm/include/cpufunc.h +++ b/sys/arch/arm/include/cpufunc.h @@ -1,4 +1,4 @@ -/* $NetBSD: cpufunc.h,v 1.18 2002/01/30 00:36:32 thorpej Exp $ */ +/* $NetBSD: cpufunc.h,v 1.19 2002/03/26 19:29:45 thorpej Exp $ */ /* * Copyright (c) 1997 Mark Brinicombe. @@ -292,7 +292,8 @@ void arm9_context_switch __P((void)); void arm9_setup __P((char *string)); #endif -#if defined(CPU_ARM9) || defined(CPU_SA110) || defined(CPU_XSCALE) +#if defined(CPU_ARM9) || defined(CPU_SA110) || defined(CPU_XSCALE_80200) || \ + defined(CPU_XSCALE_80321) void armv4_tlb_flushID __P((void)); void armv4_tlb_flushI __P((void)); void armv4_tlb_flushD __P((void)); @@ -334,7 +335,7 @@ void sa110_context_switch __P((void)); void sa110_setup __P((char *string)); #endif /* CPU_SA110 */ -#ifdef CPU_XSCALE +#if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) void xscale_cpwait __P((void)); void xscale_cpu_sleep __P((int mode)); @@ -374,7 +375,7 @@ void xscale_cache_flushI_rng __P((vaddr_t start, vsize_t end)); void xscale_context_switch __P((void)); void xscale_setup __P((char *string)); -#endif /* CPU_XSCALE */ +#endif /* CPU_XSCALE_80200 || CPU_XSCALE_80321 */ #define tlb_flush cpu_tlb_flushID #define setttb cpu_setttb diff --git a/sys/arch/arm/xscale/i80200_icu.c b/sys/arch/arm/xscale/i80200_icu.c index ba158e2994b6..3d296eae05da 100644 --- a/sys/arch/arm/xscale/i80200_icu.c +++ b/sys/arch/arm/xscale/i80200_icu.c @@ -1,4 +1,4 @@ -/* $NetBSD: i80200_icu.c,v 1.3 2002/01/25 19:05:36 thorpej Exp $ */ +/* $NetBSD: i80200_icu.c,v 1.4 2002/03/26 19:29:46 thorpej Exp $ */ /* * Copyright (c) 2002 Wasabi Systems, Inc. @@ -61,12 +61,12 @@ i80200_default_extirq_dispatch(struct clockframe *framep) } /* - * i80200_intr_init: + * i80200_icu_init: * * Initialize the i80200 ICU. */ void -i80200_intr_init(void) +i80200_icu_init(void) { /* Disable all interrupt sources. */ diff --git a/sys/arch/arm/xscale/i80200reg.h b/sys/arch/arm/xscale/i80200reg.h index 09f3581dd711..d5d7932f6949 100644 --- a/sys/arch/arm/xscale/i80200reg.h +++ b/sys/arch/arm/xscale/i80200reg.h @@ -1,4 +1,4 @@ -/* $NetBSD: i80200reg.h,v 1.2 2002/01/23 20:58:29 thorpej Exp $ */ +/* $NetBSD: i80200reg.h,v 1.3 2002/03/26 19:29:46 thorpej Exp $ */ /* * Copyright (c) 2001 Wasabi Systems, Inc. @@ -92,28 +92,4 @@ #define ELOGx_ET_BA 0x40000000 /* bus abort */ #define ELOGx_RW 0x80000000 /* direction 0 = read 1 = write */ -/* - * Performance Monitoring Unit (CP14) - * - * CP14.0 Performance Monitor Control Register - * CP14.1 Clock Counter - * CP14.2 Performance Counter Register 0 - * CP14.3 Performance Counter Register 1 - */ - -#define PMNC_E 0x00000001 /* enable counters */ -#define PMNC_P 0x00000002 /* reset both PMNs to 0 */ -#define PMNC_C 0x00000004 /* clock counter reset */ -#define PMNC_D 0x00000008 /* clock counter / 64 */ -#define PMNC_PMN0_IE 0x00000010 /* enable PMN0 interrupt */ -#define PMNC_PMN1_IE 0x00000020 /* enable PMN1 interrupt */ -#define PMNC_CC_IE 0x00000040 /* enable clock counter interrupt */ -#define PMNC_PMN0_IF 0x00000100 /* PMN0 overflow/interrupt */ -#define PMNC_PMN1_IF 0x00000200 /* PMN1 overflow/interrupt */ -#define PMNC_CC_IF 0x00000400 /* clock counter overflow/interrupt */ -#define PMNC_EVCNT0_MASK 0x000ff000 /* event to count for PMN0 */ -#define PMNC_EVCNT0_SHIFT 12 -#define PMNC_EVCNT1_MASK 0x0ff00000 /* event to count for PMN1 */ -#define PMNC_EVCNT1_SHIFT 20 - #endif /* _ARM_XSCALE_I80200REG_H_ */ diff --git a/sys/arch/arm/xscale/i80200var.h b/sys/arch/arm/xscale/i80200var.h index ddffbac02344..d7d9af5681d3 100644 --- a/sys/arch/arm/xscale/i80200var.h +++ b/sys/arch/arm/xscale/i80200var.h @@ -1,4 +1,4 @@ -/* $NetBSD: i80200var.h,v 1.2 2002/01/24 01:12:40 thorpej Exp $ */ +/* $NetBSD: i80200var.h,v 1.3 2002/03/26 19:29:46 thorpej Exp $ */ /* * Copyright (c) 2002 Wasabi Systems, Inc. @@ -39,7 +39,7 @@ #define _ARM_XSCALE_I80200VAR_H_ /* i80200_icu.c */ -void i80200_intr_init(void); +void i80200_icu_init(void); void i80200_intr_enable(uint32_t); void i80200_intr_disable(uint32_t); diff --git a/sys/arch/arm/xscale/xscalereg.h b/sys/arch/arm/xscale/xscalereg.h new file mode 100644 index 000000000000..9749155c514d --- /dev/null +++ b/sys/arch/arm/xscale/xscalereg.h @@ -0,0 +1,69 @@ +/* $NetBSD: xscalereg.h,v 1.1 2002/03/26 19:29:46 thorpej Exp $ */ + +/* + * Copyright (c) 2001 Wasabi Systems, Inc. + * All rights reserved. + * + * Written by Jason R. Thorpe for Wasabi Systems, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed for the NetBSD Project by + * Wasabi Systems, Inc. + * 4. The name of Wasabi Systems, Inc. may not be used to endorse + * or promote products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _ARM_XSCALE_XSCALEREG_H_ +#define _ARM_XSCALE_XSCALEREG_H_ + +/* + * Register definitions for the Intel XScale processor core. + */ + +/* + * Performance Monitoring Unit (CP14) + * + * CP14.0 Performance Monitor Control Register + * CP14.1 Clock Counter + * CP14.2 Performance Counter Register 0 + * CP14.3 Performance Counter Register 1 + */ + +#define PMNC_E 0x00000001 /* enable counters */ +#define PMNC_P 0x00000002 /* reset both PMNs to 0 */ +#define PMNC_C 0x00000004 /* clock counter reset */ +#define PMNC_D 0x00000008 /* clock counter / 64 */ +#define PMNC_PMN0_IE 0x00000010 /* enable PMN0 interrupt */ +#define PMNC_PMN1_IE 0x00000020 /* enable PMN1 interrupt */ +#define PMNC_CC_IE 0x00000040 /* enable clock counter interrupt */ +#define PMNC_PMN0_IF 0x00000100 /* PMN0 overflow/interrupt */ +#define PMNC_PMN1_IF 0x00000200 /* PMN1 overflow/interrupt */ +#define PMNC_CC_IF 0x00000400 /* clock counter overflow/interrupt */ +#define PMNC_EVCNT0_MASK 0x000ff000 /* event to count for PMN0 */ +#define PMNC_EVCNT0_SHIFT 12 +#define PMNC_EVCNT1_MASK 0x0ff00000 /* event to count for PMN1 */ +#define PMNC_EVCNT1_SHIFT 20 + +#endif /* _ARM_XSCALE_XSCALEREG_H_ */ diff --git a/sys/arch/evbarm/conf/IQ80310 b/sys/arch/evbarm/conf/IQ80310 index e33ed1224ceb..d4256766d655 100644 --- a/sys/arch/evbarm/conf/IQ80310 +++ b/sys/arch/evbarm/conf/IQ80310 @@ -1,4 +1,4 @@ -# $NetBSD: IQ80310,v 1.10 2002/03/10 19:56:40 lukem Exp $ +# $NetBSD: IQ80310,v 1.11 2002/03/26 19:29:46 thorpej Exp $ # # IQ80310 -- Intel IQ80310 Evaluation Board Kernel # @@ -17,7 +17,7 @@ options RTC_OFFSET=0 # hardware clock is this many mins. west of GMT # CPU options # For StrongARM systems -options CPU_XSCALE # Support the XScale core +options CPU_XSCALE_80200 # Support the XScale core makeoptions COPTS="-O2 -march=armv4 -mtune=strongarm" #makeoptions COPTS="-O2 -march=armv5 -mtune=xscale" diff --git a/sys/arch/evbarm/conf/TEAMASA_NPWR b/sys/arch/evbarm/conf/TEAMASA_NPWR index 5036e65765a3..e1c822138894 100644 --- a/sys/arch/evbarm/conf/TEAMASA_NPWR +++ b/sys/arch/evbarm/conf/TEAMASA_NPWR @@ -1,4 +1,4 @@ -# $NetBSD: TEAMASA_NPWR,v 1.4 2002/03/10 19:56:40 lukem Exp $ +# $NetBSD: TEAMASA_NPWR,v 1.5 2002/03/26 19:29:46 thorpej Exp $ # # TEAMASA_NPWR -- Team ASA, Inc. Npwr -- XScale/IOP310-based # server appliance. @@ -19,7 +19,7 @@ options NTP # NTP phase/frequency locked loop # CPU options # For StrongARM systems -options CPU_XSCALE # Support the XScale core +options CPU_XSCALE_80200 # Support the XScale core makeoptions COPTS="-O2 -march=armv4 -mtune=strongarm" #makeoptions COPTS="-O2 -march=armv5 -mtune=xscale"