Define a message structure of inter-processor communication.
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@ -1,4 +1,4 @@
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/* $NetBSD: cpuvar.h,v 1.14 1998/09/22 13:39:19 pk Exp $ */
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/* $NetBSD: cpuvar.h,v 1.15 1998/10/08 22:25:42 pk Exp $ */
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/*
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* Copyright (c) 1996 The NetBSD Foundation, Inc.
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@ -40,6 +40,7 @@
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#define _sparc_cpuvar_h
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#include <sys/device.h>
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#include <sys/lock.h>
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#include <sparc/sparc/cache.h> /* for cacheinfo */
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@ -64,17 +65,55 @@ struct module_info {
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void (*get_syncflt)__P((void));
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int (*get_asyncflt)__P((u_int *, u_int *));
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void (*cache_flush)__P((caddr_t, u_int));
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void (*vcache_flush_page)__P((int));
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void (*vcache_flush_segment)__P((int, int));
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void (*vcache_flush_region)__P((int));
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void (*vcache_flush_context)__P((void));
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void (*sp_cache_flush)__P((caddr_t, u_int));
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void (*sp_vcache_flush_page)__P((int));
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void (*sp_vcache_flush_segment)__P((int, int));
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void (*sp_vcache_flush_region)__P((int));
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void (*sp_vcache_flush_context)__P((void));
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void (*pcache_flush_line)__P((int, int));
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void (*pure_vcache_flush)__P((void));
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void (*cache_flush_all)__P((void));
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void (*memerr)__P((unsigned, u_int, u_int, struct trapframe *));
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};
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struct xpmsg {
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struct simplelock lock;
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int tag;
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#define XPMSG_SAVEFPU 1
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#define XPMSG_DEMAP_TLB_PAGE 10
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#define XPMSG_DEMAP_TLB_SEGMENT 11
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#define XPMSG_DEMAP_TLB_REGION 12
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#define XPMSG_DEMAP_TLB_CONTEXT 13
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#define XPMSG_VCACHE_FLUSH_PAGE 20
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#define XPMSG_VCACHE_FLUSH_SEGMENT 21
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#define XPMSG_VCACHE_FLUSH_REGION 22
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#define XPMSG_VCACHE_FLUSH_CONTEXT 23
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#define XPMSG_VCACHE_FLUSH_RANGE 24
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union {
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struct xpmsg_flush_page {
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int ctx;
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int va;
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} xpmsg_flush_page;
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struct xpmsg_flush_segment {
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int ctx;
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int vr;
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int vs;
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} xpmsg_flush_segment;
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struct xpmsg_flush_region {
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int ctx;
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int vr;
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} xpmsg_flush_region;
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struct xpmsg_flush_context {
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int ctx;
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} xpmsg_flush_context;
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struct xpmsg_flush_range {
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int ctx;
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caddr_t va;
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int size;
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} xpmsg_flush_range;
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} u;
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};
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/*
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* The cpuinfo structure. This structure maintains information about one
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@ -95,13 +134,13 @@ struct cpu_info {
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int mmu_vers; /* MMU version code */
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int master; /* 1 if this is bootup CPU */
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int cpu_no; /* CPU index (see cpus[] array) */
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int mid; /* Module ID for MP systems */
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int mbus; /* 1 if CPU is on MBus */
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int mxcc; /* 1 if a MBus-level MXCC is present */
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caddr_t mailbox; /* VA of CPU's mailbox */
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int mmu_ncontext; /* Number of contexts supported */
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int mmu_nregion; /* Number of regions supported */
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int mmu_nsegment; /* [4/4c] Segments */
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@ -148,6 +187,9 @@ struct cpu_info {
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/* Per processor interrupt mask register (sun4m only) */
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struct icr_pi *intreg_4m;
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#define raise_ipi(cpi) do { \
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(cpi)->intreg_4m->pi_set = PINTR_SINTRLEV(15); \
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} while (0)
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/*
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* The following pointers point to processes that are somehow
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@ -180,13 +222,25 @@ struct cpu_info {
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int sfva;
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} syncfltdump;
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/* Cache handling functions */
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/*
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* Cache handling functions.
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* Most cache flush function come in two flavours: one that
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* acts only on the CPU it executes on, and another that
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* uses inter-processor signals to flush the cache on
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* all processor modules.
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*/
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void (*cache_enable) __P((void));
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void (*cache_flush)__P((caddr_t, u_int));
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void (*sp_cache_flush)__P((caddr_t, u_int));
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void (*vcache_flush_page)__P((int));
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void (*sp_vcache_flush_page)__P((int));
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void (*vcache_flush_segment)__P((int, int));
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void (*sp_vcache_flush_segment)__P((int, int));
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void (*vcache_flush_region)__P((int));
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void (*sp_vcache_flush_region)__P((int));
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void (*vcache_flush_context)__P((void));
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void (*sp_vcache_flush_context)__P((void));
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void (*pcache_flush_line)__P((int, int));
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void (*pure_vcache_flush)__P((void));
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void (*cache_flush_all)__P((void));
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@ -206,6 +260,9 @@ struct cpu_info {
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* unrecoverable faults end up here.
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*/
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void (*memerr)__P((unsigned, u_int, u_int, struct trapframe *));
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/* Inter-processor message area */
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struct xpmsg msg;
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};
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/*
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@ -288,7 +345,7 @@ void getcpuinfo __P((struct cpu_info *sc, int node));
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void mmu_install_tables __P((struct cpu_info *));
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void pmap_alloc_cpu __P((struct cpu_info *));
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extern struct cpu_info *cpus[];
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extern struct cpu_info **cpus;
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#define cpuinfo (*(struct cpu_info *)CPUINFO_VA)
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