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Fix the use of the contiguous bit by checking the output address as well.

This commit is contained in:
skrll 2020-11-07 08:48:11 +00:00
parent f91c082fda
commit 4135af567b
1 changed files with 15 additions and 9 deletions
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24
sys/arch/aarch64/aarch64/pmapboot.c
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@ -1,4 +1,4 @@
/* $NetBSD: pmapboot.c,v 1.10 2020/07/17 07:21:44 ryo Exp $ */
/* $NetBSD: pmapboot.c,v 1.11 2020/11/07 08:48:11 skrll Exp $ */
/*
* Copyright (c) 2018 Ryo Shimizu <ryo@nerv.org>
@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: pmapboot.c,v 1.10 2020/07/17 07:21:44 ryo Exp $");
__KERNEL_RCSID(0, "$NetBSD: pmapboot.c,v 1.11 2020/11/07 08:48:11 skrll Exp $");
#include "opt_arm_debug.h"
#include "opt_ddb.h"
@ -46,7 +46,6 @@ __KERNEL_RCSID(0, "$NetBSD: pmapboot.c,v 1.10 2020/07/17 07:21:44 ryo Exp $");
#include <aarch64/pmap.h>
#include <aarch64/pte.h>
#define OPTIMIZE_TLB_CONTIG
static void
@ -180,16 +179,23 @@ pmapboot_pte_print(pt_entry_t pte, int level,
#ifdef OPTIMIZE_TLB_CONTIG
static inline bool
tlb_contiguous_p(vaddr_t addr, vaddr_t start, vaddr_t end, vsize_t blocksize)
tlb_contiguous_p(vaddr_t va, paddr_t pa, vaddr_t start, vaddr_t end,
vsize_t blocksize)
{
/*
* when using 4KB granule, 16 adjacent and aligned entries can be
* unified to one TLB cache entry.
* in other size of granule, not supported.
*/
if (((addr & ~((blocksize << 4) - 1)) >= start) &&
((addr | ((blocksize << 4) - 1)) <= end))
const vaddr_t mask = (blocksize << 4) - 1;
/* if the output address doesn't align it can't be contiguous */
if ((va & mask) != (pa & mask))
return false;
if ((va & ~mask) >= start && (va | mask) <= end)
return true;
return false;
}
#endif /* OPTIMIZE_TLB_CONTIG */
@ -288,7 +294,7 @@ pmapboot_enter(vaddr_t va, paddr_t pa, psize_t size, psize_t blocksize,
#endif
attr;
#ifdef OPTIMIZE_TLB_CONTIG
if (tlb_contiguous_p(va, va_start, va_end, blocksize))
if (tlb_contiguous_p(va, pa, va_start, va_end, blocksize))
pte |= LX_BLKPAG_CONTIG;
ll = l1;
llidx = idx1;
@ -333,7 +339,7 @@ pmapboot_enter(vaddr_t va, paddr_t pa, psize_t size, psize_t blocksize,
#endif
attr;
#ifdef OPTIMIZE_TLB_CONTIG
if (tlb_contiguous_p(va, va_start, va_end, blocksize))
if (tlb_contiguous_p(va, pa, va_start, va_end, blocksize))
pte |= LX_BLKPAG_CONTIG;
ll = l2;
llidx = idx2;
@ -377,7 +383,7 @@ pmapboot_enter(vaddr_t va, paddr_t pa, psize_t size, psize_t blocksize,
#endif
attr;
#ifdef OPTIMIZE_TLB_CONTIG
if (tlb_contiguous_p(va, va_start, va_end, blocksize))
if (tlb_contiguous_p(va, pa, va_start, va_end, blocksize))
pte |= LX_BLKPAG_CONTIG;
ll = l3;
llidx = idx3;