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finish conversion to the common m68k cacheops: 

add support for machine-specific flavors of the ops for off-chip caches.
many thanks to Izumi Tsutsui for his help with this.
This commit is contained in:
chs 2002-11-02 20:03:04 +00:00
parent c27faa29c9
commit 40e5b8394f
16 changed files with 511 additions and 1152 deletions
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97
sys/arch/amiga/amiga/locore.s
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@ -1,4 +1,4 @@
/* $NetBSD: locore.s,v 1.131 2002/02/13 16:34:05 is Exp $ */ /* $NetBSD: locore.s,v 1.132 2002/11/02 20:03:04 chs Exp $ */
/* /*
* Copyright (c) 1988 University of Utah. * Copyright (c) 1988 University of Utah.
@ -948,8 +948,7 @@ Lunshadow:
#endif #endif
/* flush TLB and turn on caches */ /* flush TLB and turn on caches */
jbsr _C_LABEL(_TBIA) | invalidate TLB
jbsr _ASM_LABEL(__TBIA) | invalidate TLB
movl #CACHE_ON,%d0 movl #CACHE_ON,%d0
tstl %d5 tstl %d5
jeq Lcacheon jeq Lcacheon
@ -1389,98 +1388,6 @@ Lsavedone:
moveq #0,%d0 | return 0 moveq #0,%d0 | return 0
rts rts
/*
* Copy 1 relocation unit (NBPG bytes)
* from user virtual address to physical address
*/
ENTRY(copyseg)
movl _C_LABEL(curpcb),%a1 | current pcb
movl #Lcpydone,%a1@(PCB_ONFAULT) | where to return to on a fault
movl %sp@(8),%d0 | destination page number
moveq #PGSHIFT,%d1
lsll %d1,%d0 | convert to address
orl #PG_CI+PG_RW+PG_V,%d0 | make sure valid and writable
movl _C_LABEL(CMAP2),%a0
movl _C_LABEL(CADDR2),%sp@- | destination kernel VA
movl %d0,%a0@ | load in page table
jbsr _ASM_LABEL(__TBIS) | invalidate any old mapping
addql #4,%sp
movl _C_LABEL(CADDR2),%a1 | destination addr
movl %sp@(4),%a0 | source addr
movl #NBPG/4-1,%d0 | count
Lcpyloop:
movsl %a0@+,%d1 | read longword
movl %d1,%a1@+ | write longword
dbf %d0,Lcpyloop | continue until done
Lcpydone:
movl _C_LABEL(curpcb),%a1 | current pcb
clrl %a1@(PCB_ONFAULT) | clear error catch
rts
/*
* Invalidate entire TLB.
*/
ASLOCAL(__TBIA)
cmpl #MMU_68040,_C_LABEL(mmutype)
jeq Ltbia040
tstl _C_LABEL(mmutype)
jpl Lmc68851a | 68851 implies no d-cache
pflusha | flush entire TLB
movl #DC_CLEAR,%d0
movc %d0,%cacr | invalidate on-chip d-cache
rts
Lmc68851a:
pflusha
rts
Ltbia040:
.word 0xf518 | pflusha
#ifdef M68060
cmpl #CPU_68060,_C_LABEL(cputype)
jne Ltbiano60
movc %cacr,%d0
orl #IC60_CABC,%d0 | and clear all btc entries
movc %d0,%cacr
#endif
Ltbiano60:
rts
/*
* Invalidate any TLB entry for given VA (TB Invalidate Single)
*/
ASLOCAL(__TBIS)
#ifdef DEBUG
tstl _ASM_LABEL(fulltflush) | being conservative?
jne _ASM_LABEL(__TBIA) | yes, flush entire TLB
#endif
movl %sp@(4),%a0 | get addr to flush
cmpl #MMU_68040,_C_LABEL(mmutype)
jeq Ltbis040
tstl _C_LABEL(mmutype)
jpl Lmc68851b | is 68851?
pflush #0,#0,%a0@ | flush address from both sides
movl #DC_CLEAR,%d0
movc %d0,%cacr | invalidate on-chip data cache
rts
Lmc68851b:
pflushs #0,#0,%a0@ | flush address from both sides
rts
Ltbis040:
moveq #FC_SUPERD,%d0 | select supervisor
movc %d0,%dfc
.word 0xf508 | pflush a0@
moveq #FC_USERD,%d0 | select user
movc %d0,%dfc
.word 0xf508 | pflush a0@
#ifdef M68060
cmpl #CPU_68060,_C_LABEL(cputype)
jne Ltbisno60
movc %cacr,%d0
orl #IC60_CABC,%d0 | and clear all btc entries
movc %d0,%cacr
Ltbisno60:
#endif
rts
ENTRY(ecacheon) ENTRY(ecacheon)
rts rts

96
sys/arch/atari/atari/locore.s
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@ -1,4 +1,4 @@
/* $NetBSD: locore.s,v 1.88 2002/05/23 06:08:40 leo Exp $ */ /* $NetBSD: locore.s,v 1.89 2002/11/02 20:03:04 chs Exp $ */
/* /*
* Copyright (c) 1988 University of Utah. * Copyright (c) 1988 University of Utah.
@ -973,7 +973,7 @@ Lend_cpuset:
clrw %a1@(PCB_FLAGS) | clear flags clrw %a1@(PCB_FLAGS) | clear flags
/* flush TLB and turn on caches */ /* flush TLB and turn on caches */
jbsr _C_LABEL(TBIA) | invalidate TLB jbsr _C_LABEL(_TBIA) | invalidate TLB
movl #CACHE_ON,%d0 movl #CACHE_ON,%d0
cmpl #MMU_68040,_C_LABEL(mmutype) cmpl #MMU_68040,_C_LABEL(mmutype)
jne Lcacheon jne Lcacheon
@ -1418,98 +1418,6 @@ Lsldone:
rts rts
#endif /* defined(M68040) */ #endif /* defined(M68040) */
/*
* Copy 1 relocation unit (NBPG bytes)
* from user virtual address to physical address
*/
ENTRY(copyseg)
movl _C_LABEL(curpcb),%a1 | current pcb
movl #Lcpydone,%a1@(PCB_ONFAULT) | where to return to on a fault
movl %sp@(8),%d0 | destination page number
moveq #PGSHIFT,%d1
lsll %d1,%d0 | convert to address
orl #PG_CI+PG_RW+PG_V,%d0 | make sure valid and writable
movl _C_LABEL(CMAP2),%a0
movl _C_LABEL(CADDR2),%sp@- | destination kernel VA
movl %d0,%a0@ | load in page table
jbsr _C_LABEL(TBIS) | invalidate any old mapping
addql #4,%sp
movl _C_LABEL(CADDR2),%a1 | destination addr
movl %sp@(4),%a0 | source addr
movl #NBPG/4-1,%d0 | count
Lcpyloop:
movsl %a0@+,%d1 | read longword
movl %d1,%a1@+ | write longword
dbf %d0,Lcpyloop | continue until done
Lcpydone:
movl _C_LABEL(curpcb),%a1 | current pcb
clrl %a1@(PCB_ONFAULT) | clear error catch
rts
/*
* Invalidate entire TLB.
*/
ENTRY(TBIA)
Ltbia:
cmpl #MMU_68040,_C_LABEL(mmutype)
jeq Ltbia040
pflusha | flush entire TLB
tstl _C_LABEL(mmutype)
jpl Lmc68851a | 68851 implies no d-cache
movl #DC_CLEAR,%d0
movc %d0,%cacr | invalidate on-chip d-cache
Lmc68851a:
rts
Ltbia040:
.word 0xf518 | pflusha
#ifdef M68060
cmpl #CPU_68060,_C_LABEL(cputype)
jne Ltbiano60 | No 060 -> no branch cache
movc %cacr,%d0
orl #IC60_CABC,%d0 | and clear all branch cache entries
movc %d0,%cacr
Ltbiano60:
#endif
rts
/*
* Invalidate any TLB entry for given VA (TB Invalidate Single)
*/
ENTRY(TBIS)
#ifdef DEBUG
tstl fulltflush | being conservative?
jne Ltbia | yes, flush entire TLB
#endif
movl %sp@(4),%a0 | get addr to flush
cmpl #MMU_68040,_C_LABEL(mmutype)
jeq Ltbis040
tstl _C_LABEL(mmutype)
jpl Lmc68851b | is 68851?
pflush #0,#0,%a0@ | flush address from both sides
movl #DC_CLEAR,%d0
movc %d0,%cacr | invalidate on-chip data cache
rts
Lmc68851b:
pflushs #0,#0,%a0@ | flush address from both sides
rts
Ltbis040:
moveq #FC_SUPERD,%d0 | select supervisor
movc %d0,%dfc
.word 0xf508 | pflush a0@
moveq #FC_USERD,%d0 | select user
movc %d0,%dfc
.word 0xf508 | pflush a0@
#if defined(M68060)
cmpl #CPU_68060,_C_LABEL(cputype)
jne Ltbisnot060 | no 060, no branch cache
movc %cacr,%d0
orl #IC60_CABC,%d0 | and clear all branch cache entries
movc %d0,%cacr
Ltbisnot060:
#endif /* defined(M68060) */
rts
ENTRY(ecacheon) ENTRY(ecacheon)
rts rts

295
sys/arch/cesfic/cesfic/locore.s
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@ -1,4 +1,4 @@
/* $NetBSD: locore.s,v 1.5 2002/05/19 21:34:16 jdolecek Exp $ */ /* $NetBSD: locore.s,v 1.6 2002/11/02 20:03:05 chs Exp $ */
/* /*
* Copyright (c) 1994, 1995 Gordon W. Ross * Copyright (c) 1994, 1995 Gordon W. Ross
@ -315,7 +315,7 @@ Lenab1:
Lenab2: Lenab2:
/* flush TLB and turn on caches */ /* flush TLB and turn on caches */
jbsr _C_LABEL(TBIA) | invalidate TLB jbsr _C_LABEL(_TBIA) | invalidate TLB
cmpl #MMU_68040,_C_LABEL(mmutype) | 68040? cmpl #MMU_68040,_C_LABEL(mmutype) | 68040?
jeq Lnocache0 | yes, cache already on jeq Lnocache0 | yes, cache already on
movl #CACHE_ON,%d0 movl #CACHE_ON,%d0
@ -1153,297 +1153,6 @@ Lsldone:
rts rts
#endif #endif
/*
* Invalidate entire TLB.
*/
ENTRY(TBIA)
_C_LABEL(_TBIA):
#if defined(M68040)
cmpl #MMU_68040,_C_LABEL(mmutype) | 68040?
jne Lmotommu3 | no, skip
.word 0xf518 | yes, pflusha
rts
Lmotommu3:
#endif
#if defined(M68K_MMU_MOTOROLA)
tstl _C_LABEL(mmutype) | HP MMU?
jeq Lhpmmu6 | yes, skip
pflusha | flush entire TLB
jpl Lmc68851a | 68851 implies no d-cache
movl #DC_CLEAR,%d0
movc %d0,%cacr | invalidate on-chip d-cache
Lmc68851a:
rts
Lhpmmu6:
#endif
#if defined(M68K_MMU_HP)
MMUADDR(%a0)
movl %a0@(MMUTBINVAL),%sp@- | do not ask me, this
addql #4,%sp | is how hpux does it
#ifdef DEBUG
tstl _ASM_LABEL(fullcflush)
jne _C_LABEL(_DCIA) | XXX: invalidate entire cache
#endif
#endif
rts
/*
* Invalidate any TLB entry for given VA (TB Invalidate Single)
*/
ENTRY(TBIS)
#ifdef DEBUG
tstl _ASM_LABEL(fulltflush) | being conservative?
jne _C_LABEL(_TBIA) | yes, flush entire TLB
#endif
#if defined(M68040)
cmpl #MMU_68040,_C_LABEL(mmutype) | 68040?
jne Lmotommu4 | no, skip
movl %sp@(4),%a0
movc %dfc,%d1
moveq #1,%d0 | user space
movc %d0,%dfc
.word 0xf508 | pflush %a0@
moveq #5,%d0 | super space
movc %d0,%dfc
.word 0xf508 | pflush %a0@
movc %d1,%dfc
rts
Lmotommu4:
#endif
#if defined(M68K_MMU_MOTOROLA)
tstl _C_LABEL(mmutype) | HP MMU?
jeq Lhpmmu5 | yes, skip
movl %sp@(4),%a0 | get addr to flush
jpl Lmc68851b | is 68851?
pflush #0,#0,%a0@ | flush address from both sides
movl #DC_CLEAR,%d0
movc %d0,%cacr | invalidate on-chip data cache
rts
Lmc68851b:
pflushs #0,#0,%a0@ | flush address from both sides
rts
Lhpmmu5:
#endif
#if defined(M68K_MMU_HP)
movl %sp@(4),%d0 | VA to invalidate
bclr #0,%d0 | ensure even
movl %d0,%a0
movw %sr,%d1 | go critical
movw #PSL_HIGHIPL,%sr | while in purge space
moveq #FC_PURGE,%d0 | change address space
movc %d0,%dfc | for destination
moveq #0,%d0 | zero to invalidate?
movsl %d0,%a0@ | hit it
moveq #FC_USERD,%d0 | back to old
movc %d0,%dfc | address space
movw %d1,%sr | restore IPL
#endif
rts
/*
* Invalidate supervisor side of TLB
*/
ENTRY(TBIAS)
#ifdef DEBUG
tstl _ASM_LABEL(fulltflush) | being conservative?
jne _C_LABEL(_TBIA) | yes, flush everything
#endif
#if defined(M68040)
cmpl #MMU_68040,_C_LABEL(mmutype) | 68040?
jne Lmotommu5 | no, skip
.word 0xf518 | yes, pflusha (for now) XXX
rts
Lmotommu5:
#endif
#if defined(M68K_MMU_MOTOROLA)
tstl _C_LABEL(mmutype) | HP MMU?
jeq Lhpmmu7 | yes, skip
jpl Lmc68851c | 68851?
pflush #4,#4 | flush supervisor TLB entries
movl #DC_CLEAR,%d0
movc %d0,%cacr | invalidate on-chip d-cache
rts
Lmc68851c:
pflushs #4,#4 | flush supervisor TLB entries
rts
Lhpmmu7:
#endif
#if defined(M68K_MMU_HP)
MMUADDR(%a0)
movl #0x8000,%d0 | more
movl %d0,%a0@(MMUTBINVAL) | HP magic
#ifdef DEBUG
tstl _ASM_LABEL(fullcflush)
jne _C_LABEL(_DCIS) | XXX: invalidate entire sup. cache
#endif
#endif
rts
/*
* Invalidate user side of TLB
*/
ENTRY(TBIAU)
#ifdef DEBUG
tstl _ASM_LABEL(fulltflush) | being conservative?
jne _C_LABEL(_TBIA) | yes, flush everything
#endif
#if defined(M68040)
cmpl #MMU_68040,_C_LABEL(mmutype) | 68040?
jne Lmotommu6 | no, skip
.word 0xf518 | yes, pflusha (for now) XXX
rts
Lmotommu6:
#endif
#if defined(M68K_MMU_MOTOROLA)
tstl _C_LABEL(mmutype) | HP MMU?
jeq Lhpmmu8 | yes, skip
jpl Lmc68851d | 68851?
pflush #0,#4 | flush user TLB entries
movl #DC_CLEAR,%d0
movc %d0,%cacr | invalidate on-chip d-cache
rts
Lmc68851d:
pflushs #0,#4 | flush user TLB entries
rts
Lhpmmu8:
#endif
#if defined(M68K_MMU_HP)
MMUADDR(%a0)
moveq #0,%d0 | more
movl %d0,%a0@(MMUTBINVAL) | HP magic
#ifdef DEBUG
tstl _ASM_LABEL(fullcflush)
jne _C_LABEL(_DCIU) | XXX: invalidate entire user cache
#endif
#endif
rts
/*
* Invalidate instruction cache
*/
ENTRY(ICIA)
#if defined(M68040)
ENTRY(ICPA)
cmpl #MMU_68040,_C_LABEL(mmutype) | 68040
jne Lmotommu7 | no, skip
.word 0xf498 | cinva ic
rts
Lmotommu7:
#endif
movl #IC_CLEAR,%d0
movc %d0,%cacr | invalidate i-cache
rts
/*
* Invalidate data cache.
* HP external cache allows for invalidation of user/supervisor portions.
* NOTE: we do not flush 68030 on-chip cache as there are no aliasing
* problems with DC_WA. The only cases we have to worry about are context
* switch and TLB changes, both of which are handled "in-line" in resume
* and TBI*.
*/
ENTRY(DCIA)
__DCIA:
#if defined(M68040)
cmpl #MMU_68040,_C_LABEL(mmutype) | 68040
jne Lmotommu8 | no, skip
/* XXX implement */
rts
Lmotommu8:
#endif
#if defined(M68K_MMU_HP)
tstl _C_LABEL(ectype) | got external VAC?
jle Lnocache2 | no, all done
MMUADDR(%a0)
andl #~MMU_CEN,%a0@(MMUCMD) | disable cache in MMU control reg
orl #MMU_CEN,%a0@(MMUCMD) | reenable cache in MMU control reg
Lnocache2:
#endif
rts
ENTRY(DCIS)
_C_LABEL(_DCIS):
#if defined(M68040)
cmpl #MMU_68040,_C_LABEL(mmutype) | 68040
jne Lmotommu9 | no, skip
/* XXX implement */
rts
Lmotommu9:
#endif
#if defined(M68K_MMU_HP)
tstl _C_LABEL(ectype) | got external VAC?
jle Lnocache3 | no, all done
MMUADDR(%a0)
movl %a0@(MMUSSTP),%d0 | read the supervisor STP
movl %d0,%a0@(MMUSSTP) | write it back
Lnocache3:
#endif
rts
ENTRY(DCIU)
_C_LABEL(_DCIU):
#if defined(M68040)
cmpl #MMU_68040,_C_LABEL(mmutype) | 68040
jne LmotommuA | no, skip
/* XXX implement */
rts
LmotommuA:
#endif
#if defined(M68K_MMU_HP)
tstl _C_LABEL(ectype) | got external VAC?
jle Lnocache4 | no, all done
MMUADDR(%a0)
movl %a0@(MMUUSTP),%d0 | read the user STP
movl %d0,%a0@(MMUUSTP) | write it back
Lnocache4:
#endif
rts
#if defined(M68040)
ENTRY(ICPL)
movl %sp@(4),%a0 | address
.word 0xf488 | cinvl ic,%a0@
rts
ENTRY(ICPP)
movl %sp@(4),%a0 | address
.word 0xf490 | cinvp ic,%a0@
rts
ENTRY(DCPL)
movl %sp@(4),%a0 | address
.word 0xf448 | cinvl dc,%a0@
rts
ENTRY(DCPP)
movl %sp@(4),%a0 | address
.word 0xf450 | cinvp dc,%a0@
rts
ENTRY(DCPA)
.word 0xf458 | cinva dc
rts
ENTRY(DCFL)
movl %sp@(4),%a0 | address
.word 0xf468 | cpushl dc,%a0@
rts
ENTRY(DCFP)
movl %sp@(4),%a0 | address
.word 0xf470 | cpushp dc,%a0@
rts
#endif
ENTRY(PCIA)
#if defined(M68040)
ENTRY(DCFA)
cmpl #MMU_68040,_C_LABEL(mmutype) | 68040
jne LmotommuB | no, skip
.word 0xf478 | cpusha dc
rts
LmotommuB:
#endif
#if defined(M68K_MMU_MOTOROLA)
movl #DC_CLEAR,%d0
movc %d0,%cacr | invalidate on-chip d-cache
#endif
rts
ENTRY_NOPROFILE(getsfc) ENTRY_NOPROFILE(getsfc)
movc %sfc,%d0 movc %sfc,%d0
rts rts

3
sys/arch/cesfic/conf/files.cesfic
View File

@ -1,4 +1,4 @@
# $NetBSD: files.cesfic,v 1.6 2002/10/26 13:50:25 jdolecek Exp $ # $NetBSD: files.cesfic,v 1.7 2002/11/02 20:03:05 chs Exp $
# #
# cesfic-specific configuration info # cesfic-specific configuration info
@ -58,6 +58,7 @@ file arch/cesfic/cesfic/pmap.c
file arch/cesfic/cesfic/pmap_bootstrap.c file arch/cesfic/cesfic/pmap_bootstrap.c
file arch/cesfic/cesfic/sys_machdep.c file arch/cesfic/cesfic/sys_machdep.c
file arch/cesfic/cesfic/trap.c file arch/cesfic/cesfic/trap.c
file arch/m68k/m68k/cacheops.c
file arch/m68k/m68k/vm_machdep.c file arch/m68k/m68k/vm_machdep.c
file dev/cons.c file dev/cons.c

301
sys/arch/hp300/hp300/locore.s
View File

@ -1,4 +1,4 @@
/* $NetBSD: locore.s,v 1.124 2002/08/28 08:57:00 gmcgarry Exp $ */ /* $NetBSD: locore.s,v 1.125 2002/11/02 20:03:05 chs Exp $ */
/* /*
* Copyright (c) 1994, 1995 Gordon W. Ross * Copyright (c) 1994, 1995 Gordon W. Ross
@ -512,7 +512,7 @@ Lenab1:
addql #4,%sp addql #4,%sp
Lenab2: Lenab2:
/* flush TLB and turn on caches */ /* flush TLB and turn on caches */
jbsr _C_LABEL(TBIA) | invalidate TLB jbsr _C_LABEL(_TBIA) | invalidate TLB
cmpl #MMU_68040,_C_LABEL(mmutype) | 68040? cmpl #MMU_68040,_C_LABEL(mmutype) | 68040?
jeq Lnocache0 | yes, cache already on jeq Lnocache0 | yes, cache already on
movl #CACHE_ON,%d0 movl #CACHE_ON,%d0
@ -1481,303 +1481,6 @@ Lsldone:
rts rts
#endif #endif
/*
* Invalidate entire TLB.
*/
ENTRY(TBIA)
_C_LABEL(_TBIA):
#if defined(M68040)
cmpl #MMU_68040,_C_LABEL(mmutype) | 68040?
jne Lmotommu3 | no, skip
.word 0xf518 | yes, pflusha
rts
Lmotommu3:
#endif
#if defined(M68K_MMU_MOTOROLA)
tstl _C_LABEL(mmutype) | HP MMU?
jeq Lhpmmu6 | yes, skip
pflusha | flush entire TLB
jpl Lmc68851a | 68851 implies no d-cache
movl #DC_CLEAR,%d0
movc %d0,%cacr | invalidate on-chip d-cache
Lmc68851a:
rts
Lhpmmu6:
#endif
#if defined(M68K_MMU_HP)
MMUADDR(%a0)
movl %a0@(MMUTBINVAL),%sp@- | do not ask me, this
addql #4,%sp | is how hpux does it
#ifdef DEBUG
tstl _ASM_LABEL(fullcflush)
jne _C_LABEL(_DCIA) | XXX: invalidate entire cache
#endif
#endif
rts
/*
* Invalidate any TLB entry for given VA (TB Invalidate Single)
*/
ENTRY(TBIS)
#ifdef DEBUG
tstl _ASM_LABEL(fulltflush) | being conservative?
jne _C_LABEL(_TBIA) | yes, flush entire TLB
#endif
#if defined(M68040)
cmpl #MMU_68040,_C_LABEL(mmutype) | 68040?
jne Lmotommu4 | no, skip
movl %sp@(4),%a0
movc %dfc,%d1
moveq #1,%d0 | user space
movc %d0,%dfc
.word 0xf508 | pflush %a0@
moveq #5,%d0 | super space
movc %d0,%dfc
.word 0xf508 | pflush %a0@
movc %d1,%dfc
rts
Lmotommu4:
#endif
#if defined(M68K_MMU_MOTOROLA)
tstl _C_LABEL(mmutype) | HP MMU?
jeq Lhpmmu5 | yes, skip
movl %sp@(4),%a0 | get addr to flush
jpl Lmc68851b | is 68851?
pflush #0,#0,%a0@ | flush address from both sides
movl #DC_CLEAR,%d0
movc %d0,%cacr | invalidate on-chip data cache
rts
Lmc68851b:
pflushs #0,#0,%a0@ | flush address from both sides
rts
Lhpmmu5:
#endif
#if defined(M68K_MMU_HP)
movl %sp@(4),%d0 | VA to invalidate
bclr #0,%d0 | ensure even
movl %d0,%a0
movw %sr,%d1 | go critical
movw #PSL_HIGHIPL,%sr | while in purge space
moveq #FC_PURGE,%d0 | change address space
movc %d0,%dfc | for destination
moveq #0,%d0 | zero to invalidate?
movsl %d0,%a0@ | hit it
moveq #FC_USERD,%d0 | back to old
movc %d0,%dfc | address space
movw %d1,%sr | restore IPL
#endif
rts
/*
* Invalidate supervisor side of TLB
*/
ENTRY(TBIAS)
#ifdef DEBUG
tstl _ASM_LABEL(fulltflush) | being conservative?
jne _C_LABEL(_TBIA) | yes, flush everything
#endif
#if defined(M68040)
cmpl #MMU_68040,_C_LABEL(mmutype) | 68040?
jne Lmotommu5 | no, skip
.word 0xf518 | yes, pflusha (for now) XXX
rts
Lmotommu5:
#endif
#if defined(M68K_MMU_MOTOROLA)
tstl _C_LABEL(mmutype) | HP MMU?
jeq Lhpmmu7 | yes, skip
jpl Lmc68851c | 68851?
pflush #4,#4 | flush supervisor TLB entries
movl #DC_CLEAR,%d0
movc %d0,%cacr | invalidate on-chip d-cache
rts
Lmc68851c:
pflushs #4,#4 | flush supervisor TLB entries
rts
Lhpmmu7:
#endif
#if defined(M68K_MMU_HP)
MMUADDR(%a0)
movl #0x8000,%d0 | more
movl %d0,%a0@(MMUTBINVAL) | HP magic
#ifdef DEBUG
tstl _ASM_LABEL(fullcflush)
jne _C_LABEL(_DCIS) | XXX: invalidate entire sup. cache
#endif
#endif
rts
/*
* Invalidate user side of TLB
*/
ENTRY(TBIAU)
#ifdef DEBUG
tstl _ASM_LABEL(fulltflush) | being conservative?
jne _C_LABEL(_TBIA) | yes, flush everything
#endif
#if defined(M68040)
cmpl #MMU_68040,_C_LABEL(mmutype) | 68040?
jne Lmotommu6 | no, skip
.word 0xf518 | yes, pflusha (for now) XXX
rts
Lmotommu6:
#endif
#if defined(M68K_MMU_MOTOROLA)
tstl _C_LABEL(mmutype) | HP MMU?
jeq Lhpmmu8 | yes, skip
jpl Lmc68851d | 68851?
pflush #0,#4 | flush user TLB entries
movl #DC_CLEAR,%d0
movc %d0,%cacr | invalidate on-chip d-cache
rts
Lmc68851d:
pflushs #0,#4 | flush user TLB entries
rts
Lhpmmu8:
#endif
#if defined(M68K_MMU_HP)
MMUADDR(%a0)
moveq #0,%d0 | more
movl %d0,%a0@(MMUTBINVAL) | HP magic
#ifdef DEBUG
tstl _ASM_LABEL(fullcflush)
jne _C_LABEL(_DCIU) | XXX: invalidate entire user cache
#endif
#endif
rts
/*
* Invalidate instruction cache
*/
ENTRY(ICIA)
#if defined(M68040)
ENTRY(ICPA)
cmpl #MMU_68040,_C_LABEL(mmutype) | 68040
jne Lmotommu7 | no, skip
.word 0xf498 | cinva ic
rts
Lmotommu7:
#endif
movl #IC_CLEAR,%d0
movc %d0,%cacr | invalidate i-cache
rts
/*
* Invalidate data cache.
* HP external cache allows for invalidation of user/supervisor portions.
* NOTE: we do not flush 68030 on-chip cache as there are no aliasing
* problems with DC_WA. The only cases we have to worry about are context
* switch and TLB changes, both of which are handled "in-line" in resume
* and TBI*.
*/
ENTRY(DCIA)
_C_LABEL(_DCIA):
#if defined(M68040)
cmpl #MMU_68040,_C_LABEL(mmutype) | 68040
jne Lmotommu8 | no, skip
/* XXX implement */
rts
Lmotommu8:
#endif
#if defined(M68K_MMU_HP)
tstl _C_LABEL(ectype) | got external VAC?
jle Lnocache2 | no, all done
MMUADDR(%a0)
andl #~MMU_CEN,%a0@(MMUCMD) | disable cache in MMU control reg
orl #MMU_CEN,%a0@(MMUCMD) | reenable cache in MMU control reg
Lnocache2:
#endif
rts
ENTRY(DCIS)
_C_LABEL(_DCIS):
#if defined(M68040)
cmpl #MMU_68040,_C_LABEL(mmutype) | 68040
jne Lmotommu9 | no, skip
/* XXX implement */
rts
Lmotommu9:
#endif
#if defined(M68K_MMU_HP)
tstl _C_LABEL(ectype) | got external VAC?
jle Lnocache3 | no, all done
MMUADDR(%a0)
movl %a0@(MMUSSTP),%d0 | read the supervisor STP
movl %d0,%a0@(MMUSSTP) | write it back
Lnocache3:
#endif
rts
ENTRY(DCIU)
_C_LABEL(_DCIU):
#if defined(M68040)
cmpl #MMU_68040,_C_LABEL(mmutype) | 68040
jne LmotommuA | no, skip
/* XXX implement */
rts
LmotommuA:
#endif
#if defined(M68K_MMU_HP)
tstl _C_LABEL(ectype) | got external VAC?
jle Lnocache4 | no, all done
MMUADDR(%a0)
movl %a0@(MMUUSTP),%d0 | read the user STP
movl %d0,%a0@(MMUUSTP) | write it back
Lnocache4:
#endif
rts
#if defined(M68040)
ENTRY(ICPL)
movl %sp@(4),%a0 | address
.word 0xf488 | cinvl ic,%a0@
rts
ENTRY(ICPP)
movl %sp@(4),%a0 | address
.word 0xf490 | cinvp ic,%a0@
rts
ENTRY(DCPL)
movl %sp@(4),%a0 | address
.word 0xf448 | cinvl dc,%a0@
rts
ENTRY(DCPP)
movl %sp@(4),%a0 | address
.word 0xf450 | cinvp dc,%a0@
rts
ENTRY(DCPA)
.word 0xf458 | cinva dc
rts
ENTRY(DCFL)
movl %sp@(4),%a0 | address
.word 0xf468 | cpushl dc,%a0@
rts
ENTRY(DCFP)
movl %sp@(4),%a0 | address
.word 0xf470 | cpushp dc,%a0@
rts
#endif
ENTRY(PCIA)
#if defined(M68040)
ENTRY(DCFA)
cmpl #MMU_68040,_C_LABEL(mmutype) | 68040
jne LmotommuB | no, skip
.word 0xf478 | cpusha dc
rts
LmotommuB:
#endif
#if defined(M68K_MMU_MOTOROLA)
movl #DC_CLEAR,%d0
movc %d0,%cacr | invalidate on-chip d-cache
tstl _C_LABEL(ectype) | got external PAC?
jge Lnocache6 | no, all done
MMUADDR(%a0)
andl #~MMU_CEN,%a0@(MMUCMD) | disable cache in MMU control reg
orl #MMU_CEN,%a0@(MMUCMD) | reenable cache in MMU control reg
Lnocache6:
#endif
rts
ENTRY(ecacheon) ENTRY(ecacheon)
tstl _C_LABEL(ectype) tstl _C_LABEL(ectype)
jeq Lnocache7 jeq Lnocache7

173
sys/arch/hp300/include/cacheops_machdep.h Normal file
View File

@ -0,0 +1,173 @@
/* $NetBSD: cacheops_machdep.h,v 1.1 2002/11/02 20:03:05 chs Exp $ */
/*
* Copyright (c) 1994, 1995 Gordon W. Ross
* Copyright (c) 1988 University of Utah.
* Copyright (c) 1980, 1990, 1993
* The Regents of the University of California. All rights reserved.
*
* This code is derived from software contributed to Berkeley by
* the Systems Programming Group of the University of Utah Computer
* Science Department.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the University of
* California, Berkeley and its contributors.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifndef _HP300_CACHEOPS_MACHDEP_H_
#define _HP300_CACHEOPS_MACHDEP_H_
extern vaddr_t MMUbase;
int DCIA_md(void);
extern __inline int
DCIA_md(void)
{
volatile int *ip = (void *)(MMUbase + MMUCMD);
if (ectype != EC_VIRT) {
return 0;
}
*ip &= ~MMU_CEN;
*ip |= MMU_CEN;
return 1;
}
int DCIS_md(void);
extern __inline int
DCIS_md(void)
{
volatile int *ip = (void *)(MMUbase + MMUSSTP);
if (ectype != EC_VIRT) {
return 0;
}
*ip = *ip;
return 1;
}
int DCIU_md(void);
extern __inline int
DCIU_md(void)
{
volatile int *ip = (void *)(MMUbase + MMUUSTP);
if (ectype != EC_VIRT) {
return 0;
}
*ip = *ip;
return 1;
}
int PCIA_md(void);
extern __inline int
PCIA_md(void)
{
volatile int *ip = (void *)(MMUbase + MMUCMD);
if (ectype != EC_PHYS || cputype != CPU_68030) {
return 0;
}
*ip &= ~MMU_CEN;
*ip |= MMU_CEN;
/*
* only some '030 models (345/370/375/400) have external PAC,
* so we need to do the standard flushing as well.
*/
return 0;
}
int TBIA_md(void);
extern __inline int
TBIA_md(void)
{
volatile int *ip = (void *)(MMUbase + MMUTBINVAL);
if (mmutype != MMU_HP) {
return 0;
}
(void) *ip;
return 1;
}
int TBIS_md(vaddr_t);
extern __inline int
TBIS_md(vaddr_t va)
{
vaddr_t r_va __asm("%a0") = va;
int s;
if (mmutype != MMU_HP) {
return 0;
}
s = splhigh();
__asm __volatile (" movc %0, %%dfc;" /* select purge space */
" movsl %3, %1@;" /* purge it */
" movc %2, %%dfc;"
: : "r" (FC_PURGE), "a" (r_va), "r" (FC_USERD),
"r" (0));
splx(s);
return 1;
}
int TBIAS_md(void);
extern __inline int
TBIAS_md(void)
{
volatile int *ip = (void *)(MMUbase + MMUTBINVAL);
if (mmutype != MMU_HP) {
return 0;
}
*ip = 0x8000;
return 1;
}
int TBIAU_md(void);
extern __inline int
TBIAU_md(void)
{
volatile int *ip = (void *)(MMUbase + MMUTBINVAL);
if (mmutype != MMU_HP) {
return 0;
}
*ip = 0;
return 1;
}
#endif /* _HP300_CACHEOPS_MACHDEP_H_ */

20
sys/arch/hp300/include/cpu.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: cpu.h,v 1.39 2002/10/20 02:37:27 chs Exp $ */ /* $NetBSD: cpu.h,v 1.40 2002/11/02 20:03:06 chs Exp $ */
/* /*
* Copyright (c) 1988 University of Utah. * Copyright (c) 1988 University of Utah.
@ -265,4 +265,22 @@ int kvtop __P((caddr_t));
#define MMU_FAULT (MMU_PTF|MMU_PF|MMU_WPF|MMU_BERR) #define MMU_FAULT (MMU_PTF|MMU_PF|MMU_WPF|MMU_BERR)
#define MMU_ENAB (MMU_UMEN|MMU_SMEN|MMU_IEN|MMU_FPE) #define MMU_ENAB (MMU_UMEN|MMU_SMEN|MMU_IEN|MMU_FPE)
#if defined(CACHE_HAVE_PAC) || defined(CACHE_HAVE_VAC)
#define M68K_CACHEOPS_MACHDEP
#endif
#ifdef CACHE_HAVE_PAC
#define M68K_CACHEOPS_MACHDEP_PCIA
#endif
#ifdef CACHE_HAVE_VAC
#define M68K_CACHEOPS_MACHDEP_DCIA
#define M68K_CACHEOPS_MACHDEP_DCIS
#define M68K_CACHEOPS_MACHDEP_DCIU
#define M68K_CACHEOPS_MACHDEP_TBIA
#define M68K_CACHEOPS_MACHDEP_TBIS
#define M68K_CACHEOPS_MACHDEP_TBIAS
#define M68K_CACHEOPS_MACHDEP_TBIAU
#endif
#endif /* _HP300_CPU_H_ */ #endif /* _HP300_CPU_H_ */

190
sys/arch/m68k/include/cacheops.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: cacheops.h,v 1.8 2000/04/05 19:38:33 is Exp $ */ /* $NetBSD: cacheops.h,v 1.9 2002/11/02 20:03:06 chs Exp $ */
/*- /*-
* Copyright (c) 1997 The NetBSD Foundation, Inc. * Copyright (c) 1997 The NetBSD Foundation, Inc.
@ -48,131 +48,127 @@
#include <m68k/cacheops_40.h> #include <m68k/cacheops_40.h>
#include <m68k/cacheops_60.h> #include <m68k/cacheops_60.h>
#if defined(M68020) && !(defined(M68030)||defined(M68040)||defined(M68060)) #define M68K_CACHEOPS_NTYPES (defined(M68K_CACHEOPS_MACHDEP) + \
defined(M68020) + defined(M68030) + defined(M68040) + defined(M68060))
#if M68K_CACHEOPS_NTYPES == 1
#if defined(M68020)
#define TBIA() TBIA_20()
#define TBIS(va) TBIS_20((va))
#define TBIAS() TBIAS_20()
#define TBIAU() TBIAU_20()
#define ICIA() ICIA_20()
#define ICPA() ICPA_20()
#define DCIA() DCIA_20() #define DCIA() DCIA_20()
#define DCIAS(pa) DCIAS_20((pa))
#define DCIS() DCIS_20() #define DCIS() DCIS_20()
#define DCIU() DCIU_20() #define DCIU() DCIU_20()
#define DCIAS(pa) DCIAS_20((pa)) #define ICIA() ICIA_20()
#define ICPA() ICPA_20()
#define PCIA() PCIA_20() #define PCIA() PCIA_20()
#define TBIA() TBIA_20()
#define TBIAS() TBIAS_20()
#define TBIAU() TBIAU_20()
#define TBIS(va) TBIS_20((va))
#elif defined(M68030) && !(defined(M68020)||defined(M68040)||defined(M68060)) #elif defined(M68030)
#define TBIA() TBIA_30()
#define TBIS(va) TBIS_30((va))
#define TBIAS() TBIAS_30()
#define TBIAU() TBIAU_30()
#define ICIA() ICIA_30()
#define ICPA() ICPA_30()
#define DCIA() DCIA_30() #define DCIA() DCIA_30()
#define DCIAS(pa) DCIAS_30((pa))
#define DCIS() DCIS_30() #define DCIS() DCIS_30()
#define DCIU() DCIU_30() #define DCIU() DCIU_30()
#define DCIAS(pa) DCIAS_30((pa)) #define ICIA() ICIA_30()
#define ICPA() ICPA_30()
#define PCIA() PCIA_30() #define PCIA() PCIA_30()
#define TBIA() TBIA_30()
#define TBIAS() TBIAS_30()
#define TBIAU() TBIAU_30()
#define TBIS(va) TBIS_30((va))
#elif defined(M68040) && !(defined(M68020)||defined(M68030)||defined(M68060)) #elif defined(M68040)
#define TBIA() TBIA_40()
#define TBIS(va) TBIS_40((va))
#define TBIAS() TBIAS_40()
#define TBIAU() TBIAU_40()
#define ICIA() ICIA_40()
#define ICPA() ICPA_40()
#define DCIA() DCIA_40()
#define DCIS() DCIS_40()
#define DCIU() DCIU_40()
#define DCIAS(pa) DCIAS_40((pa))
#define PCIA() PCIA_40()
#define DCFA() DCFA_40() #define DCFA() DCFA_40()
#define ICPL(pa) ICPL_40((pa))
#define ICPP(pa) ICPP_40((pa))
#define DCPL(pa) DCPL_40((pa))
#define DCPP(pa) DCPP_40((pa))
#define DCPA() DCPA_40()
#define DCFL(pa) DCFL_40((pa)) #define DCFL(pa) DCFL_40((pa))
#define DCFP(pa) DCFP_40((pa)) #define DCFP(pa) DCFP_40((pa))
#define DCIA() DCIA_40()
#define DCIAS(pa) DCIAS_40((pa))
#define DCIS() DCIS_40()
#define DCIU() DCIU_40()
#define DCPA() DCPA_40()
#define DCPL(pa) DCPL_40((pa))
#define DCPP(pa) DCPP_40((pa))
#define ICIA() ICIA_40()
#define ICPA() ICPA_40()
#define ICPL(pa) ICPL_40((pa))
#define ICPP(pa) ICPP_40((pa))
#define PCIA() PCIA_40()
#define TBIA() TBIA_40()
#define TBIAS() TBIAS_40()
#define TBIAU() TBIAU_40()
#define TBIS(va) TBIS_40((va))
#elif defined(M68060) && !(defined(M68020)||defined(M68030)||defined(M68040)) #elif defined(M68060)
#define TBIA() TBIA_60()
#define TBIS(va) TBIS_60((va))
#define TBIAS() TBIAS_60()
#define TBIAU() TBIAU_60()
#define ICIA() ICIA_60()
#define ICPA() ICPA_60()
#define DCIA() DCIA_60()
#define DCIS() DCIS_60()
#define DCIU() DCIU_60()
#define DCIAS(pa) DCIAS_60((pa))
#define PCIA() PCIA_60()
#define DCFA() DCFA_60() #define DCFA() DCFA_60()
#define ICPL(pa) ICPL_60((pa))
#define ICPP(pa) ICPP_60((pa))
#define DCPL(pa) DCPL_60((pa))
#define DCPP(pa) DCPP_60((pa))
#define DCPA() DCPA_60()
#define DCFL(pa) DCFL_60((pa)) #define DCFL(pa) DCFL_60((pa))
#define DCFP(pa) DCFP_60((pa)) #define DCFP(pa) DCFP_60((pa))
#define DCIA() DCIA_60()
#define DCIAS(pa) DCIAS_60((pa))
#define DCIS() DCIS_60()
#define DCIU() DCIU_60()
#define DCPA() DCPA_60()
#define DCPL(pa) DCPL_60((pa))
#define DCPP(pa) DCPP_60((pa))
#define ICIA() ICIA_60()
#define ICPA() ICPA_60()
#define ICPL(pa) ICPL_60((pa))
#define ICPP(pa) ICPP_60((pa))
#define PCIA() PCIA_60()
#define TBIA() TBIA_60()
#define TBIAS() TBIAS_60()
#define TBIAU() TBIAU_60()
#define TBIS(va) TBIS_60((va))
#else /* Multi-CPU config */
/* XXX: From cpuconf.h? */
#ifndef _MULTI_CPU
#define _MULTI_CPU
#endif #endif
void _TBIA __P((void)); #else /* M68K_CACHEOPS_NTYPES == 1 */
void _TBIS __P((vaddr_t));
void _TBIAS __P((void));
void _TBIAU __P((void));
void _ICIA __P((void));
void _ICPA __P((void));
void _DCIA __P((void));
void _DCIS __P((void));
void _DCIU __P((void));
void _DCIAS __P((paddr_t));
void _PCIA __P((void));
#define TBIA() _TBIA()
#define TBIS(va) _TBIS((va))
#define TBIAS() _TBIAS()
#define TBIAU() _TBIAU()
#define ICIA() _ICIA()
#define ICPA() _ICPA()
#define DCIA() _DCIA()
#define DCIS() _DCIS()
#define DCIU() _DCIU()
#define DCIAS(pa) _DCIAS((pa))
#define PCIA() _PCIA()
#if defined(M68040)||defined(M68060)
void _DCFA __P((void));
void _ICPL __P((paddr_t));
void _ICPP __P((paddr_t));
void _DCPL __P((paddr_t));
void _DCPP __P((paddr_t));
void _DCPA __P((void));
void _DCFL __P((paddr_t));
void _DCFP __P((paddr_t));
#define DCFA() _DCFA() #define DCFA() _DCFA()
#define ICPL(pa) _ICPL((pa))
#define ICPP(pa) _ICPP((pa))
#define DCPL(pa) _DCPL((pa))
#define DCPP(pa) _DCPP((pa))
#define DCPA() _DCPA()
#define DCFL(pa) _DCFL((pa)) #define DCFL(pa) _DCFL((pa))
#define DCFP(pa) _DCFP((pa)) #define DCFP(pa) _DCFP((pa))
#define DCIA() _DCIA()
#define DCIAS(pa) _DCIAS((pa))
#define DCIS() _DCIS()
#define DCIU() _DCIU()
#define DCPA() _DCPA()
#define DCPL(pa) _DCPL((pa))
#define DCPP(pa) _DCPP((pa))
#define ICIA() _ICIA()
#define ICPA() _ICPA()
#define ICPL(pa) _ICPL((pa))
#define ICPP(pa) _ICPP((pa))
#define PCIA() _PCIA()
#define TBIA() _TBIA()
#define TBIAS() _TBIAS()
#define TBIAU() _TBIAU()
#define TBIS(va) _TBIS((va))
#endif /* defined(M68040)||defined(M68060) */ #endif /* M68K_CACHEOPS_NTYPES == 1 */
#endif void _DCFA __P((void));
void _DCFL __P((paddr_t));
void _DCFP __P((paddr_t));
void _DCIA __P((void));
void _DCIAS __P((paddr_t));
void _DCIS __P((void));
void _DCIU __P((void));
void _DCPA __P((void));
void _DCPL __P((paddr_t));
void _DCPP __P((paddr_t));
void _ICIA __P((void));
void _ICPA __P((void));
void _ICPL __P((paddr_t));
void _ICPP __P((paddr_t));
void _PCIA __P((void));
void _TBIA __P((void));
void _TBIAS __P((void));
void _TBIAU __P((void));
void _TBIS __P((vaddr_t));
#endif /* _M68K_CACHEOPS_H_ */ #endif /* _M68K_CACHEOPS_H_ */

139
sys/arch/m68k/m68k/cacheops.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: cacheops.c,v 1.6 2000/04/15 20:31:27 scw Exp $ */ /* $NetBSD: cacheops.c,v 1.7 2002/11/02 20:03:06 chs Exp $ */
/*- /*-
* Copyright (c) 1997 The NetBSD Foundation, Inc. * Copyright (c) 1997 The NetBSD Foundation, Inc.
@ -39,13 +39,19 @@
#include <sys/cdefs.h> #include <sys/cdefs.h>
#include <sys/types.h> #include <sys/types.h>
#include <machine/cpu.h> #include <machine/cpu.h>
#include <m68k/cpu.h>
#include <m68k/cacheops.h> #include <m68k/cacheops.h>
#ifdef M68K_CACHEOPS_MACHDEP
#include <machine/cacheops_machdep.h>
#endif
#if defined(_MULTI_CPU) void
_TBIA()
void _TBIA()
{ {
#ifdef M68K_CACHEOPS_MACHDEP_TBIA
if (TBIA_md())
return;
#endif
switch (cputype) { switch (cputype) {
default: default:
#ifdef M68020 #ifdef M68020
@ -71,8 +77,14 @@ void _TBIA()
} }
} }
void _TBIAS() void
_TBIAS()
{ {
#ifdef M68K_CACHEOPS_MACHDEP_TBIAS
if (TBIAS_md())
return;
#endif
switch (cputype) { switch (cputype) {
default: default:
#ifdef M68020 #ifdef M68020
@ -98,8 +110,14 @@ void _TBIAS()
} }
} }
void _TBIAU() void
_TBIAU()
{ {
#ifdef M68K_CACHEOPS_MACHDEP_TBIAU
if (TBIAU_md())
return;
#endif
switch (cputype) { switch (cputype) {
default: default:
#ifdef M68020 #ifdef M68020
@ -125,7 +143,8 @@ void _TBIAU()
} }
} }
void _ICIA() void
_ICIA()
{ {
switch (cputype) { switch (cputype) {
default: default:
@ -152,7 +171,8 @@ void _ICIA()
} }
} }
void _ICPA() void
_ICPA()
{ {
switch (cputype) { switch (cputype) {
default: default:
@ -179,8 +199,14 @@ void _ICPA()
} }
} }
void _DCIA() void
_DCIA()
{ {
#ifdef M68K_CACHEOPS_MACHDEP_DCIA
if (DCIA_md())
return;
#endif
switch (cputype) { switch (cputype) {
default: default:
#ifdef M68020 #ifdef M68020
@ -206,8 +232,14 @@ void _DCIA()
} }
} }
void _DCIS() void
_DCIS()
{ {
#ifdef M68K_CACHEOPS_MACHDEP_DCIS
if (DCIS_md())
return;
#endif
switch (cputype) { switch (cputype) {
default: default:
#ifdef M68020 #ifdef M68020
@ -233,8 +265,14 @@ void _DCIS()
} }
} }
void _DCIU() void
_DCIU()
{ {
#ifdef M68K_CACHEOPS_MACHDEP_DCIU
if (DCIU_md())
return;
#endif
switch (cputype) { switch (cputype) {
default: default:
#ifdef M68020 #ifdef M68020
@ -260,8 +298,14 @@ void _DCIU()
} }
} }
void _PCIA() void
_PCIA()
{ {
#ifdef M68K_CACHEOPS_MACHDEP_PCIA
if (PCIA_md())
return;
#endif
switch (cputype) { switch (cputype) {
default: default:
#ifdef M68020 #ifdef M68020
@ -287,27 +331,15 @@ void _PCIA()
} }
} }
#if defined(M68040) || defined(M68060) void
void _DCFA() _TBIS(va)
{
switch (cputype) {
#ifdef M68040
case CPU_68040:
DCFA_40();
break;
#endif
#ifdef M68060
case CPU_68060:
DCFA_60();
break;
#endif
}
}
#endif /* M68040 || M68060 */
void _TBIS(va)
vaddr_t va; vaddr_t va;
{ {
#ifdef M68K_CACHEOPS_MACHDEP_TBIS
if (TBIS_md(va))
return;
#endif
switch (cputype) { switch (cputype) {
default: default:
#ifdef M68020 #ifdef M68020
@ -333,7 +365,8 @@ void _TBIS(va)
} }
} }
void _DCIAS(pa) void
_DCIAS(pa)
paddr_t pa; paddr_t pa;
{ {
switch (cputype) { switch (cputype) {
@ -362,7 +395,25 @@ void _DCIAS(pa)
} }
#if defined(M68040) || defined(M68060) #if defined(M68040) || defined(M68060)
void _DCPA() void
_DCFA()
{
switch (cputype) {
#ifdef M68040
case CPU_68040:
DCFA_40();
break;
#endif
#ifdef M68060
case CPU_68060:
DCFA_60();
break;
#endif
}
}
void
_DCPA()
{ {
switch (cputype) { switch (cputype) {
default: default:
@ -379,7 +430,8 @@ void _DCPA()
} }
} }
void _ICPL(pa) void
_ICPL(pa)
paddr_t pa; paddr_t pa;
{ {
switch (cputype) { switch (cputype) {
@ -397,7 +449,8 @@ void _ICPL(pa)
} }
} }
void _ICPP(pa) void
_ICPP(pa)
paddr_t pa; paddr_t pa;
{ {
switch (cputype) { switch (cputype) {
@ -415,7 +468,8 @@ void _ICPP(pa)
} }
} }
void _DCPL(pa) void
_DCPL(pa)
paddr_t pa; paddr_t pa;
{ {
switch (cputype) { switch (cputype) {
@ -433,7 +487,8 @@ void _DCPL(pa)
} }
} }
void _DCPP(pa) void
_DCPP(pa)
paddr_t pa; paddr_t pa;
{ {
switch (cputype) { switch (cputype) {
@ -451,7 +506,8 @@ void _DCPP(pa)
} }
} }
void _DCFL(pa) void
_DCFL(pa)
paddr_t pa; paddr_t pa;
{ {
switch (cputype) { switch (cputype) {
@ -469,7 +525,8 @@ void _DCFL(pa)
} }
} }
void _DCFP(pa) void
_DCFP(pa)
paddr_t pa; paddr_t pa;
{ {
switch (cputype) { switch (cputype) {
@ -487,5 +544,3 @@ void _DCFP(pa)
} }
} }
#endif /* M68040 || M68060 */ #endif /* M68040 || M68060 */
#endif /* defined(_MULTI_CPU) */

3
sys/arch/news68k/conf/files.news68k
View File

@ -1,4 +1,4 @@
# $NetBSD: files.news68k,v 1.18 2002/10/26 13:50:37 jdolecek Exp $ # $NetBSD: files.news68k,v 1.19 2002/11/02 20:03:06 chs Exp $
# NEWS68K-specific configuration info # NEWS68K-specific configuration info
@ -27,6 +27,7 @@ file arch/news68k/news68k/pmap_bootstrap.c compile-with "${NOPROF_C}"
file arch/news68k/news68k/procfs_machdep.c procfs file arch/news68k/news68k/procfs_machdep.c procfs
file arch/news68k/news68k/sys_machdep.c file arch/news68k/news68k/sys_machdep.c
file arch/news68k/news68k/trap.c file arch/news68k/news68k/trap.c
file arch/m68k/m68k/cacheops.c
file arch/m68k/m68k/vm_machdep.c file arch/m68k/m68k/vm_machdep.c
file dev/clock_subr.c file dev/clock_subr.c
file dev/cons.c file dev/cons.c

94
sys/arch/news68k/include/cacheops_machdep.h Normal file
View File

@ -0,0 +1,94 @@
/* $NetBSD: cacheops_machdep.h,v 1.1 2002/11/02 20:03:06 chs Exp $ */
/*
* Copyright (c) 1988 University of Utah.
* Copyright (c) 1980, 1990, 1993
* The Regents of the University of California. All rights reserved.
*
* This code is derived from software contributed to Berkeley by
* the Systems Programming Group of the University of Utah Computer
* Science Department.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the University of
* California, Berkeley and its contributors.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifndef _NEWS68K_CACHEOPS_MACHDEP_H_
#define _NEWS68K_CACHEOPS_MACHDEP_H_
extern void *cache_clr;
int DCIx_md(void);
extern __inline int
DCIx_md(void)
{
volatile uint8_t *p = cache_clr;
if (ectype != EC_VIRT) {
return 0;
}
*p = 0xff;
return 1;
}
int DCIA_md(void);
extern __inline int
DCIA_md(void)
{
return DCIx_md();
}
int DCIS_md(void);
extern __inline int
DCIS_md(void)
{
return DCIx_md();
}
int DCIU_md(void);
extern __inline int
DCIU_md(void)
{
return DCIx_md();
}
int PCIA_md(void);
extern __inline int
PCIA_md(void)
{
volatile uint8_t *p = cache_clr;
if (ectype != EC_PHYS) {
return 0;
}
*p = 0xff;
return 1;
}
#endif /* _NEWS68K_CACHEOPS_MACHDEP_H_ */

16
sys/arch/news68k/include/cpu.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: cpu.h,v 1.11 2002/10/20 02:37:31 chs Exp $ */ /* $NetBSD: cpu.h,v 1.12 2002/11/02 20:03:07 chs Exp $ */
/* /*
* Copyright (c) 1988 University of Utah. * Copyright (c) 1988 University of Utah.
@ -264,4 +264,18 @@ int kvtop __P((caddr_t));
((char *)(va) >= extiobase && (char *)(va) < (char *)EIOSIZE) ((char *)(va) >= extiobase && (char *)(va) < (char *)EIOSIZE)
#define EIOV(pa) (((u_int)(pa) - extiobase_phys) + (u_int)extiobase) #define EIOV(pa) (((u_int)(pa) - extiobase_phys) + (u_int)extiobase)
#if defined(CACHE_HAVE_PAC) || defined(CACHE_HAVE_VAC)
#define M68K_CACHEOPS_MACHDEP
#endif
#ifdef CACHE_HAVE_PAC
#define M68K_CACHEOPS_MACHDEP_PCIA
#endif
#ifdef CACHE_HAVE_VAC
#define M68K_CACHEOPS_MACHDEP_DCIA
#define M68K_CACHEOPS_MACHDEP_DCIS
#define M68K_CACHEOPS_MACHDEP_DCIU
#endif
#endif /* !_NEWS68K_CPU_H_ */ #endif /* !_NEWS68K_CPU_H_ */

135
sys/arch/news68k/news68k/locore.s
View File

@ -1,4 +1,4 @@
/* $NetBSD: locore.s,v 1.26 2002/05/30 21:49:20 thorpej Exp $ */ /* $NetBSD: locore.s,v 1.27 2002/11/02 20:03:07 chs Exp $ */
/* /*
* Copyright (c) 1988 University of Utah. * Copyright (c) 1988 University of Utah.
@ -421,7 +421,7 @@ Lenab1:
jbsr _C_LABEL(m68881_restore) | restore it (does not kill a1) jbsr _C_LABEL(m68881_restore) | restore it (does not kill a1)
addql #4,%sp addql #4,%sp
Lenab2: Lenab2:
jbsr _C_LABEL(TBIA) | invalidate TLB jbsr _C_LABEL(_TBIA) | invalidate TLB
cmpl #MMU_68040,_C_LABEL(mmutype) | 68040? cmpl #MMU_68040,_C_LABEL(mmutype) | 68040?
jeq Ltbia040 | yes, cache already on jeq Ltbia040 | yes, cache already on
pflusha pflusha
@ -1203,137 +1203,6 @@ Lsvnofpsave:
moveq #0,%d0 | return 0 moveq #0,%d0 | return 0
rts rts
/*
* Invalidate entire TLB.
*/
ENTRY(TBIA)
_C_LABEL(_TBIA):
tstl _C_LABEL(mmutype) | MMU type?
pflusha | flush entire TLB
jpl Lmc68851a | 68851 implies no d-cache
movc %cacr,%d0
orl #DC_CLR,%d0
movc %d0,%cacr | invalidate on-chip d-cache
#if 0
jmp _C_LABEL(_DCIA)
#endif
Lmc68851a:
rts
/*
* Invalidate any TLB entry for given VA (TB Invalidate Single)
*/
ENTRY(TBIS)
tstl _C_LABEL(mmutype) | MMU type?
movl %sp@(4),%a0 | get addr to flush
jpl Lmc68851b | is 68851?
pflush #0,#0,%a0@ | flush address from both sides
movc %cacr,%d0
orl #DC_CLR,%d0
movc %d0,%cacr | invalidate on-chip data cache
rts
Lmc68851b:
pflushs #0,#0,%a0@ | flush address from both sides
rts
/*
* Invalidate supervisor side of TLB
*/
ENTRY(TBIAS)
tstl _C_LABEL(mmutype) | MMU type?
jpl Lmc68851c | 68851?
pflush #4,#4 | flush supervisor TLB entries
movc %cacr,%d0
orl #DC_CLR,%d0
movc %d0,%cacr | invalidate on-chip d-cache
rts
Lmc68851c:
pflushs #4,#4 | flush supervisor TLB entries
#if 0
jmp _C_LABEL(_DCIS)
#endif
rts
/*
* Invalidate user side of TLB
*/
ENTRY(TBIAU)
tstl _C_LABEL(mmutype) | MMU type?
jpl Lmc68851d | 68851?
pflush #0,#4 | flush user TLB entries
movc %cacr,%d0
orl #DC_CLR,%d0
movc %d0,%cacr | invalidate on-chip d-cache
rts
Lmc68851d:
pflushs #0,#4 | flush user TLB entries
#if 0
jmp _C_LABEL(_DCIU)
#endif
rts
/*
* Invalidate instruction cache
*/
ENTRY(ICIA)
movc %cacr,%d0
orl #IC_CLR,%d0
movc %d0,%cacr | invalidate i-cache
#if 0
tstl _C_LABEL(ectype) | got external PAC?
jge Lnocache1 | no, all done
movl _C_LABEL(cache_clr),%a0
st %a0@ | NEWS-OS does `st 0xe1900000'
Lnocache1:
#endif
rts
/*
* Invalidate data cache.
* news68k external cache does not allow for invalidation of user/supervisor
* portions. (probably...)
* NOTE: we do not flush 68030 on-chip cache as there are no aliasing
* problems with DC_WA. The only cases we have to worry about are context
* switch and TLB changes, both of which are handled "in-line" in resume
* and TBI*.
*
* XXX: NEWS-OS *does* flush 68030 on-chip cache... Should this be done?
*/
ENTRY(DCIA)
ENTRY(DCIS)
ENTRY(DCIU)
_C_LABEL(_DCIA):
_C_LABEL(_DCIS):
_C_LABEL(_DCIU):
#if 0
movc %cacr,%d0
orl #DC_CLR,%d0
movc %d0,%cacr
#endif
tstl _C_LABEL(ectype) | got external VAC?
jle Lnocache2 | no, all done
movl _C_LABEL(cache_clr),%a0
st %a0@ | NEWS-OS does `st 0xe1900000'
Lnocache2:
rts
ENTRY(PCIA)
#if 0
movc %cacr,%d0
orl #DC_CLR,%d0
movc %d0,%cacr | invalidate on-chip d-cache
#endif
tstl _C_LABEL(ectype) | got external PAC?
jge Lnocache6 | no, all done
movl _C_LABEL(cache_clr),%a0
st %a0@ | NEWS-OS does `st 0xe1900000'
Lnocache6:
rts
ENTRY(ecacheon) ENTRY(ecacheon)
tstl _C_LABEL(ectype) tstl _C_LABEL(ectype)
jeq Lnocache7 jeq Lnocache7

5
sys/arch/news68k/news68k/trap.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: trap.c,v 1.21 2002/10/20 02:37:32 chs Exp $ */ /* $NetBSD: trap.c,v 1.22 2002/11/02 20:03:07 chs Exp $ */
/* /*
* Copyright (c) 1988 University of Utah. * Copyright (c) 1988 University of Utah.
@ -55,11 +55,10 @@
#include <sys/syscall.h> #include <sys/syscall.h>
#include <sys/user.h> #include <sys/user.h>
#include <m68k/cacheops.h>
#include <machine/db_machdep.h> #include <machine/db_machdep.h>
#include <machine/trap.h> #include <machine/trap.h>
#include <machine/cpu.h> #include <machine/cpu.h>
#include <m68k/cacheops.h>
#include <machine/reg.h> #include <machine/reg.h>
#include <uvm/uvm_extern.h> #include <uvm/uvm_extern.h>

4
sys/arch/sun3/conf/files.sun3
View File

@ -1,4 +1,4 @@
# $NetBSD: files.sun3,v 1.67 2002/10/27 23:23:48 chs Exp $ # $NetBSD: files.sun3,v 1.68 2002/11/02 20:03:07 chs Exp $
# #
# sun3-specific configuration info # sun3-specific configuration info
@ -45,7 +45,7 @@ file arch/sun3/sun3/sunmon.c
file arch/sun3/sun3/sys_machdep.c file arch/sun3/sun3/sys_machdep.c
file arch/sun3/sun3/trap.c file arch/sun3/sun3/trap.c
file arch/sun3/sun3/vector.c file arch/sun3/sun3/vector.c
file arch/m68k/m68k/cacheops.c file arch/m68k/m68k/cacheops.c _sun3x_
file arch/m68k/m68k/vm_machdep.c file arch/m68k/m68k/vm_machdep.c
include "arch/m68k/fpe/files.fpe" include "arch/m68k/fpe/files.fpe"

90
sys/arch/sun3/sun3x/locore.s
View File

@ -1,4 +1,4 @@
/* $NetBSD: locore.s,v 1.49 2002/10/20 02:37:38 chs Exp $ */ /* $NetBSD: locore.s,v 1.50 2002/11/02 20:03:07 chs Exp $ */
/* /*
* Copyright (c) 1988 University of Utah. * Copyright (c) 1988 University of Utah.
@ -867,94 +867,6 @@ ASGLOBAL(fullcflush)
.text .text
#endif #endif
/*
* Invalidate entire TLB.
*/
ENTRY(TBIA)
_C_LABEL(_TBIA):
pflusha
movl #DC_CLEAR,%d0
movc %d0,%cacr | invalidate on-chip d-cache
rts
/*
* Invalidate any TLB entry for given VA (TB Invalidate Single)
*/
ENTRY(TBIS)
#ifdef DEBUG
tstl _ASM_LABEL(fulltflush) | being conservative?
jne _C_LABEL(_TBIA) | yes, flush entire TLB
#endif
movl %sp@(4),%a0
pflush #0,#0,%a0@ | flush address from both sides
movl #DC_CLEAR,%d0
movc %d0,%cacr | invalidate on-chip data cache
rts
/*
* Invalidate supervisor side of TLB
*/
ENTRY(TBIAS)
#ifdef DEBUG
tstl _ASM_LABEL(fulltflush) | being conservative?
jne _C_LABEL(_TBIA) | yes, flush everything
#endif
pflush #4,#4 | flush supervisor TLB entries
movl #DC_CLEAR,%d0
movc %d0,%cacr | invalidate on-chip d-cache
rts
/*
* Invalidate user side of TLB
*/
ENTRY(TBIAU)
#ifdef DEBUG
tstl _ASM_LABEL(fulltflush) | being conservative?
jne _C_LABEL(_TBIA) | yes, flush everything
#endif
pflush #0,#4 | flush user TLB entries
movl #DC_CLEAR,%d0
movc %d0,%cacr | invalidate on-chip d-cache
rts
/*
* Invalidate instruction cache
*/
ENTRY(ICIA)
movl #IC_CLEAR,%d0
movc %d0,%cacr | invalidate i-cache
rts
/*
* Invalidate data cache.
* NOTE: we do not flush 68030 on-chip cache as there are no aliasing
* problems with DC_WA. The only cases we have to worry about are context
* switch and TLB changes, both of which are handled "in-line" in resume
* and TBI*.
*/
ENTRY(DCIA)
__DCIA:
rts
ENTRY(DCIS)
__DCIS:
rts
/*
* Invalidate data cache.
*/
ENTRY(DCIU)
movl #DC_CLEAR,%d0
movc %d0,%cacr | invalidate on-chip d-cache
rts
/* ICPL, ICPP, DCPL, DCPP, DCPA, DCFL, DCFP */
ENTRY(PCIA)
movl #DC_CLEAR,%d0
movc %d0,%cacr | invalidate on-chip d-cache
rts
ENTRY(ecacheon) ENTRY(ecacheon)
rts rts