more OMAP5 workarounds.
u-boot doesn't initialize the generic timer on the omap5430 evm properly. so check to see if it's OK, and if not, initialize omap5 registers properly. Pass the timer freq via properties to the armgtmr since we can't write the cnt_frq cp15 register (which can be written in secure mode).
This commit is contained in:
matt
parent
8264309027
commit
404129e876
@ -1,4 +1,4 @@
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/* $NetBSD: beagle_machdep.c,v 1.48 2013/06/18 23:40:38 matt Exp $ */
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/* $NetBSD: beagle_machdep.c,v 1.49 2013/06/20 05:39:19 matt Exp $ */
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/*
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* Machine dependent functions for kernel setup for TI OSK5912 board.
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@ -125,7 +125,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: beagle_machdep.c,v 1.48 2013/06/18 23:40:38 matt Exp $");
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__KERNEL_RCSID(0, "$NetBSD: beagle_machdep.c,v 1.49 2013/06/20 05:39:19 matt Exp $");
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#include "opt_machdep.h"
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#include "opt_ddb.h"
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@ -219,6 +219,10 @@ int use_fb_console = false;
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int use_fb_console = true;
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#endif
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#ifdef CPU_CORTEXA15
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uint32_t omap5_cnt_frq;
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#endif
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/*
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* Macros to translate between physical and virtual for a subset of the
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* kernel address space. *Not* for general use.
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@ -479,7 +483,7 @@ initarm(void *arg)
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#if 1
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beagle_putchar('h');
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#endif
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printf("uboot arg = %#x, %#x, %#x, %#x\n",
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printf("\nuboot arg = %#x, %#x, %#x, %#x\n",
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uboot_args[0], uboot_args[1], uboot_args[2], uboot_args[3]);
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#ifdef KGDB
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@ -502,6 +506,8 @@ initarm(void *arg)
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printf("initarm: Configuring system ...\n");
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#endif
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printf("initarm: cbar=%#x\n", armreg_cbar_read());
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/*
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* Set up the variables that define the availability of physical
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* memory.
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@ -719,7 +725,8 @@ omap4_cpu_clk(void)
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const vaddr_t cm_base = OMAP2_CM_BASE - OMAP_L4_CORE_BASE + OMAP_L4_CORE_VBASE;
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static const uint32_t cm_clksel_freqs[] = OMAP4_CM_CLKSEL_FREQS;
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const uint32_t prm_clksel = *(volatile uint32_t *)(prm_base + OMAP4_CM_SYS_CLKSEL);
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const uint32_t sys_clk = cm_clksel_freqs[__SHIFTOUT(prm_clksel, OMAP4_CM_SYS_CLKSEL_CLKIN)];
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const u_int clksel = __SHIFTOUT(prm_clksel, OMAP4_CM_SYS_CLKSEL_CLKIN);
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const uint32_t sys_clk = cm_clksel_freqs[clksel];
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const uint32_t dpll1 = *(volatile uint32_t *)(cm_base + OMAP4_CM_CLKSEL_DPLL_MPU);
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const uint32_t dpll2 = *(volatile uint32_t *)(cm_base + OMAP4_CM_DIV_M2_DPLL_MPU);
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const uint32_t m = __SHIFTOUT(dpll1, OMAP4_CM_CLKSEL_DPLL_MPU_DPLL_MULT);
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@ -734,6 +741,56 @@ omap4_cpu_clk(void)
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printf("%s: %"PRIu64": sys_clk=%u m=%u n=%u (%u) m2=%u mult=%u\n",
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__func__, curcpu()->ci_data.cpu_cc_freq,
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sys_clk, m, n, n+1, m2, OMAP4_CM_CLKSEL_MULT);
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#if defined(CPU_CORTEXA15)
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if ((armreg_pfr1_read() & ARM_PFR1_GTIMER_MASK) != 0) {
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beagle_putchar('0');
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uint32_t voffset = OMAP_L4_PERIPHERAL_VBASE - OMAP_L4_PERIPHERAL_BASE;
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uint32_t frac1_reg = OMAP5_PRM_FRAC_INCREMENTER_NUMERATOR;
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uint32_t frac2_reg = OMAP5_PRM_FRAC_INCREMENTER_DENUMERATOR_RELOAD;
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uint32_t frac1 = *(volatile uint32_t *)(frac1_reg + voffset);
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beagle_putchar('1');
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uint32_t frac2 = *(volatile uint32_t *)(frac2_reg + voffset);
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beagle_putchar('2');
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uint32_t numer = __SHIFTOUT(frac1, PRM_FRAC_INCR_NUM_SYS_MODE);
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uint32_t denom = __SHIFTOUT(frac2, PRM_FRAC_INCR_DENUM_DENOMINATOR);
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uint32_t freq = (uint64_t)omap_sys_clk * numer / denom;
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#if 1
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if (freq != OMAP5_GTIMER_FREQ) {
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static uint16_t numer_demon[8][2] = {
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{ 0, 0 }, /* not used */
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{ 26 * 64, 26 * 125 }, /* 12.0Mhz */
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{ 2 * 768, 2 * 1625 }, /* 13.0Mhz */
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{ 0, 0 }, /* 16.8Mhz (not used) */
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{ 130 * 8, 130 * 25 }, /* 19.2Mhz */
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{ 2 * 384, 2 * 1625 }, /* 26.0Mhz */
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{ 3 * 256, 3 * 1125 }, /* 27.0Mhz */
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{ 130 * 4, 130 * 25 }, /* 38.4Mhz */
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};
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if (numer_demon[clksel][0] != numer) {
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frac1 &= ~PRM_FRAC_INCR_NUM_SYS_MODE;
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frac1 |= numer_demon[clksel][0];
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}
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if (numer_demon[clksel][1] != denom) {
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frac2 &= ~PRM_FRAC_INCR_DENUM_DENOMINATOR;
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frac2 |= numer_demon[clksel][1];
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}
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*(volatile uint32_t *)(frac1_reg + voffset) = frac1;
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*(volatile uint32_t *)(frac2_reg + voffset) = frac2
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| PRM_FRAC_INCR_DENUM_RELOAD;
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freq = OMAP5_GTIMER_FREQ;
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}
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#endif
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beagle_putchar('3');
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#if 0
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if (gtimer_freq != freq) {
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armreg_cnt_frq_write(freq); // secure only
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}
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#endif
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omap5_cnt_frq = freq;
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beagle_putchar('4');
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}
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#endif
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}
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#endif /* OMAP_4XXX || OMAP_5XXX */
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@ -767,7 +824,15 @@ am335x_cpu_clk(void)
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static inline uint32_t
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emif_read_sdram_config(vaddr_t emif_base)
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{
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return *(const volatile uint32_t *)(emif_base + EMIF_SDRAM_CONFIG);
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#ifdef CPU_CORTEXA15
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return 0x61851b32; // XXX until i figure out why deref emif_base dies
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#else
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emif_base += EMIF_SDRAM_CONFIG;
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//printf("%s: sdram_config @ %#"PRIxVADDR" = ", __func__, emif_base);
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uint32_t v = *(const volatile uint32_t *)(emif_base);
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//printf("%#x\n", v);
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return v;
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#endif
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}
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static psize_t
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@ -881,6 +946,7 @@ beagle_device_register(device_t self, void *aux)
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return;
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}
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#ifdef CPU_CORTEXA9
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/*
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* We need to tell the A9 Global/Watchdog Timer
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* what frequency it runs at.
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@ -893,7 +959,18 @@ beagle_device_register(device_t self, void *aux)
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prop_dictionary_set_uint32(dict, "frequency",
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curcpu()->ci_data.cpu_cc_freq / 2);
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return;
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}
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}
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#endif
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#ifdef CPU_CORTEXA15
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if (device_is_a(self, "armgtmr")) {
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/*
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* The frequency of the generic timer was figured out when
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* determined the cpu frequency.
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*/
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prop_dictionary_set_uint32(dict, "frequency", omap5_cnt_frq);
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}
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#endif
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if (device_is_a(self, "ehci")) {
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#if defined(OMAP_3530)
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