Sort options. Fix a few typos.
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@ -1,4 +1,4 @@
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.\" $NetBSD: mb.9,v 1.1 2007/02/02 03:40:07 ad Exp $
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.\" $NetBSD: mb.9,v 1.2 2007/02/02 07:35:28 wiz Exp $
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.\"
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.\" Copyright (c) 2007 The NetBSD Foundation, Inc.
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.\" All rights reserved.
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@ -35,7 +35,7 @@
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.\" POSSIBILITY OF SUCH DAMAGE.
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.\"
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.Dd November 13, 2006
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.Dt MUTEX 9
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.Dt MB 9
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.Os
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.Sh NAME
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.Nm mb ,
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@ -70,9 +70,10 @@ and
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.Fn mb_write
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can be used to control the order in which memory acceses occur, and
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thus the order in which those accesses become visible to other processors.
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They can be used to implement "lockless" access to data structures where
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They can be used to implement
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.Dq lockless
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access to data structures where
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the necessary barrier conditions are well understood.
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.Pp
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.Sh FUNCTIONS
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.Bl -tag -width abcd
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.It Fn mb_memory ""
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@ -98,13 +99,23 @@ to complete before execution continues.
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Loads may be reordered ahead of or behind a call to
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.Fn mb_write .
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.El
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.Sh SEE ALSO
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.Xr bus_dma 9 ,
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.Xr bus_space 9 ,
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.Xr mutex 9 ,
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.Xr rwlock 9
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.Sh HISTORY
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The memory barrier primitives first appeared in
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.Nx 5.0 .
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.Sh CAVEATS
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Memory barriers cay be computationally expensive, as they are
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considered "serializing" operations and may stall further execution
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Memory barriers can be computationally expensive, as they are
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considered
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.Dq serializing
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operations and may stall further execution
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until the processor has drained internal buffers and re-synchronized.
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.Pp
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The memory barrier primitives control only the order of memory access.
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They provide no guarantee that stores have been flused to the bus, or
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They provide no guarantee that stores have been flushed to the bus, or
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that loads have been made from the bus.
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.Pp
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The memory barrier primitives are guaranteed only to prevent reordering
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@ -116,11 +127,3 @@ To guarantee ordering of access to device memory, the
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and
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.Xr bus_space 9
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interfaces should be used.
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.Sh SEE ALSO
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.Xr bus_dma 9 ,
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.Xr bus_space 9 ,
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.Xr mutex 9 ,
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.Xr rwlock 9
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.Sh HISTORY
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The memory barrier primitives first appeared in
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.Nx 5.0 .
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