Handle Cyrix CPUs a bit differently. Based on suggestions from Michael
VanLoon.
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1423112c96
commit
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@ -37,7 +37,7 @@
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* SUCH DAMAGE.
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*
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* from: @(#)locore.s 7.3 (Berkeley) 5/13/91
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* $Id: locore.s,v 1.83 1994/09/09 03:16:03 mycroft Exp $
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* $Id: locore.s,v 1.84 1994/10/06 03:36:40 mycroft Exp $
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*/
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/*
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@ -243,24 +243,35 @@ is486: movl $CPU_486,_cpu-KERNBASE
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movl $0x69727943,_cpu_vendor-KERNBASE # store vendor string
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movw $0x0078,_cpu_vendor-KERNBASE+4
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#ifndef notdef
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#ifndef CYRIX_CACHE_WORKS
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/* Disable caching of the ISA hole only. */
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invd
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movb $CCR0,%al # Configuration Register index (CCR0)
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outb %al,$0x22
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inb $0x23,%al
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orb $CCR0_NC1,%al
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orb $(CCR0_NC1|CCR0_BARB),%al
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movb %al,%ah
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movb $CCR0,%al
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outb %al,$0x22
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movb %ah,%al
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outb %al,$0x23
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invd
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#else
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#else /* CYRIX_CACHE_WORKS */
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/* Set cache parameters */
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invd # Start with guaranteed clean cache
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#ifdef CYRIX_CACHE_WORKS
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movb $CCR0,%al # Configuration Register index (CCR0)
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outb %al,$0x22
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inb $0x23,%al
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andb $~CCR0_NC0,%al
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#ifndef CYRIX_CACHE_REALLY_WORKS
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orb $(CCR0_NC1|CCR0_BARB),%al
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#else
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orb $CCR0_NC1,%al
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#endif
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movb %al,%ah
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movb $CCR0,%al
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outb %al,$0x22
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movb %ah,%al
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outb %al,$0x23
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/* clear non-cacheable region 1 */
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movb $(NCR1+2),%al
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@ -286,14 +297,8 @@ is486: movl $CPU_486,_cpu-KERNBASE
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movl %cr0,%eax
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andl $~(CR0_CD|CR0_NW),%eax
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movl %eax,%cr0
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#else
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/* disable caching in CR0 */
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movl %cr0,%eax
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orl $CR0_CD,%eax
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movl %eax,%cr0
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#endif
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invd
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#endif /* notdef */
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#endif /* CYRIX_CACHE_WORKS */
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jmp 2f
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@ -570,21 +575,6 @@ reloc_gdt:
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1:
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#endif
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#ifdef notdef
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cmp $CPU_486DLC,_cpu
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jne 1f
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pushl $2f
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call _printf
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addl $4,%esp
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jmp 1f
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#ifdef CYRIX_CACHE_WORKS
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2: .asciz "WARNING: CYRIX 486DLC CACHE ENABLED.\n"
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#else
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2: .asciz "WARNING: CYRIX 486DLC CACHE DISABLED BY DEFAULT.\n"
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#endif
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1:
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#endif /* notdef */
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INTRFASTEXIT
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/* NOTREACHED */
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@ -36,7 +36,7 @@
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* SUCH DAMAGE.
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*
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* from: @(#)machdep.c 7.4 (Berkeley) 6/3/91
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* $Id: machdep.c,v 1.120 1994/09/07 20:32:45 mycroft Exp $
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* $Id: machdep.c,v 1.121 1994/10/06 03:36:44 mycroft Exp $
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*/
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#include <sys/param.h>
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@ -387,6 +387,18 @@ identifycpu()
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default:
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break;
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}
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if (cpu == CPU_486DLC) {
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#ifndef CYRIX_CACHE_WORKS
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printf("WARNING: CYRIX 486DLC CACHE UNCHANGED.\n");
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#else
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#ifndef CYRIX_CACHE_REALLY_WORKS
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printf("WARNING: CYRIX 486DLC CACHE ENABLED IN HOLD-FLUSH MODE.\n");
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#else
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printf("WARNING: CYRIX 486DLC CACHE ENABLED.\n");
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#endif
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#endif
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}
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}
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/*
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