Make DMA descriptors volatile to avoid unintended reordering which might
cause some race condition.
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parent
d14a7576fc
commit
3fe4f9fc45
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@ -1,4 +1,4 @@
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/* $NetBSD: smc83c170reg.h,v 1.11 2006/04/16 00:38:59 tsutsui Exp $ */
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/* $NetBSD: smc83c170reg.h,v 1.12 2007/02/16 13:43:00 tsutsui Exp $ */
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/*-
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* Copyright (c) 1998 The NetBSD Foundation, Inc.
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@ -49,10 +49,10 @@
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* EPIC transmit descriptor. Must be 4-byte aligned.
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*/
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struct epic_txdesc {
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uint32_t et_txstatus; /* transmit status; see below */
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uint32_t et_bufaddr; /* buffer address */
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uint32_t et_control; /* control word; see below */
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uint32_t et_nextdesc; /* next descriptor pointer */
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volatile uint32_t et_txstatus; /* transmit status; see below */
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volatile uint32_t et_bufaddr; /* buffer address */
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volatile uint32_t et_control; /* control word; see below */
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volatile uint32_t et_nextdesc; /* next descriptor pointer */
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};
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/* et_txstatus */
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@ -86,10 +86,10 @@ struct epic_txdesc {
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* EPIC receive descriptor. Must be 4-byte aligned.
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*/
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struct epic_rxdesc {
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uint32_t er_rxstatus; /* receive status; see below */
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uint32_t er_bufaddr; /* buffer address */
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uint32_t er_control; /* control word; see below */
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uint32_t er_nextdesc; /* next descriptor pointer */
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volatile uint32_t er_rxstatus; /* receive status; see below */
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volatile uint32_t er_bufaddr; /* buffer address */
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volatile uint32_t er_control; /* control word; see below */
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volatile uint32_t er_nextdesc; /* next descriptor pointer */
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};
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/* er_rxstatus */
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@ -126,10 +126,10 @@ struct epic_rxdesc {
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* EPIC fraglist descriptor.
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*/
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struct epic_fraglist {
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uint32_t ef_nfrags; /* number of frags in list */
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volatile uint32_t ef_nfrags; /* number of frags in list */
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struct {
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uint32_t ef_addr; /* address of frag */
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uint32_t ef_length; /* length of frag */
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volatile uint32_t ef_addr; /* address of frag */
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volatile uint32_t ef_length; /* length of frag */
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} ef_frags[EPIC_NFRAGS];
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};
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