More comment/whitespace tidy-up.
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@ -1,4 +1,4 @@
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/* $NetBSD: wdcvar.h,v 1.52 2004/01/03 01:50:53 thorpej Exp $ */
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/* $NetBSD: wdcvar.h,v 1.53 2004/01/03 19:31:09 thorpej Exp $ */
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/*-
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* Copyright (c) 1998, 2003 The NetBSD Foundation, Inc.
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@ -50,22 +50,25 @@
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#define WDC_NREG 8 /* number of command registers */
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struct wdc_channel { /* Per channel data */
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/* Our timeout callout */
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struct callout ch_callout;
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/* Our location */
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int channel;
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/* Our controller's softc */
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struct wdc_softc *wdc;
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/*
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* Per-channel data
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*/
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struct wdc_channel {
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struct callout ch_callout; /* callout handle */
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int channel; /* location */
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struct wdc_softc *wdc; /* controller's softc */
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/* Our registers */
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bus_space_tag_t cmd_iot;
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bus_space_handle_t cmd_baseioh;
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bus_space_handle_t cmd_iohs[WDC_NREG];
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bus_space_tag_t ctl_iot;
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bus_space_handle_t ctl_ioh;
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/* data32{iot,ioh} are only used for 32 bit data xfers */
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bus_space_tag_t data32iot;
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bus_space_handle_t data32ioh;
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/* Our state */
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int ch_flags;
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#define WDCF_ACTIVE 0x01 /* channel is active */
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@ -75,32 +78,38 @@ struct wdc_channel { /* Per channel data */
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#define WDCF_DISABLED 0x80 /* channel is disabled */
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#define WDCF_TH_RUN 0x100 /* the kenrel thread is working */
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#define WDCF_TH_RESET 0x200 /* someone ask the thread to reset */
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u_int8_t ch_status; /* copy of status register */
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u_int8_t ch_error; /* copy of error register */
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/* per-drive infos */
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u_int8_t ch_status; /* copy of status register */
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u_int8_t ch_error; /* copy of error register */
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/* per-drive info */
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struct ata_drive_datas ch_drive[2];
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struct device *atabus; /* self */
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struct device *atapibus; /* children */
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/* ATAPI children */
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struct device *atapibus;
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struct scsipi_channel ch_atapi_channel;
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struct device *ata_drives[2]; /* children */
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/* ATA children */
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struct device *ata_drives[2];
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/*
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* channel queues. May be the same for all channels, if hw channels
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* are not independent.
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* Channel queues. May be the same for all channels, if hw
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* channels are not independent.
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*/
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struct ata_queue *ch_queue;
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/* the channel kernel thread */
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/* The channel kernel thread */
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struct proc *thread;
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};
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struct wdc_softc { /* Per controller state */
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struct device sc_dev;
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/* mandatory fields */
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int cap;
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/* Capabilities supported by the controller */
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/*
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* Per-controller data
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*/
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struct wdc_softc {
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struct device sc_dev; /* generic device info */
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int cap; /* controller capabilities */
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#define WDC_CAPABILITY_DATA16 0x0001 /* can do 16-bit data access */
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#define WDC_CAPABILITY_DATA32 0x0002 /* can do 32-bit data access */
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#define WDC_CAPABILITY_MODE 0x0004 /* controller knows its PIO/DMA modes */
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@ -110,16 +119,16 @@ struct wdc_softc { /* Per controller state */
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#define WDC_CAPABILITY_ATA_NOSTREAM 0x0040 /* Don't use stream funcs on ATA */
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#define WDC_CAPABILITY_ATAPI_NOSTREAM 0x0080 /* Don't use stream f on ATAPI */
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#define WDC_CAPABILITY_NO_EXTRA_RESETS 0x0100 /* only reset once */
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#define WDC_CAPABILITY_PREATA 0x0200 /* ctrl can be a pre-ata one */
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#define WDC_CAPABILITY_IRQACK 0x0400 /* callback to ack interrupt */
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#define WDC_CAPABILITY_PREATA 0x0200 /* ctrl can be a pre-ata one */
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#define WDC_CAPABILITY_IRQACK 0x0400 /* callback to ack interrupt */
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#define WDC_CAPABILITY_NOIRQ 0x1000 /* Controller never interrupts */
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#define WDC_CAPABILITY_SELECT 0x2000 /* Controller selects target */
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#define WDC_CAPABILITY_RAID 0x4000 /* Controller "supports" RAID */
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u_int8_t PIO_cap; /* highest PIO mode supported */
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u_int8_t DMA_cap; /* highest DMA mode supported */
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u_int8_t UDMA_cap; /* highest UDMA mode supported */
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int nchannels; /* Number of channels on this controller */
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struct wdc_channel **channels; /* channels-specific datas (array) */
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u_int8_t PIO_cap; /* highest PIO mode supported */
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u_int8_t DMA_cap; /* highest DMA mode supported */
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u_int8_t UDMA_cap; /* highest UDMA mode supported */
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int nchannels; /* # channels on this controller */
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struct wdc_channel **channels; /* channel-specific data (array) */
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/*
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* The reference count here is used for both IDE and ATAPI devices.
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