sparc64_ipi_save_fpstate:
- use primary MMU context for consistency with other trap/interrupt handlers. sparc64_ipi_save_fpstate, savefpstate: - avoid storing fp registers as we can. sparc64_ipi_save_fpstate, savefpstate, loadfpstate: - remove unaligned case since buffers allocated with pool_cache are ensured 64-byte aligned. Ok by martin@.
This commit is contained in:
nakayama
parent
b74ec3e6b6
commit
3eac605929
@ -1,4 +1,4 @@
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/* $NetBSD: db_machdep.h,v 1.24 2008/02/29 20:27:07 martin Exp $ */
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/* $NetBSD: db_machdep.h,v 1.25 2008/07/10 15:23:58 nakayama Exp $ */
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/*
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* Mach Operating System
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@ -56,7 +56,7 @@ typedef struct {
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struct frame64 db_fr;
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struct trapstate db_ts[5];
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int db_tl;
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struct fpstate64 db_fpstate;
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struct fpstate64 db_fpstate __aligned(BLOCK_SIZE);
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} db_regs_t;
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/* Current CPU register state */
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@ -1,4 +1,4 @@
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/* $NetBSD: cpu.c,v 1.76 2008/07/10 15:04:41 nakayama Exp $ */
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/* $NetBSD: cpu.c,v 1.77 2008/07/10 15:23:58 nakayama Exp $ */
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/*
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* Copyright (c) 1996
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@ -52,7 +52,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.76 2008/07/10 15:04:41 nakayama Exp $");
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__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.77 2008/07/10 15:23:58 nakayama Exp $");
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#include "opt_multiprocessor.h"
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@ -184,7 +184,7 @@ cpu_reset_fpustate(void)
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struct fpstate64 *fpstate;
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struct fpstate64 fps[2];
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/* This needs to be 64-bit aligned */
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/* This needs to be 64-byte aligned */
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fpstate = ALIGNFPSTATE(&fps[1]);
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/*
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@ -1,4 +1,4 @@
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/* $NetBSD: locore.s,v 1.282 2008/07/02 12:15:19 nakayama Exp $ */
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/* $NetBSD: locore.s,v 1.283 2008/07/10 15:23:58 nakayama Exp $ */
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/*
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* Copyright (c) 1996-2002 Eduardo Horvath
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@ -9492,120 +9492,76 @@ ENTRY(sparc64_ipi_save_fpstate)
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sethi %hi(FPLWP), %g1
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LDPTR [%g1 + %lo(FPLWP)], %g3
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cmp %g3, %g2
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bne,pn CCCR, 7f ! skip if fplwp != %g2
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bne,pn CCCR, 7f ! skip if fplwp has changed
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mov CTX_SECONDARY, %g5
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ldxa [%g5] ASI_DMMU, %g6
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membar #LoadStore
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stxa %g0, [%g5] ASI_DMMU
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membar #Sync
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LDPTR [%g3 + L_FPSTATE], %g3
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rdpr %pstate, %g2 ! enable FP before we begin
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rdpr %pstate, %g2 ! enable FP before we begin
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rd %fprs, %g5
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wr %g0, FPRS_FEF, %fprs
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or %g2, PSTATE_PEF, %g2
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wrpr %g2, 0, %pstate
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LDPTR [%g3 + L_FPSTATE], %g3
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stx %fsr, [%g3 + FS_FSR] ! f->fs_fsr = getfsr();
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rd %gsr, %g2 ! Save %gsr
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st %g2, [%g3 + FS_GSR]
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#if FS_REGS > 0
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add %g3, FS_REGS, %g3
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#endif
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#ifdef DIAGNOSTIC
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btst BLOCK_ALIGN, %g3 ! Needs to be re-executed
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bnz,pn %icc, 3f ! Check alignment
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bnz,pn %icc, 6f ! Check alignment
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#endif
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st %g0, [%g3 + FS_QSIZE - FS_REGS] ! f->fs_qsize = 0;
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btst FPRS_DL, %g5 ! Lower FPU clean?
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bz,a,pt %icc, 1f ! Then skip it
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add %g3, 128, %g3 ! Skip a block
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btst FPRS_DL|FPRS_DU, %g5 ! Both FPU halves clean?
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bz,pt %icc, 5f ! Then skip it
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mov CTX_PRIMARY, %g2
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ldxa [%g2] ASI_DMMU, %g6
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membar #LoadStore
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stxa %g0, [%g2] ASI_DMMU ! Switch MMU to kernel primary context
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membar #Sync
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stda %f0, [%g3] ASI_BLK_S ! f->fs_f0 = etc;
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btst FPRS_DL, %g5 ! Lower FPU clean?
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bz,a,pt %icc, 1f ! Then skip it, but upper FPU not clean
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add %g3, 2*BLOCK_SIZE, %g3 ! Skip a block
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stda %f0, [%g3] ASI_BLK_P ! f->fs_f0 = etc;
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inc BLOCK_SIZE, %g3
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stda %f16, [%g3] ASI_BLK_S
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inc BLOCK_SIZE, %g3
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1:
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stda %f16, [%g3] ASI_BLK_P
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btst FPRS_DU, %g5 ! Upper FPU clean?
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bz,pt %icc, 2f ! Then skip it
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nop
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membar #Sync
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stda %f32, [%g3] ASI_BLK_S
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inc BLOCK_SIZE, %g3
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1:
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stda %f32, [%g3] ASI_BLK_P
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inc BLOCK_SIZE, %g3
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stda %f48, [%g3] ASI_BLK_S
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stda %f48, [%g3] ASI_BLK_P
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2:
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membar #Sync ! Finish operation so we can
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wr %g0, FPRS_FEF, %fprs ! Mark FPU clean
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mov CTX_SECONDARY, %g5
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STPTR %g0, [%g1 + %lo(FPLWP)] ! fplwp = NULL
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stxa %g6, [%g5] ASI_DMMU
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brz,pn %g6, 5f ! Skip if context 0
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nop
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stxa %g6, [%g2] ASI_DMMU ! Restore primary context
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membar #Sync
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5:
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wr %g0, FPRS_FEF, %fprs ! Mark FPU clean
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STPTR %g0, [%g1 + %lo(FPLWP)] ! fplwp = NULL
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7:
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IPIEVC_INC(IPI_EVCNT_FPU_SYNCH,%g2,%g3)
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ba,a ret_from_intr_vector
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nop
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3:
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#ifdef DIAGONSTIC
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btst 7, %g3 ! 32-bit aligned!?!?
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bnz,pn %icc, 6f
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#endif
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btst FPRS_DL, %g5 ! Lower FPU clean?
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bz,a,pt %icc, 4f ! Then skip it
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add %g3, 128, %g3
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membar #Sync
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std %f0, [%g3 + FS_REGS + (4*0)] ! f->fs_f0 = etc;
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std %f2, [%g3 + FS_REGS + (4*2)]
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std %f4, [%g3 + FS_REGS + (4*4)]
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std %f6, [%g3 + FS_REGS + (4*6)]
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std %f8, [%g3 + FS_REGS + (4*8)]
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std %f10, [%g3 + FS_REGS + (4*10)]
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std %f12, [%g3 + FS_REGS + (4*12)]
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std %f14, [%g3 + FS_REGS + (4*14)]
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std %f16, [%g3 + FS_REGS + (4*16)]
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std %f18, [%g3 + FS_REGS + (4*18)]
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std %f20, [%g3 + FS_REGS + (4*20)]
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std %f22, [%g3 + FS_REGS + (4*22)]
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std %f24, [%g3 + FS_REGS + (4*24)]
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std %f26, [%g3 + FS_REGS + (4*26)]
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std %f28, [%g3 + FS_REGS + (4*28)]
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std %f30, [%g3 + FS_REGS + (4*30)]
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4:
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btst FPRS_DU, %g5 ! Upper FPU clean?
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bz,pt %icc, 2b ! Then skip it
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nop
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membar #Sync
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std %f32, [%g3 + FS_REGS + (4*32)]
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std %f34, [%g3 + FS_REGS + (4*34)]
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std %f36, [%g3 + FS_REGS + (4*36)]
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std %f38, [%g3 + FS_REGS + (4*38)]
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std %f40, [%g3 + FS_REGS + (4*40)]
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std %f42, [%g3 + FS_REGS + (4*42)]
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std %f44, [%g3 + FS_REGS + (4*44)]
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std %f46, [%g3 + FS_REGS + (4*46)]
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std %f48, [%g3 + FS_REGS + (4*48)]
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std %f50, [%g3 + FS_REGS + (4*50)]
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std %f52, [%g3 + FS_REGS + (4*52)]
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std %f54, [%g3 + FS_REGS + (4*54)]
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std %f56, [%g3 + FS_REGS + (4*56)]
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std %f58, [%g3 + FS_REGS + (4*58)]
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std %f60, [%g3 + FS_REGS + (4*60)]
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ba 2b
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std %f62, [%g3 + FS_REGS + (4*62)]
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#ifdef DIAGNOSTIC
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!!
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!! Damn thing is *NOT* aligned on a 64-byte boundary
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!!
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6:
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wr %g0, FPRS_FEF, %fprs
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! XXX -- we should panic instead of silently entering debugger
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ta 1
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nop
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ba,a ret_from_intr_vector
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nop
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#endif
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/*
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* IPI handler to drop the current FPU state.
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@ -9661,92 +9617,47 @@ ENTRY(savefpstate)
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st %o4, [%o0 + FS_GSR]
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add %o0, FS_REGS, %o2
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#ifdef DIAGNOSTIC
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btst BLOCK_ALIGN, %o2 ! Needs to be re-executed
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bnz,pn %icc, 3f ! Check alignment
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bnz,pn %icc, 6f ! Check alignment
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#endif
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st %g0, [%o0 + FS_QSIZE] ! f->fs_qsize = 0;
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btst FPRS_DL, %o5 ! Lower FPU clean?
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bz,a,pt %icc, 1f ! Then skip it
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add %o2, 128, %o2 ! Skip a block
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btst FPRS_DL|FPRS_DU, %o5 ! Both FPU halves clean?
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bz,pt %icc, 5f ! Then skip it
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btst FPRS_DL, %o5 ! Lower FPU clean?
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membar #Sync
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stda %f0, [%o2] ASI_BLK_COMMIT_P ! f->fs_f0 = etc;
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bz,a,pt %icc, 1f ! Then skip it, but upper FPU not clean
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add %o2, 2*BLOCK_SIZE, %o2 ! Skip a block
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stda %f0, [%o2] ASI_BLK_P ! f->fs_f0 = etc;
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inc BLOCK_SIZE, %o2
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stda %f16, [%o2] ASI_BLK_COMMIT_P
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inc BLOCK_SIZE, %o2
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1:
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stda %f16, [%o2] ASI_BLK_P
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btst FPRS_DU, %o5 ! Upper FPU clean?
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bz,pt %icc, 2f ! Then skip it
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nop
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membar #Sync
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stda %f32, [%o2] ASI_BLK_COMMIT_P
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inc BLOCK_SIZE, %o2
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1:
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stda %f32, [%o2] ASI_BLK_P
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inc BLOCK_SIZE, %o2
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stda %f48, [%o2] ASI_BLK_COMMIT_P
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stda %f48, [%o2] ASI_BLK_P
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2:
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membar #Sync ! Finish operation so we can
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5:
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retl
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wr %g0, FPRS_FEF, %fprs ! Mark FPU clean
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3:
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#ifdef DIAGONSTIC
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btst 7, %o2 ! 32-bit aligned!?!?
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bnz,pn %icc, 6f
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#endif
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btst FPRS_DL, %o5 ! Lower FPU clean?
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bz,a,pt %icc, 4f ! Then skip it
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add %o0, 128, %o0
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membar #Sync
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std %f0, [%o0 + FS_REGS + (4*0)] ! f->fs_f0 = etc;
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std %f2, [%o0 + FS_REGS + (4*2)]
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std %f4, [%o0 + FS_REGS + (4*4)]
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std %f6, [%o0 + FS_REGS + (4*6)]
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std %f8, [%o0 + FS_REGS + (4*8)]
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std %f10, [%o0 + FS_REGS + (4*10)]
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std %f12, [%o0 + FS_REGS + (4*12)]
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std %f14, [%o0 + FS_REGS + (4*14)]
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std %f16, [%o0 + FS_REGS + (4*16)]
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std %f18, [%o0 + FS_REGS + (4*18)]
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std %f20, [%o0 + FS_REGS + (4*20)]
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std %f22, [%o0 + FS_REGS + (4*22)]
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std %f24, [%o0 + FS_REGS + (4*24)]
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std %f26, [%o0 + FS_REGS + (4*26)]
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std %f28, [%o0 + FS_REGS + (4*28)]
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std %f30, [%o0 + FS_REGS + (4*30)]
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4:
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btst FPRS_DU, %o5 ! Upper FPU clean?
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bz,pt %icc, 5f ! Then skip it
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nop
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membar #Sync
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std %f32, [%o0 + FS_REGS + (4*32)]
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std %f34, [%o0 + FS_REGS + (4*34)]
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std %f36, [%o0 + FS_REGS + (4*36)]
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std %f38, [%o0 + FS_REGS + (4*38)]
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std %f40, [%o0 + FS_REGS + (4*40)]
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std %f42, [%o0 + FS_REGS + (4*42)]
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std %f44, [%o0 + FS_REGS + (4*44)]
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std %f46, [%o0 + FS_REGS + (4*46)]
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std %f48, [%o0 + FS_REGS + (4*48)]
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std %f50, [%o0 + FS_REGS + (4*50)]
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std %f52, [%o0 + FS_REGS + (4*52)]
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std %f54, [%o0 + FS_REGS + (4*54)]
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std %f56, [%o0 + FS_REGS + (4*56)]
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std %f58, [%o0 + FS_REGS + (4*58)]
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std %f60, [%o0 + FS_REGS + (4*60)]
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std %f62, [%o0 + FS_REGS + (4*62)]
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5:
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membar #Sync
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retl
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wr %g0, FPRS_FEF, %fprs ! Mark FPU clean
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#ifdef DIAGNOSTIC
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!!
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!! Damn thing is *NOT* aligned on a 64-bit boundary
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!! Damn thing is *NOT* aligned on a 64-byte boundary
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!!
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6:
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wr %g0, FPRS_FEF, %fprs
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! XXX -- we should panic instead of silently entering debugger
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ta 1
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retl
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nop
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#endif
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/*
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* Load FPU state.
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@ -9762,8 +9673,10 @@ ENTRY(loadfpstate)
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wrpr %o1, 0, %pstate
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ldx [%o0 + FS_FSR], %fsr ! setfsr(f->fs_fsr);
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add %o0, FS_REGS, %o3 ! This is zero...
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#ifdef DIAGNOSTIC
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btst BLOCK_ALIGN, %o3
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bne,pt %icc, 1f ! Only use block loads on aligned blocks
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bne,pn %icc, 1f ! Only use block loads on aligned blocks
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#endif
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wr %o4, %g0, %gsr
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membar #Sync
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ldda [%o3] ASI_BLK_P, %f0
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@ -9776,55 +9689,19 @@ ENTRY(loadfpstate)
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membar #Sync ! Make sure loads are complete
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retl
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wr %g0, FPRS_FEF, %fprs ! Clear dirty bits
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1:
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#ifdef DIAGNOSTIC
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btst 7, %o3
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bne,pn %icc, 1f
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nop
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#endif
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/* Unaligned -- needs to be done the long way */
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membar #Sync
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ldd [%o3 + (4*0)], %f0
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ldd [%o3 + (4*2)], %f2
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ldd [%o3 + (4*4)], %f4
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ldd [%o3 + (4*6)], %f6
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ldd [%o3 + (4*8)], %f8
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ldd [%o3 + (4*10)], %f10
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ldd [%o3 + (4*12)], %f12
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ldd [%o3 + (4*14)], %f14
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ldd [%o3 + (4*16)], %f16
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ldd [%o3 + (4*18)], %f18
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ldd [%o3 + (4*20)], %f20
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ldd [%o3 + (4*22)], %f22
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ldd [%o3 + (4*24)], %f24
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ldd [%o3 + (4*26)], %f26
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ldd [%o3 + (4*28)], %f28
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ldd [%o3 + (4*30)], %f30
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ldd [%o3 + (4*32)], %f32
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ldd [%o3 + (4*34)], %f34
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ldd [%o3 + (4*36)], %f36
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ldd [%o3 + (4*38)], %f38
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ldd [%o3 + (4*40)], %f40
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ldd [%o3 + (4*42)], %f42
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ldd [%o3 + (4*44)], %f44
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ldd [%o3 + (4*46)], %f46
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ldd [%o3 + (4*48)], %f48
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ldd [%o3 + (4*50)], %f50
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ldd [%o3 + (4*52)], %f52
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ldd [%o3 + (4*54)], %f54
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ldd [%o3 + (4*56)], %f56
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ldd [%o3 + (4*58)], %f58
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ldd [%o3 + (4*60)], %f60
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ldd [%o3 + (4*62)], %f62
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membar #Sync
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retl
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wr %g0, FPRS_FEF, %fprs ! Clear dirty bits
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#ifdef DIAGNOSTIC
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!!
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!! Damn thing is *NOT* aligned on a 64-byte boundary
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!!
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1:
|
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wr %g0, FPRS_FEF, %fprs ! Clear dirty bits
|
||||
! XXX -- we should panic instead of silently entering debugger
|
||||
ta 1
|
||||
retl
|
||||
nop
|
||||
#endif
|
||||
|
||||
/*
|
||||
* ienab_bis(bis) int bis;
|
||||
* ienab_bic(bic) int bic;
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: trap.c,v 1.152 2008/07/10 15:04:42 nakayama Exp $ */
|
||||
/* $NetBSD: trap.c,v 1.153 2008/07/10 15:23:58 nakayama Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1996-2002 Eduardo Horvath. All rights reserved.
|
||||
@ -50,7 +50,7 @@
|
||||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__KERNEL_RCSID(0, "$NetBSD: trap.c,v 1.152 2008/07/10 15:04:42 nakayama Exp $");
|
||||
__KERNEL_RCSID(0, "$NetBSD: trap.c,v 1.153 2008/07/10 15:23:58 nakayama Exp $");
|
||||
|
||||
#include "opt_ddb.h"
|
||||
#include "opt_multiprocessor.h"
|
||||
@ -173,8 +173,7 @@ int trapdebug = 0/*|TDB_SYSCALL|TDB_STOPSIG|TDB_STOPCPIO|TDB_ADDFLT|TDB_FOLLOW*/
|
||||
* set, no matter how it is interpreted. Appendix N of the Sparc V8 document
|
||||
* seems to imply that we should do this, and it does make sense.
|
||||
*/
|
||||
__asm(".align 64");
|
||||
const struct fpstate64 initfpstate = {
|
||||
const struct fpstate64 initfpstate __aligned(BLOCK_SIZE) = {
|
||||
.fs_regs =
|
||||
{ ~0, ~0, ~0, ~0, ~0, ~0, ~0, ~0, ~0, ~0, ~0, ~0, ~0, ~0, ~0, ~0,
|
||||
~0, ~0, ~0, ~0, ~0, ~0, ~0, ~0, ~0, ~0, ~0, ~0, ~0, ~0, ~0, ~0,
|
||||
@ -668,7 +667,7 @@ badtrap:
|
||||
struct fpstate64 *fs = l->l_md.md_fpstate;
|
||||
|
||||
if (fs == NULL) {
|
||||
/* NOTE: fpstate must be 64-bit aligned */
|
||||
/* NOTE: fpstate must be 64-byte aligned */
|
||||
fs = pool_cache_get(fpstate_cache, PR_WAITOK);
|
||||
*fs = initfpstate;
|
||||
l->l_md.md_fpstate = fs;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user