hdaudio: pci: PCIe config space fixes and Intel PCH snoop support
The HD audio specification does not cover PCI config space, and this driver was unconditionally writing to a vendor specific register. Reduce scope of config space accesses based on PCI IDs. With this cleaned up, add support for Intel PCH devices which require some additional vendor specific configuration to bypass no snoop mode.
This commit is contained in:
jmcneill
parent
eae1841cdb
commit
3e8c9d8ae9
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@ -1,4 +1,4 @@
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/* $NetBSD: hdaudioreg.h,v 1.3 2019/01/07 01:03:05 mrg Exp $ */
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/* $NetBSD: hdaudioreg.h,v 1.4 2022/03/21 09:12:10 jmcneill Exp $ */
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/*
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* Copyright (c) 2009 Precedence Technologies Ltd <support@precedence.co.uk>
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@ -35,14 +35,6 @@
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#include <sys/cdefs.h>
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#include <sys/types.h>
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/*
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* High Definition Audio Audio PCI Configuration Space
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*/
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#define HDAUDIO_PCI_AZBARL 0x10
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#define HDAUDIO_PCI_AZBARU 0x14
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#define HDAUDIO_PCI_AZCTL 0x40
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#define HDAUDIO_PCI_TCSEL 0x44
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/*
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* High Definition Audio Memory Mapped Configuration Registers
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*/
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@ -1,4 +1,4 @@
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/* $NetBSD: hdaudio_pci.c,v 1.11 2021/10/28 09:15:35 msaitoh Exp $ */
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/* $NetBSD: hdaudio_pci.c,v 1.12 2022/03/21 09:12:09 jmcneill Exp $ */
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/*
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* Copyright (c) 2009 Precedence Technologies Ltd <support@precedence.co.uk>
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@ -34,7 +34,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: hdaudio_pci.c,v 1.11 2021/10/28 09:15:35 msaitoh Exp $");
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__KERNEL_RCSID(0, "$NetBSD: hdaudio_pci.c,v 1.12 2022/03/21 09:12:09 jmcneill Exp $");
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#include <sys/types.h>
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#include <sys/param.h>
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@ -61,6 +61,11 @@ struct hdaudio_pci_softc {
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pci_intr_handle_t *sc_pihp;
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};
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#define HDAUDIO_PCI_IS_INTEL(sc) \
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(PCI_VENDOR(sc->sc_id) == PCI_VENDOR_INTEL)
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#define HDAUDIO_PCI_IS_NVIDIA(sc) \
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(PCI_VENDOR(sc->sc_id) == PCI_VENDOR_NVIDIA)
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static int hdaudio_pci_match(device_t, cfdata_t, void *);
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static void hdaudio_pci_attach(device_t, device_t, void *);
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static int hdaudio_pci_detach(device_t, int);
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@ -68,7 +73,7 @@ static int hdaudio_pci_rescan(device_t, const char *, const int *);
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static void hdaudio_pci_childdet(device_t, device_t);
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static int hdaudio_pci_intr(void *);
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static void hdaudio_pci_reinit(struct hdaudio_pci_softc *);
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static void hdaudio_pci_init(struct hdaudio_pci_softc *);
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/* power management */
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static bool hdaudio_pci_resume(device_t, const pmf_qual_t *);
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@ -139,7 +144,7 @@ hdaudio_pci_attach(device_t parent, device_t self, void *opaque)
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pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, csr);
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/* Map MMIO registers */
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reg = HDAUDIO_PCI_AZBARL;
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reg = PCI_BAR0;
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maptype = pci_mapreg_type(sc->sc_pc, sc->sc_tag, reg);
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err = pci_mapreg_map(pa, reg, maptype, 0,
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&sc->sc_hdaudio.sc_memt,
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@ -174,7 +179,7 @@ hdaudio_pci_attach(device_t parent, device_t self, void *opaque)
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}
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aprint_normal_dev(self, "interrupting at %s\n", intrstr);
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hdaudio_pci_reinit(sc);
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hdaudio_pci_init(sc);
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/* Attach bus-independent HD audio layer */
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if (hdaudio_attach(self, &sc->sc_hdaudio)) {
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@ -187,15 +192,18 @@ hdaudio_pci_attach(device_t parent, device_t self, void *opaque)
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sc->sc_hdaudio.sc_memvalid = false;
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csr = pci_conf_read(sc->sc_pc, sc->sc_tag,
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PCI_COMMAND_STATUS_REG);
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csr &= ~(PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_BACKTOBACK_ENABLE);
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csr &= ~(PCI_COMMAND_MASTER_ENABLE |
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PCI_COMMAND_BACKTOBACK_ENABLE);
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pci_conf_write(sc->sc_pc, sc->sc_tag,
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PCI_COMMAND_STATUS_REG, csr);
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if (!pmf_device_register(self, NULL, NULL))
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aprint_error_dev(self, "couldn't establish power handler\n");
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}
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else if (!pmf_device_register(self, NULL, hdaudio_pci_resume))
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if (!pmf_device_register(self, NULL, NULL)) {
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aprint_error_dev(self,
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"couldn't establish power handler\n");
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}
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} else if (!pmf_device_register(self, NULL, hdaudio_pci_resume)) {
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aprint_error_dev(self, "couldn't establish power handler\n");
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}
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}
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static int
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@ -252,28 +260,51 @@ hdaudio_pci_intr(void *opaque)
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return hdaudio_intr(&sc->sc_hdaudio);
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}
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static void
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hdaudio_pci_reinit(struct hdaudio_pci_softc *sc)
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hdaudio_pci_init(struct hdaudio_pci_softc *sc)
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{
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pcireg_t val;
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/* stops playback static */
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val = pci_conf_read(sc->sc_pc, sc->sc_tag, HDAUDIO_PCI_TCSEL);
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val &= ~7;
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val |= 0;
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pci_conf_write(sc->sc_pc, sc->sc_tag, HDAUDIO_PCI_TCSEL, val);
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if (HDAUDIO_PCI_IS_INTEL(sc)) {
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/*
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* ICH: Set traffic class for input/output/buf descriptors
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* to TC0. For PCH without a TCSEL register, PGCTL is in
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* the same location and clearing these bits is harmless.
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*/
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val = pci_conf_read(sc->sc_pc, sc->sc_tag,
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HDAUDIO_INTEL_REG_ICH_TCSEL);
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val &= ~HDAUDIO_INTEL_ICH_TCSEL_MASK;
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val |= HDAUDIO_INTEL_ICH_TCSEL_TC0;
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pci_conf_write(sc->sc_pc, sc->sc_tag,
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HDAUDIO_INTEL_REG_ICH_TCSEL, val);
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switch (PCI_VENDOR(sc->sc_id)) {
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case PCI_VENDOR_NVIDIA:
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/* enable snooping */
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/*
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* PCH: Disable dynamic clock gating logic. Implementations
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* without a CGCTL register do not appear to have anything
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* else in its place.
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*/
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val = pci_conf_read(sc->sc_pc, sc->sc_tag,
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HDAUDIO_INTEL_REG_PCH_CGCTL);
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val &= ~HDAUDIO_INTEL_PCH_CGCTL_MISCBDCGE;
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pci_conf_write(sc->sc_pc, sc->sc_tag,
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HDAUDIO_INTEL_REG_PCH_CGCTL, val);
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/* ICH/PCH: Enable snooping. */
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val = pci_conf_read(sc->sc_pc, sc->sc_tag,
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HDAUDIO_INTEL_REG_PCH_DEVC);
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val &= ~HDAUDIO_INTEL_PCH_DEVC_NSNPEN;
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pci_conf_write(sc->sc_pc, sc->sc_tag,
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HDAUDIO_INTEL_REG_PCH_DEVC, val);
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}
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if (HDAUDIO_PCI_IS_NVIDIA(sc)) {
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/* Enable snooping. */
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val = pci_conf_read(sc->sc_pc, sc->sc_tag,
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HDAUDIO_NV_REG_SNOOP);
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val &= ~HDAUDIO_NV_SNOOP_MASK;
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val |= HDAUDIO_NV_SNOOP_ENABLE;
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pci_conf_write(sc->sc_pc, sc->sc_tag,
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HDAUDIO_NV_REG_SNOOP, val);
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break;
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}
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}
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@ -282,7 +313,8 @@ hdaudio_pci_resume(device_t self, const pmf_qual_t *qual)
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{
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struct hdaudio_pci_softc *sc = device_private(self);
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hdaudio_pci_reinit(sc);
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hdaudio_pci_init(sc);
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return hdaudio_resume(&sc->sc_hdaudio);
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}
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@ -1,4 +1,4 @@
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/* $NetBSD: hdaudio_pci.h,v 1.1 2015/03/28 14:09:59 jmcneill Exp $ */
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/* $NetBSD: hdaudio_pci.h,v 1.2 2022/03/21 09:12:09 jmcneill Exp $ */
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/*
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* Copyright (c) 2010 Jared D. McNeill <jmcneill@invisible.ca>
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@ -31,8 +31,20 @@
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#ifndef _HDAUDIO_PCI_H
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#define _HDAUDIO_PCI_H
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#define HDAUDIO_NV_REG_SNOOP 0x4c
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#define HDAUDIO_NV_SNOOP_MASK 0x00ff0000
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#define HDAUDIO_NV_SNOOP_ENABLE 0x000f0000
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/* NVIDIA specific registers */
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#define HDAUDIO_NV_REG_SNOOP 0x4c
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#define HDAUDIO_NV_SNOOP_MASK 0x00ff0000
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#define HDAUDIO_NV_SNOOP_ENABLE 0x000f0000
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/* Intel ICH specific registers */
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#define HDAUDIO_INTEL_REG_ICH_TCSEL 0x44
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#define HDAUDIO_INTEL_ICH_TCSEL_MASK __BITS(2,0)
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#define HDAUDIO_INTEL_ICH_TCSEL_TC0 0
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/* Intel 100 Series Chipset Family Platform Controller Hub (PCH) */
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#define HDAUDIO_INTEL_REG_PCH_CGCTL 0x48
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#define HDAUDIO_INTEL_PCH_CGCTL_MISCBDCGE __BIT(6)
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#define HDAUDIO_INTEL_REG_PCH_DEVC 0x78
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#define HDAUDIO_INTEL_PCH_DEVC_NSNPEN __BIT(11)
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#endif /* !_HDAUDIO_PCI_H */
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