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This commit is contained in:
msaitoh 2017-08-17 01:05:51 +00:00
parent e9a2d4fa2a
commit 3e4c5bfebb
2 changed files with 5542 additions and 5288 deletions
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82
sys/dev/pci/pcidevs.h
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@ -1,10 +1,10 @@
/* $NetBSD: pcidevs.h,v 1.1289 2017/08/02 07:35:47 msaitoh Exp $ */
/* $NetBSD: pcidevs.h,v 1.1290 2017/08/17 01:05:51 msaitoh Exp $ */
/*
* THIS FILE IS AUTOMATICALLY GENERATED. DO NOT EDIT.
*
* generated from:
* NetBSD: pcidevs,v 1.1296 2017/08/02 07:35:05 msaitoh Exp
* NetBSD: pcidevs,v 1.1297 2017/08/17 01:05:22 msaitoh Exp
*/
/*
@ -3064,6 +3064,8 @@
#define PCI_PRODUCT_INTEL_82380AB 0x123c /* 82380AB (MISA) Mobile PCI-ISA Bridge */
#define PCI_PRODUCT_INTEL_82380FB 0x124b /* 82380FB (MPCI2) Mobile PCI-PCI Bridge */
#define PCI_PRODUCT_INTEL_82439HX 0x1250 /* 82439HX (TXC) System Controller */
#define PCI_PRODUCT_INTEL_C3K_X553_10G 0x1306 /* C3000 X553 10G Ethernet */
#define PCI_PRODUCT_INTEL_C3K_X553_1G 0x1307 /* C3000 X553 1G Ethernet */
#define PCI_PRODUCT_INTEL_82870P2_PPB 0x1460 /* 82870P2 P64H2 PCI-PCI Bridge */
#define PCI_PRODUCT_INTEL_82870P2_IOxAPIC 0x1461 /* 82870P2 P64H2 IOxAPIC */
#define PCI_PRODUCT_INTEL_82870P2_HPLUG 0x1462 /* 82870P2 P64H2 Hot Plug Controller */
@ -3150,14 +3152,25 @@
#define PCI_PRODUCT_INTEL_X552_SFP 0x15ac /* X552 SFP+ */
#define PCI_PRODUCT_INTEL_X557_AT2 0x15ad /* X557-AT2 */
#define PCI_PRODUCT_INTEL_X552_1G_T 0x15ae /* X552 1000Base-T */
#define PCI_PRODUCT_INTEL_C3K_X553_VF_HYPV 0x15b4 /* C3000 X553 VF (Hyper-V) */
#define PCI_PRODUCT_INTEL_I219_LM2 0x15b7 /* I219-LM Ethernet Connection */
#define PCI_PRODUCT_INTEL_I219_V2 0x15b8 /* I219-V Ethernet Connection */
#define PCI_PRODUCT_INTEL_I219_LM3 0x15b9 /* I219-LM Ethernet Connection */
#define PCI_PRODUCT_INTEL_C3K_X553_KRKX 0x15c2 /* C3000 X553 Backplane (KR/KX 10G SKU) */
#define PCI_PRODUCT_INTEL_C3K_X553_KX_25G 0x15c3 /* C3000 X553 Backplane (KX 2.5G) */
#define PCI_PRODUCT_INTEL_C3K_X553_SFI_SFP 0x15c4 /* C3000 X553 10G SFP+ */
#define PCI_PRODUCT_INTEL_C3K_X553_VF 0x15c5 /* C3000 X553 VF */
#define PCI_PRODUCT_INTEL_C3K_X553_SGMII_BP 0x15c6 /* C3000 X553 1GbE SGMII Backplane (10G SKU) */
#define PCI_PRODUCT_INTEL_C3K_X553_SGMII_BP_L 0x15c7 /* C3000 X553 1GbE SGMII Backplane (non-10G SKU) */
#define PCI_PRODUCT_INTEL_C3K_X553_10G_T 0x15c8 /* C3000 X553 10GBASE-T (X557) */
#define PCI_PRODUCT_INTEL_C3K_X553_KR_SFP 0x15ce /* C3000 X553 10G SFP+ */
#define PCI_PRODUCT_INTEL_X550T1 0x15d1 /* X550 10G Ethernet */
#define PCI_PRODUCT_INTEL_I219_V5 0x15d6 /* I219-V Ethernet Connection */
#define PCI_PRODUCT_INTEL_I219_LM4 0x15d7 /* I219-LM Ethernet Connection */
#define PCI_PRODUCT_INTEL_I219_V4 0x15d8 /* I219-V Ethernet Connection */
#define PCI_PRODUCT_INTEL_I219_LM5 0x15e3 /* I219-LM Ethernet Connection */
#define PCI_PRODUCT_INTEL_C3K_X553_SGMII 0x15e4 /* C3000 X553 1GbE SGMII (10G SKU) */
#define PCI_PRODUCT_INTEL_C3K_X553_SGMII_L 0x15e5 /* C3000 X553 1GbE SGMII (non-10G SKU) */
#define PCI_PRODUCT_INTEL_CORE5G_HB_1 0x1604 /* Core 5G Host Bridge */
#define PCI_PRODUCT_INTEL_CORE5G_M_GT1 0x1606 /* HD Graphics (GT1) */
#define PCI_PRODUCT_INTEL_CORE5G_HDA_1 0x160c /* Core 5G HD Audio */
@ -3197,6 +3210,71 @@
#define PCI_PRODUCT_INTEL_CORE6G_S_GT4_2 0x193d /* Iris Pro Graphics (GT4) */
#define PCI_PRODUCT_INTEL_80960_RP 0x1960 /* ROB-in i960RP Microprocessor */
#define PCI_PRODUCT_INTEL_80960RM_2 0x1962 /* i960 RM PCI-PCI */
#define PCI_PRODUCT_INTEL_C3K_SYSA_0 0x1980 /* C3000 System Agent */
#define PCI_PRODUCT_INTEL_C3K_GLREG 0x19a1 /* C3000 GLREG */
#define PCI_PRODUCT_INTEL_C3K_RCEC 0x19a2 /* C3000 RCEC */
#define PCI_PRODUCT_INTEL_C3K_PCIERP_QAT 0x19a3 /* C3000 PCIe Root Port for QAT */
#define PCI_PRODUCT_INTEL_C3K_PCIERP_0 0x19a4 /* C3000 PCIe Cluster 0 Port 0 */
#define PCI_PRODUCT_INTEL_C3K_PCIERP_1 0x19a5 /* C3000 PCIe Cluster 0 Port 1 */
#define PCI_PRODUCT_INTEL_C3K_PCIERP_2 0x19a6 /* C3000 PCIe Cluster 0 Port 2 */
#define PCI_PRODUCT_INTEL_C3K_PCIERP_3 0x19a7 /* C3000 PCIe Cluster 0 Port 3 */
#define PCI_PRODUCT_INTEL_C3K_PCIERP_4 0x19a8 /* C3000 PCIe Cluster 1 Port 0 */
#define PCI_PRODUCT_INTEL_C3K_PCIERP_5 0x19a9 /* C3000 PCIe Cluster 1 Port 1 */
#define PCI_PRODUCT_INTEL_C3K_PCIERP_6 0x19aa /* C3000 PCIe Cluster 1 Port 2 */
#define PCI_PRODUCT_INTEL_C3K_PCIERP_7 0x19ab /* C3000 PCIe Cluster 1 Port 3 */
#define PCI_PRODUCT_INTEL_C3K_SMBUS 0x19ac /* C3000 SMBus */
#define PCI_PRODUCT_INTEL_C3K_SATA0_0 0x19b0 /* C3000 SATA Controller 0 */
#define PCI_PRODUCT_INTEL_C3K_SATA0_1 0x19b1 /* C3000 SATA Controller 0 */
#define PCI_PRODUCT_INTEL_C3K_SATA0_2 0x19b2 /* C3000 SATA Controller 0 */
#define PCI_PRODUCT_INTEL_C3K_SATA0_3 0x19b3 /* C3000 SATA Controller 0 */
#define PCI_PRODUCT_INTEL_C3K_SATA0_4 0x19b4 /* C3000 SATA Controller 0 */
#define PCI_PRODUCT_INTEL_C3K_SATA0_5 0x19b5 /* C3000 SATA Controller 0 */
#define PCI_PRODUCT_INTEL_C3K_SATA0_6 0x19b6 /* C3000 SATA Controller 0 */
#define PCI_PRODUCT_INTEL_C3K_SATA0_7 0x19b7 /* C3000 SATA Controller 0 */
#define PCI_PRODUCT_INTEL_C3K_SATA0_8 0x19b8 /* C3000 SATA Controller 0 */
#define PCI_PRODUCT_INTEL_C3K_SATA0_9 0x19b9 /* C3000 SATA Controller 0 */
#define PCI_PRODUCT_INTEL_C3K_SATA0_10 0x19ba /* C3000 SATA Controller 0 */
#define PCI_PRODUCT_INTEL_C3K_SATA0_11 0x19bb /* C3000 SATA Controller 0 */
#define PCI_PRODUCT_INTEL_C3K_SATA0_12 0x19bc /* C3000 SATA Controller 0 */
#define PCI_PRODUCT_INTEL_C3K_SATA0_13 0x19bd /* C3000 SATA Controller 0 */
#define PCI_PRODUCT_INTEL_C3K_SATA0_14 0x19be /* C3000 SATA Controller 0 */
#define PCI_PRODUCT_INTEL_C3K_SATA0_15 0x19bf /* C3000 SATA Controller 0 */
#define PCI_PRODUCT_INTEL_C3K_SATA1_0 0x19c0 /* C3000 SATA Controller 1 */
#define PCI_PRODUCT_INTEL_C3K_SATA1_1 0x19c1 /* C3000 SATA Controller 1 */
#define PCI_PRODUCT_INTEL_C3K_SATA1_2 0x19c2 /* C3000 SATA Controller 1 */
#define PCI_PRODUCT_INTEL_C3K_SATA1_3 0x19c3 /* C3000 SATA Controller 1 */
#define PCI_PRODUCT_INTEL_C3K_SATA1_4 0x19c4 /* C3000 SATA Controller 1 */
#define PCI_PRODUCT_INTEL_C3K_SATA1_5 0x19c5 /* C3000 SATA Controller 1 */
#define PCI_PRODUCT_INTEL_C3K_SATA1_6 0x19c6 /* C3000 SATA Controller 1 */
#define PCI_PRODUCT_INTEL_C3K_SATA1_7 0x19c7 /* C3000 SATA Controller 1 */
#define PCI_PRODUCT_INTEL_C3K_SATA1_8 0x19c8 /* C3000 SATA Controller 1 */
#define PCI_PRODUCT_INTEL_C3K_SATA1_9 0x19c9 /* C3000 SATA Controller 1 */
#define PCI_PRODUCT_INTEL_C3K_SATA1_10 0x19ca /* C3000 SATA Controller 1 */
#define PCI_PRODUCT_INTEL_C3K_SATA1_11 0x19cb /* C3000 SATA Controller 1 */
#define PCI_PRODUCT_INTEL_C3K_SATA1_12 0x19cc /* C3000 SATA Controller 1 */
#define PCI_PRODUCT_INTEL_C3K_SATA1_13 0x19cd /* C3000 SATA Controller 1 */
#define PCI_PRODUCT_INTEL_C3K_SATA1_14 0x19ce /* C3000 SATA Controller 1 */
#define PCI_PRODUCT_INTEL_C3K_SATA1_15 0x19cf /* C3000 SATA Controller 1 */
#define PCI_PRODUCT_INTEL_C3K_USB23 0x19d0 /* C3000 USB 2.0/3.0 Combo */
#define PCI_PRODUCT_INTEL_C3K_PCIERP_LAN0 0x19d1 /* C3000 PCIe Root Port for LAN 0 */
#define PCI_PRODUCT_INTEL_C3K_PCIERP_LAN1 0x19d2 /* C3000 PCIe Root Port for LAN 1 */
#define PCI_PRODUCT_INTEL_C3K_ME_HECI_1 0x19d3 /* C3000 ME HECI 1 */
#define PCI_PRODUCT_INTEL_C3K_ME_EHCI_2 0x19d4 /* C3000 ME HECI 2 */
#define PCI_PRODUCT_INTEL_C3K_ME_KT 0x19d5 /* C3000 ME KT */
#define PCI_PRODUCT_INTEL_C3K_ME_HECI_3 0x19d6 /* C3000 ME HECI 3 */
#define PCI_PRODUCT_INTEL_C3K_HSUART 0x19d8 /* C3000 HS UART */
#define PCI_PRODUCT_INTEL_C3K_EMMC 0x19db /* C3000 eMMC */
#define PCI_PRODUCT_INTEL_C3K_LPC 0x19dc /* C3000 LPC */
#define PCI_PRODUCT_INTEL_C3K_P2SB 0x19dd /* C3000 P2SB */
#define PCI_PRODUCT_INTEL_C3K_PMC 0x19de /* C3000 PMC */
#define PCI_PRODUCT_INTEL_C3K_SMBUS_LEGACY 0x19df /* C3000 Legacy SMBus */
#define PCI_PRODUCT_INTEL_C3K_SPI 0x19e0 /* C3000 SPI */
#define PCI_PRODUCT_INTEL_C3K_TRACE 0x19e1 /* C3000 Trace Hub */
#define PCI_PRODUCT_INTEL_C3K_QAT 0x19e2 /* C3000 QAT */
#define PCI_PRODUCT_INTEL_C3K_IE_HECI_1 0x19e5 /* C3000 IE HECI 1 */
#define PCI_PRODUCT_INTEL_C3K_IE_HECI_2 0x19e6 /* C3000 IE HECI 2 */
#define PCI_PRODUCT_INTEL_C3K_IE_KT 0x19e8 /* C3000 IE KT */
#define PCI_PRODUCT_INTEL_C3K_IE_HECI_3 0x19e9 /* C3000 IE HECI 3 */
#define PCI_PRODUCT_INTEL_82840_HB 0x1a21 /* 82840 Host */
#define PCI_PRODUCT_INTEL_82840_AGP 0x1a23 /* 82840 AGP */
#define PCI_PRODUCT_INTEL_82840_PCI 0x1a24 /* 82840 PCI */

10748
sys/dev/pci/pcidevs_data.h
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