Remove some #ifdef ARMADAXP. We can enable simultaneously both ARMADAXP and
other SoC options.
This commit is contained in:
kiyohara
parent
1a037cc30d
commit
3e4b99ebf2
@ -1,6 +1,6 @@
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/* $NetBSD: mvsoctmr.c,v 1.9 2013/05/01 12:45:31 rkujawa Exp $ */
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/* $NetBSD: mvsoctmr.c,v 1.10 2013/10/14 04:17:59 kiyohara Exp $ */
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/*
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* Copyright (c) 2007, 2008 KIYOHARA Takashi
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* Copyright (c) 2007, 2008, 2010 KIYOHARA Takashi
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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@ -25,7 +25,7 @@
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: mvsoctmr.c,v 1.9 2013/05/01 12:45:31 rkujawa Exp $");
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__KERNEL_RCSID(0, "$NetBSD: mvsoctmr.c,v 1.10 2013/10/14 04:17:59 kiyohara Exp $");
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#include "opt_ddb.h"
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#include "opt_mvsoc.h"
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@ -49,6 +49,7 @@ __KERNEL_RCSID(0, "$NetBSD: mvsoctmr.c,v 1.9 2013/05/01 12:45:31 rkujawa Exp $")
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#include <arm/marvell/mvsocvar.h>
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#include <arm/marvell/mvsoctmrreg.h>
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#include <dev/marvell/marvellreg.h>
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#include <dev/marvell/marvellvar.h>
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#include <dev/sysmon/sysmonvar.h>
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@ -68,9 +69,10 @@ struct mvsoctmr_softc {
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bus_space_tag_t sc_iot;
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bus_space_handle_t sc_ioh;
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#if defined(ARMADAXP)
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int sc_irq;
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#endif
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#define TMR_FLAGS_ARMADAXP (1 << 0)
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int sc_flags;
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};
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@ -116,7 +118,8 @@ mvsoctmr_match(device_t parent, struct cfdata *match, void *aux)
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if (strcmp(mva->mva_name, match->cf_name) != 0)
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return 0;
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if (mva->mva_offset == MVA_OFFSET_DEFAULT)
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if (mva->mva_offset == MVA_OFFSET_DEFAULT ||
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mva->mva_irq == MVA_IRQ_DEFAULT)
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return 0;
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mva->mva_size = MVSOCTMR_SIZE;
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@ -137,15 +140,22 @@ mvsoctmr_attach(device_t parent, device_t self, void *aux)
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if (mvsoctmr_sc == NULL)
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mvsoctmr_sc = sc;
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#if defined(ARMADAXP)
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sc->sc_irq = mva->mva_irq;
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#endif
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sc->sc_dev = self;
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sc->sc_iot = mva->mva_iot;
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if (bus_space_subregion(mva->mva_iot, mva->mva_ioh,
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mva->mva_offset, mva->mva_size, &sc->sc_ioh))
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panic("%s: Cannot map registers", device_xname(self));
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sc->sc_irq = mva->mva_irq;
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switch (mva->mva_model) {
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case MARVELL_ARMADAXP_MV78130:
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case MARVELL_ARMADAXP_MV78160:
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case MARVELL_ARMADAXP_MV78230:
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case MARVELL_ARMADAXP_MV78260:
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case MARVELL_ARMADAXP_MV78460:
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sc->sc_flags = TMR_FLAGS_ARMADAXP;
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break;
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}
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mvsoctmr_timecounter.tc_name = device_xname(self);
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mvsoctmr_cntl(sc, MVSOCTMR_TIMER1, 0xffffffff, 1, 1);
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@ -186,9 +196,12 @@ clockhandler(void *arg)
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struct clockframe *frame = arg;
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#if defined(ARMADAXP)
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/* Acknowledge all timers-related interrupts */
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bus_space_write_4(mvsoctmr_sc->sc_iot, mvsoctmr_sc->sc_ioh,
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MVSOCTMR_TESR, 0x0);
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KASSERT(mvsoctmr_sc != NULL);
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if (mvsoctmr_sc->sc_flags & TMR_FLAGS_ARMADAXP)
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/* Acknowledge all timers-related interrupts */
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bus_space_write_4(mvsoctmr_sc->sc_iot, mvsoctmr_sc->sc_ioh,
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MVSOCTMR_TESR, 0x0);
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#endif
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hardclock(frame);
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@ -226,12 +239,11 @@ cpu_initclocks(void)
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mvsoctmr_timecounter.tc_priv = sc;
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#if defined(ARMADAXP)
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/* We set global timer and counter to 25 MHz mode */
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mvsoctmr_timecounter.tc_frequency = 25000000;
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#else
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mvsoctmr_timecounter.tc_frequency = mvTclk;
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#endif
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if (sc->sc_flags & TMR_FLAGS_ARMADAXP)
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/* We set global timer and counter to 25 MHz mode */
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mvsoctmr_timecounter.tc_frequency = 25000000;
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else
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mvsoctmr_timecounter.tc_frequency = mvTclk;
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timer0_tval = (mvsoctmr_timecounter.tc_frequency * 2) / (u_long) hz;
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timer0_tval = (timer0_tval / 2) + (timer0_tval & 1);
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@ -239,19 +251,19 @@ cpu_initclocks(void)
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mvsoctmr_cntl(sc, MVSOCTMR_TIMER0, timer0_tval, en, autoen);
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mvsoctmr_cntl(sc, MVSOCTMR_TIMER1, 0xffffffff, en, autoen);
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#if defined(ARMADAXP)
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/*
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* Establishing timer interrupts is slightly different for Armada XP
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* than for other supported SoCs from Marvell.
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* Timer interrupt is no different from any other interrupt in Armada
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* XP, so we use generic marvell_intr_establish().
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*/
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clock_ih = marvell_intr_establish(sc->sc_irq, IPL_CLOCK,
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clockhandler, NULL);
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#else
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clock_ih = mvsoc_bridge_intr_establish(MVSOC_MLMB_MLMBI_CPUTIMER0INTREQ,
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IPL_CLOCK, clockhandler, NULL);
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#endif
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if (sc->sc_flags & TMR_FLAGS_ARMADAXP) {
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/*
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* Establishing timer interrupts is slightly different for
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* Armada XP than for other supported SoCs from Marvell.
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* Timer interrupt is no different from any other interrupt
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* in Armada XP, so we use generic marvell_intr_establish().
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*/
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clock_ih = marvell_intr_establish(sc->sc_irq, IPL_CLOCK,
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clockhandler, NULL);
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} else
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clock_ih = mvsoc_bridge_intr_establish(
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MVSOC_MLMB_MLMBI_CPUTIMER0INTREQ, IPL_CLOCK, clockhandler,
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NULL);
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if (clock_ih == NULL)
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panic("cpu_initclocks: unable to register timer interrupt");
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@ -320,8 +332,7 @@ mvsoctmr_cntl(struct mvsoctmr_softc *sc, int num, u_int ticks, int en,
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{
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uint32_t ctrl;
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bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVSOCTMR_RELOAD(num),
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ticks);
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bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVSOCTMR_RELOAD(num), ticks);
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bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVSOCTMR_TIMER(num), ticks);
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@ -334,10 +345,9 @@ mvsoctmr_cntl(struct mvsoctmr_softc *sc, int num, u_int ticks, int en,
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ctrl |= MVSOCTMR_CTCR_CPUTIMERAUTO(num);
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else
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ctrl &= ~MVSOCTMR_CTCR_CPUTIMERAUTO(num);
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#if defined(ARMADAXP)
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/* Set timer and counter to 25MHz mode */
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ctrl |= MVSOCTMR_CTCR_25MHZEN(num);
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#endif
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if (sc->sc_flags & TMR_FLAGS_ARMADAXP)
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/* Set timer and counter to 25MHz mode */
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ctrl |= MVSOCTMR_CTCR_25MHZEN(num);
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bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVSOCTMR_CTCR, ctrl);
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}
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