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found the last piece of crack, so 

- now my sparcbook goes multiuser without LOCKDEBUG
- shaved a couple instructions
This commit is contained in:
macallan 2007-03-03 09:21:19 +00:00
parent 3fa05cb2a1
commit 3e166b9534
1 changed files with 30 additions and 30 deletions
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60
sys/arch/sparc/sparc/lock_stubs.s
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@ -1,4 +1,4 @@
/* $NetBSD: lock_stubs.s,v 1.6 2007/03/03 00:00:30 macallan Exp $ */
/* $NetBSD: lock_stubs.s,v 1.7 2007/03/03 09:21:19 macallan Exp $ */
/*-
* Copyright (c) 2002, 2007 The NetBSD Foundation, Inc.
@ -128,31 +128,30 @@ _ENTRY(_C_LABEL(mutex_exit))
* void mutex_spin_enter(kmutex_t *);
*/
_ENTRY(_C_LABEL(mutex_spin_enter))
sethi %hi(CPUINFO_VA), %g4
ld [ %g4 + CPUINFO_MTX_COUNT ], %o5
add %o5, -1, %g1
st %g1, [ %g4 + CPUINFO_MTX_COUNT ]
ldub [ %o0 + MTX_IPL ], %g2
rd %psr, %g1
sll %g2, 8, %g2
and %g1, PSR_PIL, %g3
cmp %g3, %g2
sethi %hi(CPUINFO_VA), %o4
ld [ %o4 + CPUINFO_MTX_COUNT ], %o5
sub %o5, 1, %o1
st %o1, [ %o4 + CPUINFO_MTX_COUNT ]
ldub [ %o0 + MTX_IPL ], %o2
rd %psr, %o1
sll %o2, 8, %o2
and %o1, PSR_PIL, %o3
cmp %o3, %o2
bge 1f
tst %o5
andn %g1, %g3, %g1
or %g2, %g1, %g1
mov %g1, %psr
andn %o1, PSR_PIL, %o1
wr %o2, %o1, %psr
nop
nop
nop
tst %o5
1:
bnz,a 2f
st %g3, [ %g4 + CPUINFO_MTX_OLDSPL ]
bz,a 2f
st %o3, [ %o4 + CPUINFO_MTX_OLDSPL ]
2:
#if defined(MULTIPROCESSOR) || defined(DIAGNOSTIC)
ldstub [ %o0 + MTX_LOCK ], %g2
tst %g2
ldstub [ %o0 + MTX_LOCK ], %o2
tst %o2
bnz _C_LABEL(mutex_spin_retry)
nop
#endif
@ -163,24 +162,25 @@ _ENTRY(_C_LABEL(mutex_spin_enter))
* void mutex_spin_exit(kmutex_t *);
*/
_ENTRY(_C_LABEL(mutex_spin_exit))
#if defined(DIAGNOSTIC)
ldub [ %o0 + MTX_LOCK ], %g1
cmp %g1, __SIMPLELOCK_LOCKED
bne,a _C_LABEL(mutex_vector_exit)
clrb [ %o0 + MTX_LOCK ]
ldub [ %o0 + MTX_LOCK ], %o1
tst %o1
bz _C_LABEL(mutex_vector_exit)
nop
clrb [ %o0 + MTX_LOCK ]
#elif defined(MULTIPROCESSOR)
clrb [ %o0 + MTX_LOCK ]
#endif
sethi %hi(CPUINFO_VA), %g2
ld [ %g2 + CPUINFO_MTX_OLDSPL ], %g3
ld [ %g2 + CPUINFO_MTX_COUNT ], %g1
inc %g1
tst %g1
sethi %hi(CPUINFO_VA), %o2
ld [ %o2 + CPUINFO_MTX_OLDSPL ], %o3
ld [ %o2 + CPUINFO_MTX_COUNT ], %o1
addcc %o1, 1, %o4
bnz 1f
st %g1, [ %g2 + CPUINFO_MTX_COUNT ]
rd %psr, %g1
and %g1, ~PSR_PIL, %g1
wr %g1, %g3, %psr
st %o4, [ %o2 + CPUINFO_MTX_COUNT ]
rd %psr, %o1
andn %o1, PSR_PIL, %o1
wr %o3, %o1, %psr
nop
nop
nop