timer interrupt and IPIs
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macallan
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3c99b902c7
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170
sys/arch/evbmips/ingenic/intr.c
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170
sys/arch/evbmips/ingenic/intr.c
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/* $NetBSD: intr.c,v 1.1 2014/12/06 14:26:40 macallan Exp $ */
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/*-
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* Copyright (c) 2014 Michael Lorenz
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: intr.c,v 1.1 2014/12/06 14:26:40 macallan Exp $");
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#define __INTR_PRIVATE
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#include <sys/param.h>
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#include <sys/cpu.h>
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#include <sys/device.h>
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#include <sys/kernel.h>
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#include <sys/systm.h>
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#include <sys/timetc.h>
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#include <mips/locore.h>
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#include <machine/intr.h>
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#include <mips/ingenic/ingenic_regs.h>
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extern void ingenic_clockintr(uint32_t);
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extern void ingenic_puts(const char *);
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/*
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* This is a mask of bits to clear in the SR when we go to a
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* given hardware interrupt priority level.
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*/
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static const struct ipl_sr_map ingenic_ipl_sr_map = {
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.sr_bits = {
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[IPL_NONE] = 0,
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[IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
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[IPL_SOFTNET] = MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1,
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[IPL_VM] =
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MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1 |
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MIPS_INT_MASK_0 |
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MIPS_INT_MASK_3 |
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MIPS_INT_MASK_4 |
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MIPS_INT_MASK_5,
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[IPL_SCHED] =
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MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1 |
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MIPS_INT_MASK_0 |
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MIPS_INT_MASK_1 |
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MIPS_INT_MASK_2 |
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MIPS_INT_MASK_3 |
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MIPS_INT_MASK_4 |
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MIPS_INT_MASK_5,
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[IPL_DDB] = MIPS_INT_MASK,
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[IPL_HIGH] = MIPS_INT_MASK,
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},
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};
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//#define INGENIC_DEBUG
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void
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evbmips_intr_init(void)
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{
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uint32_t reg;
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ipl_sr_map = ingenic_ipl_sr_map;
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/* mask all peripheral IRQs */
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writereg(JZ_ICMR0, 0xffffffff);
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writereg(JZ_ICMR1, 0xffffffff);
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/* allow mailbox and peripheral interrupts to core 0 only */
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reg = MFC0(12, 4); /* reset entry and interrupts */
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reg &= 0xffff0000;
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reg |= REIM_IRQ0_M | REIM_MIRQ0_M | REIM_MIRQ1_M;
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MTC0(reg, 12, 4);
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}
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void
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evbmips_iointr(int ipl, vaddr_t pc, uint32_t ipending)
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{
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uint32_t id;
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#ifdef INGENIC_DEBUG
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char buffer[256];
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snprintf(buffer, 256, "pending: %08x CR %08x\n", ipending, MFC0(MIPS_COP_0_CAUSE, 0));
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ingenic_puts(buffer);
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#endif
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/* see which core we're on */
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id = MFC0(15, 1) & 7;
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/*
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* XXX
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* the manual counts the softint bits as INT0 and INT1, out headers
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* don't so everything here looks off by two
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*/
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if (ipending & MIPS_INT_MASK_1) {
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/*
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* this is a mailbox interrupt / IPI
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* for now just print the message and clear it
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*/
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uint32_t reg;
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/* read pending IPIs */
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reg = MFC0(12, 3);
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if (id == 0) {
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if (reg & CS_MIRQ0_P) {
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#ifdef INGENIC_DEBUG
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snprintf(buffer, 256, "IPI for core 0, msg %08x\n",
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MFC0(CP0_CORE_MBOX, 0));
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ingenic_puts(buffer);
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#endif
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reg &= (~CS_MIRQ0_P);
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/* clear it */
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MTC0(reg, 12, 3);
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}
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} else if (id == 1) {
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if (reg & CS_MIRQ1_P) {
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#ifdef INGENIC_DEBUG
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snprintf(buffer, 256, "IPI for core 1, msg %08x\n",
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MFC0(CP0_CORE_MBOX, 1));
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ingenic_puts(buffer);
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#endif
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reg &= ( 7 - CS_MIRQ1_P);
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/* clear it */
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MTC0(reg, 12, 3);
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}
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}
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}
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if (ipending & MIPS_INT_MASK_2) {
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/* this is a timer interrupt */
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ingenic_clockintr(id);
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ingenic_puts("INT2\n");
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}
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if (ipending & MIPS_INT_MASK_0) {
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/* peripheral interrupt */
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/*
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* XXX
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* OS timer interrupts are supposed to show up as INT2 as well
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* but I haven't seen them there so for now we just weed them
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* out right here.
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* The idea is to allow peripheral interrupts on both cores but
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* block INT0 on core1 so it would see only timer interrupts
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* and IPIs. If that doesn't work we'll have to send an IPI to
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* core1 for each timer tick.
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*/
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if (readreg(JZ_ICPR0) & 0x08000000)
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ingenic_clockintr(id);
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KASSERT(id == 0);
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}
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}
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