Map all of core0 and core1 space and let drivers use bus_space_subregion
instead of bus_space_map. Fill in rockchip_reset.
This commit is contained in:
jmcneill
parent
fd190b9d38
commit
3d2a425be2
@ -1,4 +1,4 @@
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# $NetBSD: files.rockchip,v 1.1 2014/12/26 16:53:33 jmcneill Exp $
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# $NetBSD: files.rockchip,v 1.2 2014/12/26 19:44:48 jmcneill Exp $
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#
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# Configuration info for Rockchip ARM Peripherals
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#
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@ -11,6 +11,7 @@ file arch/arm/arm32/arm32_kvminit.c
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file arch/arm/arm32/arm32_reboot.c
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file arch/arm/arm32/irq_dispatch.S
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file arch/arm/rockchip/rockchip_board.c
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file arch/arm/rockchip/rockchip_space.c obio
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#file arch/arm/rockchip/rockchip_a4x_space.c obio
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file arch/arm/rockchip/rockchip_dma.c
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@ -25,11 +26,11 @@ file arch/arm/rockchip/obio.c obio
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attach com at obio with obiouart
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file arch/arm/rockchip/obio_com.c obiouart
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# SDHC
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#attach sdhc at obio with rksdhc
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#file arch/arm/rockchip/rockchip_sdhc.c rksdhc
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# SD/MMC (Synopsys DesignWare)
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attach dwcmmc at obio with rkdwcmmc
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file arch/arm/rockchip/rockchip_dwcmmc.c rkdwcmmc
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# USB OTG (Synopsys DesignWave OTG)
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# USB OTG (Synopsys DesignWare OTG)
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attach dwctwo at obio with rkdwctwo
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file arch/arm/rockchip/rockchip_dwctwo.c rkdwctwo needs-flag
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@ -1,4 +1,4 @@
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/* $NetBSD: obio.c,v 1.1 2014/12/26 16:53:33 jmcneill Exp $ */
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/* $NetBSD: obio.c,v 1.2 2014/12/26 19:44:48 jmcneill Exp $ */
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/*
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* Copyright (c) 2001, 2002, 2003 Wasabi Systems, Inc.
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@ -36,7 +36,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: obio.c,v 1.1 2014/12/26 16:53:33 jmcneill Exp $");
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__KERNEL_RCSID(0, "$NetBSD: obio.c,v 1.2 2014/12/26 19:44:48 jmcneill Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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@ -100,14 +100,16 @@ int
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obio_print(void *aux, const char *pnp)
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{
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struct obio_attach_args *obio = aux;
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bus_addr_t addr = obio->obio_base + obio->obio_offset;
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aprint_normal(": addr 0x%08lx", obio->obio_addr);
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aprint_normal("-0x%08lx", obio->obio_addr + (obio->obio_size - 1));
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aprint_normal(": addr 0x%08lx", addr);
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aprint_normal("-0x%08lx", addr + (obio->obio_size - 1));
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if (obio->obio_width != OBIOCF_WIDTH_DEFAULT)
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aprint_normal(" width %d", obio->obio_width);
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if (obio->obio_intr != OBIOCF_INTR_DEFAULT)
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aprint_normal(" intr %d", obio->obio_intr);
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aprint_normal(" mult %d", obio->obio_mult);
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if (obio->obio_mult != OBIOCF_MULT_DEFAULT)
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aprint_normal(" mult %d", obio->obio_mult);
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return UNCONF;
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}
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@ -116,21 +118,33 @@ int
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obio_search(device_t parent, cfdata_t cf, const int *ldesc, void *aux)
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{
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struct obio_attach_args obio;
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bus_addr_t addr = cf->cf_loc[OBIOCF_ADDR];
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obio.obio_addr = cf->cf_loc[OBIOCF_ADDR];
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if (addr >= ROCKCHIP_CORE0_BASE &&
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addr < ROCKCHIP_CORE0_BASE + ROCKCHIP_CORE0_SIZE) {
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obio.obio_base = ROCKCHIP_CORE0_BASE;
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obio.obio_bsh = rockchip_core0_bsh;
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} else if (addr >= ROCKCHIP_CORE1_BASE &&
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addr < ROCKCHIP_CORE1_BASE + ROCKCHIP_CORE1_SIZE) {
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obio.obio_base = ROCKCHIP_CORE1_BASE;
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obio.obio_bsh = rockchip_core1_bsh;
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} else {
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panic("addr %#llx is not in CORE0 or CORE1 space",
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(long long unsigned int)addr);
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}
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obio.obio_offset = addr - obio.obio_base;
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obio.obio_size = cf->cf_loc[OBIOCF_SIZE];
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obio.obio_width = cf->cf_loc[OBIOCF_WIDTH];
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obio.obio_intr = cf->cf_loc[OBIOCF_INTR];
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obio.obio_mult = cf->cf_loc[OBIOCF_MULT];
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obio.obio_dmat = &rockchip_bus_dma_tag;
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switch (cf->cf_loc[OBIOCF_MULT]) {
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case 1:
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obio.obio_iot = &rockchip_bs_tag;
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obio.obio_bst = &rockchip_bs_tag;
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break;
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case 4:
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obio.obio_iot = &rockchip_a4x_bs_tag;
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obio.obio_bst = &rockchip_a4x_bs_tag;
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break;
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default:
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panic("Unsupported EMIFS multiplier.");
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@ -160,16 +174,14 @@ void obio_iomux(int offset, int new)
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bus_space_tag_t bt = &rockchip_bs_tag;
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int old, renew;
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if (bus_space_map(bt, ROCKCHIP_GRF_BASE, ROCKCHIP_GRF_SIZE, 0, &bh))
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panic("GRF can not be mapped.");
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bus_space_subregion(bt, rockchip_core1_bsh, ROCKCHIP_GRF_OFFSET,
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ROCKCHIP_GRF_SIZE, &bh);
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old = bus_space_read_4(bt, bh, offset);
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bus_space_write_4(bt, bh, offset, (old | new | 0xffff0000));
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renew = bus_space_read_4(bt, bh, offset);
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printf("grf iomux: old %08x, new %08x, renew %08x\n", old, new, renew);
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bus_space_unmap(bt, bh, ROCKCHIP_GRF_SIZE);
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}
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#define GPIO_SWPORTA_DR_OFFSET 0x00
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@ -177,8 +189,8 @@ void obio_iomux(int offset, int new)
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void obio_init_gpio(void)
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{
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obio_swporta(ROCKCHIP_GPIO0_BASE, GPIO_SWPORTA_DR_OFFSET, __BIT(3));
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obio_swporta(ROCKCHIP_GPIO0_BASE, GPIO_SWPORTA_DD_OFFSET, __BIT(3));
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obio_swporta(ROCKCHIP_GPIO0_OFFSET, GPIO_SWPORTA_DR_OFFSET, __BIT(3));
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obio_swporta(ROCKCHIP_GPIO0_OFFSET, GPIO_SWPORTA_DD_OFFSET, __BIT(3));
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}
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void obio_swporta(int gpio_base, int offset, int new)
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@ -188,14 +200,11 @@ void obio_swporta(int gpio_base, int offset, int new)
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int old, renew;
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int gpio_size = 0x100; /* XXX */
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if (bus_space_map(bt, gpio_base, gpio_size, 0, &bh))
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panic("gpio can not be mapped.");
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bus_space_subregion(bt, rockchip_core1_bsh, gpio_base, gpio_size, &bh);
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old = bus_space_read_4(bt, bh, offset);
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bus_space_write_4(bt, bh, offset, old | new);
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renew = bus_space_read_4(bt, bh, offset);
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printf("gpio: 0x%08x 0x%08x -> 0x%08x\n", gpio_base + offset, old, renew);
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bus_space_unmap(bt, bh, gpio_size);
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}
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@ -1,4 +1,4 @@
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/* $NetBSD: obio_com.c,v 1.1 2014/12/26 16:53:33 jmcneill Exp $ */
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/* $NetBSD: obio_com.c,v 1.2 2014/12/26 19:44:48 jmcneill Exp $ */
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/* based on omap/obio_com.c */
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@ -41,7 +41,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: obio_com.c,v 1.1 2014/12/26 16:53:33 jmcneill Exp $");
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__KERNEL_RCSID(0, "$NetBSD: obio_com.c,v 1.2 2014/12/26 19:44:48 jmcneill Exp $");
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#include "opt_rockchip.h"
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/*#include "opt_com.h"*/
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@ -77,10 +77,24 @@ static int
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obiouart_match(device_t parent, cfdata_t cf, void *aux)
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{
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struct obio_attach_args *obio = aux;
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bus_space_handle_t bh;
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int rv;
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if (obio->obio_addr == OBIOCF_ADDR_DEFAULT)
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bus_space_handle_t bsh;
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bus_addr_t ioaddr;
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switch (obio->obio_base) {
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case ROCKCHIP_CORE0_BASE:
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KASSERT(obio->obio_offset == ROCKCHIP_UART0_OFFSET ||
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obio->obio_offset == ROCKCHIP_UART1_OFFSET);
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break;
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case ROCKCHIP_CORE1_BASE:
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KASSERT(obio->obio_offset == ROCKCHIP_UART2_OFFSET ||
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obio->obio_offset == ROCKCHIP_UART3_OFFSET);
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break;
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default:
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panic("obiouart must have addr specified in config.");
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}
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ioaddr = obio->obio_base + obio->obio_offset;
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#if 0
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/*
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* XXX this should be ifdefed on a board-dependent switch
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@ -93,18 +107,13 @@ obiouart_match(device_t parent, cfdata_t cf, void *aux)
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if (obio->obio_size == OBIOCF_SIZE_DEFAULT)
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obio->obio_size = ROCKCHIP_UART_SIZE;
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if (com_is_console(obio->obio_iot, obio->obio_addr, NULL))
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if (com_is_console(obio->obio_bst, ioaddr, NULL))
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return 1;
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if (bus_space_map(obio->obio_iot, obio->obio_addr, obio->obio_size,
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0, &bh))
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return 1;
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bus_space_subregion(obio->obio_bst, obio->obio_bsh, obio->obio_size, 0,
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&bsh);
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rv = comprobe1(obio->obio_iot, bh);
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bus_space_unmap(obio->obio_iot, bh, obio->obio_size);
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return rv;
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return comprobe1(obio->obio_bst, bsh);
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}
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static void
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@ -113,24 +122,23 @@ obiouart_attach(device_t parent, device_t self, void *aux)
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struct com_obio_softc *osc = device_private(self);
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struct com_softc *sc = &osc->sc_sc;
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struct obio_attach_args *obio = aux;
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bus_space_tag_t iot;
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bus_space_handle_t ioh = 0;
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bus_space_tag_t bst;
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bus_space_handle_t bsh = 0;
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bus_addr_t iobase;
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sc->sc_dev = self;
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iot = obio->obio_iot;
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iobase = obio->obio_addr;
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bst = obio->obio_bst;
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iobase = obio->obio_base + obio->obio_offset;
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sc->sc_frequency = ROCKCHIP_UART_FREQ;
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sc->sc_type = COM_TYPE_NORMAL;
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if (com_is_console(iot, iobase, &ioh) == 0 &&
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bus_space_map(iot, iobase, obio->obio_size, 0, &ioh)) {
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if (com_is_console(bst, iobase, &bsh) == 0 &&
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bus_space_subregion(bst, obio->obio_bsh, obio->obio_size, 0, &bsh)) {
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panic(": can't map registers\n");
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return;
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}
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COM_INIT_REGS(sc->sc_regs, iot, ioh, iobase);
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COM_INIT_REGS(sc->sc_regs, bst, bsh, iobase);
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com_attach_subr(sc);
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aprint_naive("\n");
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57
sys/arch/arm/rockchip/rockchip_board.c
Normal file
57
sys/arch/arm/rockchip/rockchip_board.c
Normal file
@ -0,0 +1,57 @@
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/* $NetBSD: rockchip_board.c,v 1.1 2014/12/26 19:44:48 jmcneill Exp $ */
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/*-
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* Copyright (c) 2014 Jared D. McNeill <jmcneill@invisible.ca>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: rockchip_board.c,v 1.1 2014/12/26 19:44:48 jmcneill Exp $");
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/cpu.h>
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#include <sys/device.h>
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#include <arm/rockchip/rockchip_reg.h>
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#include <arm/rockchip/rockchip_var.h>
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bus_space_handle_t rockchip_core0_bsh;
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bus_space_handle_t rockchip_core1_bsh;
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void
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rockchip_bootstrap(void)
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{
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int error;
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error = bus_space_map(&rockchip_bs_tag, ROCKCHIP_CORE0_BASE,
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ROCKCHIP_CORE0_SIZE, 0, &rockchip_core0_bsh);
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if (error)
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panic("%s: failed to map CORE0 registers: %d", __func__, error);
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error = bus_space_map(&rockchip_bs_tag, ROCKCHIP_CORE1_BASE,
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ROCKCHIP_CORE1_SIZE, 0, &rockchip_core1_bsh);
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if (error)
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panic("%s: failed to map CORE1 registers: %d", __func__, error);
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}
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@ -1,4 +1,4 @@
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/* $NetBSD: rockchip_dwctwo.c,v 1.1 2014/12/26 16:53:33 jmcneill Exp $ */
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/* $NetBSD: rockchip_dwctwo.c,v 1.2 2014/12/26 19:44:48 jmcneill Exp $ */
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/*-
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* Copyright (c) 2013 The NetBSD Foundation, Inc.
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@ -30,7 +30,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: rockchip_dwctwo.c,v 1.1 2014/12/26 16:53:33 jmcneill Exp $");
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__KERNEL_RCSID(0, "$NetBSD: rockchip_dwctwo.c,v 1.2 2014/12/26 19:44:48 jmcneill Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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@ -112,21 +112,15 @@ rkdwc2_attach(device_t parent, device_t self, void *aux)
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{
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struct rkdwc2_softc *sc = device_private(self);
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struct obio_attach_args *obio = aux;
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int error;
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sc->sc_dwc2.sc_dev = self;
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sc->sc_dwc2.sc_iot = obio->obio_iot;
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sc->sc_dwc2.sc_iot = obio->obio_bst;
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sc->sc_dwc2.sc_bus.dmatag = obio->obio_dmat;
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sc->sc_dwc2.sc_params = &rkdwc2_params;
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error = bus_space_map(obio->obio_iot, obio->obio_addr, obio->obio_size, 0,
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&sc->sc_dwc2.sc_ioh);
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if (error) {
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aprint_error_dev(self,
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"can't map registers for %s: %d\n", obio->obio_name, error);
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return;
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}
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bus_space_subregion(obio->obio_bst, obio->obio_bsh, obio->obio_offset,
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obio->obio_size, &sc->sc_dwc2.sc_ioh);
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aprint_naive(": USB controller\n");
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aprint_normal(": USB controller\n");
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@ -151,7 +145,6 @@ fail:
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intr_disestablish(sc->sc_ih);
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sc->sc_ih = NULL;
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}
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bus_space_unmap(sc->sc_dwc2.sc_iot, sc->sc_dwc2.sc_ioh, obio->obio_size);
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}
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static void
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@ -1,4 +1,4 @@
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/* $NetBSD: rockchip_reg.h,v 1.1 2014/12/26 16:53:33 jmcneill Exp $ */
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/* $NetBSD: rockchip_reg.h,v 1.2 2014/12/26 19:44:48 jmcneill Exp $ */
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/*-
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* Copyright (c) 2014 The NetBSD Foundation, Inc.
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@ -42,43 +42,46 @@
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#define ROCKCHIP_CORE0_VBASE 0xFEA00000
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#define ROCKCHIP_CORE0_SIZE 0x00300000
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#define ROCKCHIP_OTG_BASE 0x10180000
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/* CORE0 */
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#define ROCKCHIP_OTG_OFFSET 0x00180000
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#define ROCKCHIP_OTG_SIZE 0x40000
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#define ROCKCHIP_USB_BASE 0x101C0000
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#define ROCKCHIP_USB_OFFSET 0x001C0000
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#define ROCKCHIP_USB_SIZE 0x40000
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#define ROCKCHIP_UART0_BASE 0x10124000
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#define ROCKCHIP_UART0_OFFSET 0x00124000
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#define ROCKCHIP_UART0_SIZE 0x400
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#define ROCKCHIP_UART1_BASE 0x10126000
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#define ROCKCHIP_UART1_OFFSET 0x00126000
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#define ROCKCHIP_UART1_SIZE 0x400
|
||||
#define ROCKCHIP_PL310_BASE 0x10138000
|
||||
#define ROCKCHIP_PL310_OFFSET 0x00138000
|
||||
#define ROCKCHIP_PL310_SIZE 0x1000
|
||||
#define ROCKCHIP_GICC_BASE 0x1013C100
|
||||
#define ROCKCHIP_GICC_OFFSET 0x0013C100
|
||||
#define ROCKCHIP_GICC_SIZE 0x100
|
||||
#define ROCKCHIP_A9TMR_BASE 0x1013C200
|
||||
#define ROCKCHIP_A9TMR_OFFSET 0x0013C200
|
||||
#define ROCKCHIP_A9TMR_SIZE 0x100
|
||||
#define ROCKCHIP_A9WDT_BASE 0x1013C600
|
||||
#define ROCKCHIP_A9WDT_OFFSET 0x0013C600
|
||||
#define ROCKCHIP_A9WDT_SIZE 0x20
|
||||
#define ROCKCHIP_GICD_BASE 0x1013D000
|
||||
#define ROCKCHIP_GICD_OFFSET 0x0013D000
|
||||
#define ROCKCHIP_GICD_SIZE 0x1000
|
||||
|
||||
#define ROCKCHIP_CORE1_BASE 0x20000000
|
||||
#define ROCKCHIP_CORE1_VBASE 0xFED00000
|
||||
#define ROCKCHIP_CORE1_SIZE 0x00100000
|
||||
|
||||
#define ROCKCHIP_GRF_BASE 0x20008000
|
||||
/* CORE1 */
|
||||
#define ROCKCHIP_CRU_OFFSET 0x00000000
|
||||
#define ROCKCHIP_CRU_SIZE 0x4000
|
||||
#define ROCKCHIP_GRF_OFFSET 0x00008000
|
||||
#define ROCKCHIP_GRF_SIZE 0x2000
|
||||
|
||||
#define ROCKCHIP_UART2_BASE 0x20064000
|
||||
#define ROCKCHIP_UART2_OFFSET 0x00064000
|
||||
#define ROCKCHIP_UART2_SIZE 0x400
|
||||
#define ROCKCHIP_UART3_BASE 0x20068000
|
||||
#define ROCKCHIP_UART3_OFFSET 0x00068000
|
||||
#define ROCKCHIP_UART3_SIZE 0x400
|
||||
#define ROCKCHIP_GPIO0_BASE 0x2000A000
|
||||
#define ROCKCHIP_GPIO0_OFFSET 0x0000A000
|
||||
#define ROCKCHIP_GPIO0_SIZE 0x100
|
||||
#define ROCKCHIP_GPIO1_BASE 0x2003C000
|
||||
#define ROCKCHIP_GPIO1_OFFSET 0x0003C000
|
||||
#define ROCKCHIP_GPIO1_SIZE 0x100
|
||||
#define ROCKCHIP_GPIO2_BASE 0x2003E000
|
||||
#define ROCKCHIP_GPIO2_OFFSET 0x0003E000
|
||||
#define ROCKCHIP_GPIO2_SIZE 0x100
|
||||
#define ROCKCHIP_GPIO3_BASE 0x20080000
|
||||
#define ROCKCHIP_GPIO3_OFFSET 0x00080000
|
||||
#define ROCKCHIP_GPIO3_SIZE 0x100
|
||||
|
||||
#endif /* _ARM_ROCKCHIP_ROCKCHIP_REG_H_ */
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: rockchip_var.h,v 1.1 2014/12/26 16:53:33 jmcneill Exp $ */
|
||||
/* $NetBSD: rockchip_var.h,v 1.2 2014/12/26 19:44:48 jmcneill Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 2014 The NetBSD Foundation, Inc.
|
||||
@ -36,8 +36,10 @@
|
||||
#include <sys/bus.h>
|
||||
|
||||
struct obio_attach_args {
|
||||
bus_space_tag_t obio_iot; /* bus space tag */
|
||||
bus_addr_t obio_addr; /* address of device */
|
||||
bus_space_tag_t obio_bst; /* bus space tag */
|
||||
bus_space_handle_t obio_bsh; /* bus space handle */
|
||||
bus_addr_t obio_base; /* base address of handle */
|
||||
bus_addr_t obio_offset; /* address of device */
|
||||
bus_size_t obio_size; /* size of device */
|
||||
int obio_intr; /* irq */
|
||||
int obio_width; /* bus width */
|
||||
@ -49,5 +51,9 @@ struct obio_attach_args {
|
||||
extern struct bus_space rockchip_bs_tag;
|
||||
extern struct bus_space rockchip_a4x_bs_tag;
|
||||
extern struct arm32_bus_dma_tag rockchip_bus_dma_tag;
|
||||
extern bus_space_handle_t rockchip_core0_bsh;
|
||||
extern bus_space_handle_t rockchip_core1_bsh;
|
||||
|
||||
void rockchip_bootstrap(void);
|
||||
|
||||
#endif /* _ARM_ROCKCHIP_ROCKCHIP_VAR_H_ */
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: rockchip_machdep.c,v 1.1 2014/12/26 16:53:33 jmcneill Exp $ */
|
||||
/* $NetBSD: rockchip_machdep.c,v 1.2 2014/12/26 19:44:48 jmcneill Exp $ */
|
||||
|
||||
/*
|
||||
* Machine dependent functions for kernel setup for TI OSK5912 board.
|
||||
@ -125,7 +125,7 @@
|
||||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__KERNEL_RCSID(0, "$NetBSD: rockchip_machdep.c,v 1.1 2014/12/26 16:53:33 jmcneill Exp $");
|
||||
__KERNEL_RCSID(0, "$NetBSD: rockchip_machdep.c,v 1.2 2014/12/26 19:44:48 jmcneill Exp $");
|
||||
|
||||
#include "opt_machdep.h"
|
||||
#include "opt_ddb.h"
|
||||
@ -181,6 +181,7 @@ __KERNEL_RCSID(0, "$NetBSD: rockchip_machdep.c,v 1.1 2014/12/26 16:53:33 jmcneil
|
||||
#include <dev/ic/ns16550reg.h>
|
||||
#include <dev/ic/comreg.h>
|
||||
|
||||
#include <arm/rockchip/rockchip_reg.h>
|
||||
#include <arm/rockchip/rockchip_var.h>
|
||||
|
||||
#ifdef CPU_CORTEXA9
|
||||
@ -340,6 +341,9 @@ initarm(void *arg)
|
||||
rockchip_putchar('d');
|
||||
#endif
|
||||
|
||||
pmap_devmap_register(devmap);
|
||||
rockchip_bootstrap();
|
||||
|
||||
/* Heads up ... Setup the CPU / MMU / TLB functions. */
|
||||
if (set_cpufuncs())
|
||||
panic("cpu not recognized!");
|
||||
@ -348,8 +352,6 @@ curcpu()->ci_data.cpu_cc_freq = 1600000000; /* XXX hack XXX */
|
||||
|
||||
init_clocks();
|
||||
|
||||
/* The console is going to try to map things. Give pmap a devmap. */
|
||||
pmap_devmap_register(devmap);
|
||||
consinit();
|
||||
#ifdef CPU_CORTEXA15
|
||||
#ifdef MULTIPROCESSOR
|
||||
@ -362,8 +364,8 @@ curcpu()->ci_data.cpu_cc_freq = 1600000000; /* XXX hack XXX */
|
||||
* Probe the PL310 L2CC
|
||||
*/
|
||||
printf("probe the PL310 L2CC\n");
|
||||
const bus_space_handle_t pl310_bh = ROCKCHIP_PL310_BASE
|
||||
+ ROCKCHIP_CORE0_VBASE - ROCKCHIP_CORE0_BASE;
|
||||
const bus_space_handle_t pl310_bh =
|
||||
ROCKCHIP_CORE0_VBASE + ROCKCHIP_PL310_OFFSET;
|
||||
arml2cc_init(&rockchip_a4x_bs_tag, pl310_bh, 0);
|
||||
rockchip_putchar('l');
|
||||
#endif
|
||||
@ -520,7 +522,13 @@ consinit(void)
|
||||
void
|
||||
rockchip_reset(void)
|
||||
{
|
||||
/* NOT YET */
|
||||
bus_space_tag_t bst = &rockchip_bs_tag;
|
||||
bus_space_handle_t bsh;
|
||||
|
||||
bus_space_subregion(bst, rockchip_core1_bsh,
|
||||
ROCKCHIP_CRU_OFFSET, ROCKCHIP_CRU_SIZE, &bsh);
|
||||
|
||||
bus_space_write_4(bst, bsh, 0x100, 0xfdb9);
|
||||
}
|
||||
|
||||
#ifdef KGDB
|
||||
|
||||
Loading…
Reference in New Issue
Block a user