Make these compatible with thumb/thumb2
This commit is contained in:
matt
parent
9eea19add8
commit
3d199353e0
@ -1,4 +1,4 @@
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/* $NetBSD: bus_space_a2x.S,v 1.3 2013/08/18 06:28:18 matt Exp $ */
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/* $NetBSD: bus_space_a2x.S,v 1.4 2013/10/28 22:50:25 matt Exp $ */
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/*-
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* Copyright (c) 2012 The NetBSD Foundation, Inc.
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@ -33,7 +33,7 @@
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#include <arm/locore.h>
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#include <arm/byte_swap.h>
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RCSID("$NetBSD: bus_space_a2x.S,v 1.3 2013/08/18 06:28:18 matt Exp $")
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RCSID("$NetBSD: bus_space_a2x.S,v 1.4 2013/10/28 22:50:25 matt Exp $")
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/*
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* bus_space_read_[124](void *cookie, bus_space_handle_t handle,
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@ -47,13 +47,13 @@ END(a2x_bs_r_1)
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#if (ARM_ARCH_4 + ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7) > 0
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ENTRY_NP(a2x_bs_r_2)
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lsl r2, r2, #1
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lsls r2, r2, #1
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ldrh r0, [r1, r2]
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RET
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END(a2x_bs_r_2)
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ENTRY_NP(a2x_bs_r_2_swap)
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lsl r2, r2, #1
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lsls r2, r2, #1
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ldrh r0, [r1, r2]
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BSWAP16(r0, r0, r1)
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RET
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@ -77,29 +77,29 @@ END(a2x_bs_r_4_swap)
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*/
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ENTRY_NP(a2x_bs_rm_1)
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lsl r2, r2, #1
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lsls r2, r2, #1
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b generic_bs_rm_1
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END(a2x_bs_rm_1)
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#if (ARM_ARCH_4 + ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7) > 0
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ENTRY_NP(a2x_bs_rm_2)
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lsl r2, r2, #1
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lsls r2, r2, #1
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b generic_armv4_bs_rm_2
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END(a2x_bs_rm_2)
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ENTRY_NP(a2x_bs_rm_2_swap)
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lsl r2, r2, #1
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lsls r2, r2, #1
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b generic_armv4_bs_rm_2_swap
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END(a2x_bs_rm_2_swap)
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#endif
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ENTRY_NP(a2x_bs_rm_4)
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lsl r2, r2, #1
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lsls r2, r2, #1
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b generic_bs_rm_4
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END(a2x_bs_rm_4)
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ENTRY_NP(a2x_bs_rm_4_swap)
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lsl r2, r2, #1
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lsls r2, r2, #1
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b generic_bs_rm_4_swap
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END(a2x_bs_rm_4_swap)
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@ -116,7 +116,7 @@ END(a2x_bs_w_1)
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ENTRY_NP(a2x_bs_w_2_swap)
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BSWAP16(r3, r3, r0)
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ENTRY_NP(a2x_bs_w_2)
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lsl r2, r2, #1
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lsls r2, r2, #1
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strh r3, [r1, r2]
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RET
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END(a2x_bs_w_2)
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@ -137,28 +137,28 @@ END(a2x_bs_w_4_swap)
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*/
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ENTRY_NP(a2x_bs_wm_1)
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lsl r2, r2, #1
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lsls r2, r2, #1
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b generic_bs_wm_1
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END(a2x_bs_wm_1)
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#if (ARM_ARCH_4 + ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7) > 0
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ENTRY_NP(a2x_bs_wm_2)
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lsl r2, r2, #1
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lsls r2, r2, #1
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b generic_armv4_bs_wm_2
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END(a2x_bs_wm_2)
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ENTRY_NP(a2x_bs_wm_2_swap)
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lsl r2, r2, #1
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lsls r2, r2, #1
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b generic_armv4_bs_wm_2_swap
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END(a2x_bs_wm_2_swap)
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#endif
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ENTRY_NP(a2x_bs_wm_4)
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lsl r2, r2, #1
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lsls r2, r2, #1
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b generic_bs_wm_4
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END(a2x_bs_wm_4)
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ENTRY_NP(a2x_bs_wm_4_swap)
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lsl r2, r2, #1
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lsls r2, r2, #1
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b generic_bs_wm_4_swap
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END(a2x_bs_wm_4_swap)
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@ -1,4 +1,4 @@
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/* $NetBSD: bus_space_a4x.S,v 1.3 2013/08/18 06:28:18 matt Exp $ */
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/* $NetBSD: bus_space_a4x.S,v 1.4 2013/10/28 22:50:25 matt Exp $ */
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/*-
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* Copyright (c) 2012 The NetBSD Foundation, Inc.
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@ -33,7 +33,7 @@
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#include <arm/locore.h>
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#include <arm/byte_swap.h>
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RCSID("$NetBSD: bus_space_a4x.S,v 1.3 2013/08/18 06:28:18 matt Exp $")
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RCSID("$NetBSD: bus_space_a4x.S,v 1.4 2013/10/28 22:50:25 matt Exp $")
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/*
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* bus_space_read_[124](void *cookie, bus_space_handle_t handle,
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@ -47,13 +47,13 @@ END(a4x_bs_r_1)
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#if (ARM_ARCH_4 + ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7) > 0
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ENTRY_NP(a4x_bs_r_2)
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lsl r2, r2, #2
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lsls r2, r2, #2
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ldrh r0, [r1, r2]
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RET
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END(a4x_bs_r_2)
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ENTRY_NP(a4x_bs_r_2_swap)
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lsl r2, r2, #2
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lsls r2, r2, #2
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ldrh r0, [r1, r2]
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BSWAP16(r0, r0, r1)
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RET
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@ -77,29 +77,29 @@ END(a4x_bs_r_4_swap)
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*/
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ENTRY_NP(a4x_bs_rm_1)
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lsl r2, r2, #2
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lsls r2, r2, #2
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b generic_bs_rm_1
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END(a4x_bs_rm_1)
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#if (ARM_ARCH_4 + ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7) > 0
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ENTRY_NP(a4x_bs_rm_2)
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lsl r2, r2, #2
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lsls r2, r2, #2
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b generic_armv4_bs_rm_2
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END(a4x_bs_rm_2)
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ENTRY_NP(a4x_bs_rm_2_swap)
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lsl r2, r2, #2
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lsls r2, r2, #2
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b generic_armv4_bs_rm_2_swap
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END(a4x_bs_rm_2_swap)
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#endif
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ENTRY_NP(a4x_bs_rm_4)
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lsl r2, r2, #2
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lsls r2, r2, #2
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b generic_bs_rm_4
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END(a4x_bs_rm_4)
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ENTRY_NP(a4x_bs_rm_4_swap)
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lsl r2, r2, #2
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lsls r2, r2, #2
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b generic_bs_rm_4_swap
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END(a4x_bs_rm_4_swap)
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@ -116,7 +116,7 @@ END(a4x_bs_w_1)
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ENTRY_NP(a4x_bs_w_2_swap)
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BSWAP16(r3, r3, r0)
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ENTRY_NP(a4x_bs_w_2)
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lsl r2, r2, #2
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lsls r2, r2, #2
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strh r3, [r1, r2]
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RET
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END(a4x_bs_w_2)
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@ -137,28 +137,28 @@ END(a4x_bs_w_4_swap)
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*/
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ENTRY_NP(a4x_bs_wm_1)
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lsl r2, r2, #2
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lsls r2, r2, #2
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b generic_bs_wm_1
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END(a4x_bs_wm_1)
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#if (ARM_ARCH_4 + ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7) > 0
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ENTRY_NP(a4x_bs_wm_2)
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lsl r2, r2, #2
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lsls r2, r2, #2
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b generic_armv4_bs_wm_2
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END(a4x_bs_wm_2)
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ENTRY_NP(a4x_bs_wm_2_swap)
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lsl r2, r2, #2
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lsls r2, r2, #2
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b generic_armv4_bs_wm_2_swap
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END(a4x_bs_wm_2_swap)
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#endif
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ENTRY_NP(a4x_bs_wm_4)
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lsl r2, r2, #2
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lsls r2, r2, #2
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b generic_bs_wm_4
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END(a4x_bs_wm_4)
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ENTRY_NP(a4x_bs_wm_4_swap)
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lsl r2, r2, #2
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lsls r2, r2, #2
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b generic_bs_wm_4_swap
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END(a4x_bs_wm_4_swap)
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@ -1,4 +1,4 @@
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/* $NetBSD: bus_space_asm_generic.S,v 1.10 2013/08/18 06:29:29 matt Exp $ */
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/* $NetBSD: bus_space_asm_generic.S,v 1.11 2013/10/28 22:50:25 matt Exp $ */
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/*
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* Copyright (c) 1997 Causality Limited.
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@ -46,6 +46,13 @@
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#define DSB
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#endif
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#if defined(__thumb__) && defined(_ARM_ARCH_T2)
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#define CHECK_LENGTH(r, l) cbz r, l
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#elif defined(__thumb__)
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#define CHECK_LENGTH(r, l) cmp r, #0; beq l
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#else
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#define CHECK_LENGTH(r, l) cmp r, #0; RETc(eq)
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#endif
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/*
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* Generic bus_space functions.
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*/
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@ -123,11 +130,10 @@ END(generic_bs_w_4_swap)
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*/
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ENTRY_NP(generic_bs_rm_1)
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add r0, r1, r2
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adds r0, r1, r2
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mov r1, r3
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ldr r2, [sp, #0]
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teq r2, #0
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RETc(eq)
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CHECK_LENGTH(r2, 99f)
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DSB
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1: ldrb r3, [r0]
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@ -135,16 +141,15 @@ ENTRY_NP(generic_bs_rm_1)
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subs r2, r2, #1
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bne 1b
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RET
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99: RET
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END(generic_bs_rm_1)
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#if (ARM_ARCH_4 + ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7) > 0
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ENTRY_NP(generic_armv4_bs_rm_2)
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add r0, r1, r2
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adds r0, r1, r2
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mov r1, r3
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ldr r2, [sp, #0]
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teq r2, #0
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RETc(eq)
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CHECK_LENGTH(r2, 99f)
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DSB
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1: ldrh r3, [r0]
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@ -152,16 +157,15 @@ ENTRY_NP(generic_armv4_bs_rm_2)
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subs r2, r2, #1
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bne 1b
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RET
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99: RET
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END(generic_armv4_bs_rm_2)
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ENTRY_NP(generic_armv4_bs_rm_2_swap)
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DSB
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add r0, r1, r2
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adds r0, r1, r2
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mov r1, r3
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ldr r2, [sp, #0]
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teq r2, #0
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RETc(eq)
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CHECK_LENGTH(r2, 99f)
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DSB
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1: ldrh r3, [r0]
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@ -170,16 +174,15 @@ ENTRY_NP(generic_armv4_bs_rm_2_swap)
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subs r2, r2, #1
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bne 1b
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RET
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99: RET
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END(generic_armv4_bs_rm_2_swap)
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#endif
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ENTRY_NP(generic_bs_rm_4)
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add r0, r1, r2
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adds r0, r1, r2
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mov r1, r3
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ldr r2, [sp, #0]
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teq r2, #0
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RETc(eq)
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CHECK_LENGTH(r2, 99f)
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DSB
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1: ldr r3, [r0]
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@ -187,15 +190,14 @@ ENTRY_NP(generic_bs_rm_4)
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subs r2, r2, #1
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bne 1b
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RET
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99: RET
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END(generic_bs_rm_4)
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ENTRY_NP(generic_bs_rm_4_swap)
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add r0, r1, r2
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adds r0, r1, r2
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mov r1, r3
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ldr r2, [sp, #0]
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teq r2, #0
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RETc(eq)
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CHECK_LENGTH(r2, 99f)
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DSB
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1: ldr r3, [r0]
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@ -204,7 +206,7 @@ ENTRY_NP(generic_bs_rm_4_swap)
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subs r2, r2, #1
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bne 1b
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RET
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99: RET
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END(generic_bs_rm_4_swap)
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/*
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@ -212,11 +214,10 @@ END(generic_bs_rm_4_swap)
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*/
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ENTRY_NP(generic_bs_wm_1)
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add r0, r1, r2
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adds r0, r1, r2
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mov r1, r3
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ldr r2, [sp, #0]
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teq r2, #0
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RETc(eq)
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CHECK_LENGTH(r2, 99f)
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1: ldrb r3, [r1], #1
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strb r3, [r0]
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@ -224,16 +225,15 @@ ENTRY_NP(generic_bs_wm_1)
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bne 1b
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DSB
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RET
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99: RET
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END(generic_bs_wm_1)
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#if (ARM_ARCH_4 + ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7) > 0
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ENTRY_NP(generic_armv4_bs_wm_2)
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add r0, r1, r2
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adds r0, r1, r2
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mov r1, r3
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ldr r2, [sp, #0]
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teq r2, #0
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RETc(eq)
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CHECK_LENGTH(r2, 99f)
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1: ldrh r3, [r1], #2
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strh r3, [r0]
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@ -241,15 +241,13 @@ ENTRY_NP(generic_armv4_bs_wm_2)
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bne 1b
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DSB
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RET
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99: RET
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END(generic_armv4_bs_wm_2)
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ENTRY_NP(generic_armv4_bs_wm_2_swap)
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add r0, r1, r2
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adds r0, r1, r2
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mov r1, r3
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ldr r2, [sp, #0]
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teq r2, #0
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RETc(eq)
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1: ldrh r3, [r1], #2
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BSWAP16(r3, r3, ip)
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@ -258,16 +256,15 @@ ENTRY_NP(generic_armv4_bs_wm_2_swap)
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bne 1b
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DSB
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RET
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99: RET
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END(generic_armv4_bs_wm_2_swap)
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#endif
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ENTRY_NP(generic_bs_wm_4)
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add r0, r1, r2
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adds r0, r1, r2
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mov r1, r3
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ldr r2, [sp, #0]
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teq r2, #0
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RETc(eq)
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CHECK_LENGTH(r2, 99f)
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1: ldr r3, [r1], #4
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str r3, [r0]
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@ -275,15 +272,14 @@ ENTRY_NP(generic_bs_wm_4)
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bne 1b
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DSB
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RET
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99: RET
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END(generic_bs_wm_4)
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ENTRY_NP(generic_bs_wm_4_swap)
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add r0, r1, r2
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adds r0, r1, r2
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mov r1, r3
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ldr r2, [sp, #0]
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teq r2, #0
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RETc(eq)
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CHECK_LENGTH(r2, 99f)
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1: ldr r3, [r1], #4
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BSWAP32(r3, r3, ip)
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@ -292,7 +288,7 @@ ENTRY_NP(generic_bs_wm_4_swap)
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bne 1b
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DSB
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RET
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99: RET
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END(generic_bs_wm_4_swap)
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/*
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@ -300,11 +296,10 @@ END(generic_bs_wm_4_swap)
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*/
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ENTRY_NP(generic_bs_rr_1)
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add r0, r1, r2
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adds r0, r1, r2
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mov r1, r3
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ldr r2, [sp, #0]
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teq r2, #0
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||||
RETc(eq)
|
||||
CHECK_LENGTH(r2, 99f)
|
||||
DSB
|
||||
|
||||
1: ldrb r3, [r0], #1
|
||||
@ -312,16 +307,15 @@ ENTRY_NP(generic_bs_rr_1)
|
||||
subs r2, r2, #1
|
||||
bne 1b
|
||||
|
||||
RET
|
||||
99: RET
|
||||
END(generic_bs_rr_1)
|
||||
|
||||
#if (ARM_ARCH_4 + ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7) > 0
|
||||
ENTRY_NP(generic_armv4_bs_rr_2)
|
||||
add r0, r1, r2
|
||||
adds r0, r1, r2
|
||||
mov r1, r3
|
||||
ldr r2, [sp, #0]
|
||||
teq r2, #0
|
||||
RETc(eq)
|
||||
CHECK_LENGTH(r2, 99f)
|
||||
DSB
|
||||
|
||||
1: ldrh r3, [r0], #2
|
||||
@ -329,15 +323,14 @@ ENTRY_NP(generic_armv4_bs_rr_2)
|
||||
subs r2, r2, #1
|
||||
bne 1b
|
||||
|
||||
RET
|
||||
99: RET
|
||||
END(generic_armv4_bs_rr_2)
|
||||
|
||||
ENTRY_NP(generic_armv4_bs_rr_2_swap)
|
||||
add r0, r1, r2
|
||||
adds r0, r1, r2
|
||||
mov r1, r3
|
||||
ldr r2, [sp, #0]
|
||||
teq r2, #0
|
||||
RETc(eq)
|
||||
CHECK_LENGTH(r2, 99f)
|
||||
DSB
|
||||
|
||||
1: ldrh r3, [r0], #2
|
||||
@ -346,31 +339,29 @@ ENTRY_NP(generic_armv4_bs_rr_2_swap)
|
||||
subs r2, r2, #1
|
||||
bne 1b
|
||||
|
||||
RET
|
||||
99: RET
|
||||
END(generic_armv4_bs_rr_2_swap)
|
||||
#endif
|
||||
|
||||
ENTRY_NP(generic_bs_rr_4)
|
||||
add r0, r1, r2
|
||||
adds r0, r1, r2
|
||||
mov r1, r3
|
||||
ldr r2, [sp, #0]
|
||||
teq r2, #0
|
||||
RETc(eq)
|
||||
CHECK_LENGTH(r2, 99f)
|
||||
|
||||
1: ldr r3, [r0], #4
|
||||
str r3, [r1], #4
|
||||
subs r2, r2, #1
|
||||
bne 1b
|
||||
|
||||
RET
|
||||
99: RET
|
||||
END(generic_bs_rr_4)
|
||||
|
||||
ENTRY_NP(generic_bs_rr_4_swap)
|
||||
add r0, r1, r2
|
||||
adds r0, r1, r2
|
||||
mov r1, r3
|
||||
ldr r2, [sp, #0]
|
||||
teq r2, #0
|
||||
RETc(eq)
|
||||
CHECK_LENGTH(r2, 99f)
|
||||
DSB
|
||||
|
||||
1: ldr r3, [r0], #4
|
||||
@ -379,7 +370,7 @@ ENTRY_NP(generic_bs_rr_4_swap)
|
||||
subs r2, r2, #1
|
||||
bne 1b
|
||||
|
||||
RET
|
||||
99: RET
|
||||
END(generic_bs_rr_4_swap)
|
||||
|
||||
/*
|
||||
@ -387,11 +378,10 @@ END(generic_bs_rr_4_swap)
|
||||
*/
|
||||
|
||||
ENTRY_NP(generic_bs_wr_1)
|
||||
add r0, r1, r2
|
||||
adds r0, r1, r2
|
||||
mov r1, r3
|
||||
ldr r2, [sp, #0]
|
||||
teq r2, #0
|
||||
RETc(eq)
|
||||
CHECK_LENGTH(r2, 99f)
|
||||
|
||||
1: ldrb r3, [r1], #1
|
||||
strb r3, [r0], #1
|
||||
@ -399,16 +389,15 @@ ENTRY_NP(generic_bs_wr_1)
|
||||
bne 1b
|
||||
|
||||
DSB
|
||||
RET
|
||||
99: RET
|
||||
END(generic_bs_wr_1)
|
||||
|
||||
#if (ARM_ARCH_4 + ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7) > 0
|
||||
ENTRY_NP(generic_armv4_bs_wr_2)
|
||||
add r0, r1, r2
|
||||
adds r0, r1, r2
|
||||
mov r1, r3
|
||||
ldr r2, [sp, #0]
|
||||
teq r2, #0
|
||||
RETc(eq)
|
||||
CHECK_LENGTH(r2, 99f)
|
||||
|
||||
1: ldrh r3, [r1], #2
|
||||
strh r3, [r0], #2
|
||||
@ -416,15 +405,14 @@ ENTRY_NP(generic_armv4_bs_wr_2)
|
||||
bne 1b
|
||||
|
||||
DSB
|
||||
RET
|
||||
99: RET
|
||||
END(generic_armv4_bs_wr_2)
|
||||
|
||||
ENTRY_NP(generic_armv4_bs_wr_2_swap)
|
||||
add r0, r1, r2
|
||||
adds r0, r1, r2
|
||||
mov r1, r3
|
||||
ldr r2, [sp, #0]
|
||||
teq r2, #0
|
||||
RETc(eq)
|
||||
CHECK_LENGTH(r2, 99f)
|
||||
|
||||
1: ldrh r3, [r1], #2
|
||||
BSWAP16(r3, r3, ip)
|
||||
@ -433,16 +421,15 @@ ENTRY_NP(generic_armv4_bs_wr_2_swap)
|
||||
bne 1b
|
||||
|
||||
DSB
|
||||
RET
|
||||
99: RET
|
||||
END(generic_armv4_bs_wr_2_swap)
|
||||
#endif
|
||||
|
||||
ENTRY_NP(generic_bs_wr_4)
|
||||
add r0, r1, r2
|
||||
adds r0, r1, r2
|
||||
mov r1, r3
|
||||
ldr r2, [sp, #0]
|
||||
teq r2, #0
|
||||
RETc(eq)
|
||||
CHECK_LENGTH(r2, 99f)
|
||||
|
||||
1: ldr r3, [r1], #4
|
||||
str r3, [r0], #4
|
||||
@ -450,15 +437,14 @@ ENTRY_NP(generic_bs_wr_4)
|
||||
bne 1b
|
||||
|
||||
DSB
|
||||
RET
|
||||
99: RET
|
||||
END(generic_bs_wr_4)
|
||||
|
||||
ENTRY_NP(generic_bs_wr_4_swap)
|
||||
add r0, r1, r2
|
||||
adds r0, r1, r2
|
||||
mov r1, r3
|
||||
ldr r2, [sp, #0]
|
||||
teq r2, #0
|
||||
RETc(eq)
|
||||
CHECK_LENGTH(r2, 99f)
|
||||
|
||||
1: ldr r3, [r1], #4
|
||||
BSWAP32(r3, r3, ip)
|
||||
@ -467,7 +453,7 @@ ENTRY_NP(generic_bs_wr_4_swap)
|
||||
bne 1b
|
||||
|
||||
DSB
|
||||
RET
|
||||
99: RET
|
||||
END(generic_bs_wr_4_swap)
|
||||
|
||||
/*
|
||||
@ -475,36 +461,34 @@ END(generic_bs_wr_4_swap)
|
||||
*/
|
||||
|
||||
ENTRY_NP(generic_bs_sr_1)
|
||||
add r0, r1, r2
|
||||
adds r0, r1, r2
|
||||
mov r1, r3
|
||||
ldr r2, [sp, #0]
|
||||
teq r2, #0
|
||||
RETc(eq)
|
||||
CHECK_LENGTH(r2, 99f)
|
||||
|
||||
1: strb r1, [r0], #1
|
||||
subs r2, r2, #1
|
||||
bne 1b
|
||||
|
||||
DSB
|
||||
RET
|
||||
99: RET
|
||||
END(generic_bs_sr_1)
|
||||
|
||||
#if (ARM_ARCH_4 + ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7) > 0
|
||||
ENTRY_NP(generic_armv4_bs_sr_2_swap)
|
||||
BSWAP16(r3, r3, r0) /* swap and fallthrough */
|
||||
ENTRY_NP(generic_armv4_bs_sr_2)
|
||||
add r0, r1, r2
|
||||
adds r0, r1, r2
|
||||
mov r1, r3
|
||||
ldr r2, [sp, #0]
|
||||
teq r2, #0
|
||||
RETc(eq)
|
||||
CHECK_LENGTH(r2, 99f)
|
||||
|
||||
1: strh r1, [r0], #2
|
||||
subs r2, r2, #1
|
||||
bne 1b
|
||||
|
||||
DSB
|
||||
RET
|
||||
99: RET
|
||||
END(generic_armv4_bs_sr_2)
|
||||
END(generic_armv4_bs_sr_2_swap)
|
||||
#endif
|
||||
@ -512,18 +496,17 @@ END(generic_armv4_bs_sr_2_swap)
|
||||
ENTRY_NP(generic_bs_sr_4_swap)
|
||||
BSWAP32(r3, r3, r0) /* swap and fallthrough */
|
||||
ENTRY_NP(generic_bs_sr_4)
|
||||
add r0, r1, r2
|
||||
adds r0, r1, r2
|
||||
mov r1, r3
|
||||
ldr r2, [sp, #0]
|
||||
teq r2, #0
|
||||
RETc(eq)
|
||||
CHECK_LENGTH(r2, 99f)
|
||||
|
||||
1: str r1, [r0], #4
|
||||
subs r2, r2, #1
|
||||
bne 1b
|
||||
|
||||
DSB
|
||||
RET
|
||||
99: RET
|
||||
END(generic_bs_sr_4)
|
||||
END(generic_bs_sr_4_swap)
|
||||
|
||||
@ -533,35 +516,35 @@ END(generic_bs_sr_4_swap)
|
||||
|
||||
#if (ARM_ARCH_4 + ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7) > 0
|
||||
ENTRY_NP(generic_armv4_bs_c_2)
|
||||
add r0, r1, r2
|
||||
adds r0, r1, r2
|
||||
ldr r2, [sp, #0]
|
||||
add r1, r2, r3
|
||||
adds r1, r2, r3
|
||||
ldr r2, [sp, #4]
|
||||
teq r2, #0
|
||||
RETc(eq)
|
||||
CHECK_LENGTH(r2, 99f)
|
||||
|
||||
lsls r2, r2, #1
|
||||
|
||||
cmp r0, r1
|
||||
blt 2f
|
||||
|
||||
1: ldrh r3, [r0], #2
|
||||
strh r3, [r1], #2
|
||||
subs r2, r2, #1
|
||||
adds r0, r0, r2
|
||||
adds r1, r1, r2
|
||||
negs r2, r2
|
||||
|
||||
1: ldrh r3, [r0, r2]
|
||||
strh r3, [r1, r2]
|
||||
adds r2, r2, #2
|
||||
bne 1b
|
||||
|
||||
DSB
|
||||
RET
|
||||
|
||||
2: add r0, r0, r2, lsl #1
|
||||
add r1, r1, r2, lsl #1
|
||||
sub r0, r0, #2
|
||||
sub r1, r1, #2
|
||||
|
||||
3: ldrh r3, [r0], #-2
|
||||
strh r3, [r1], #-2
|
||||
subs r2, r2, #1
|
||||
bne 3b
|
||||
2: subs r2, r2, #2
|
||||
ldrh r3, [r0, r2]
|
||||
strh r3, [r1, r2]
|
||||
bne 2b
|
||||
|
||||
DSB
|
||||
RET
|
||||
99: RET
|
||||
END(generic_armv4_bs_c_2)
|
||||
#endif
|
||||
|
||||
Loading…
Reference in New Issue
Block a user