Fixup USB Phy initialisation for Exynos5410.
odroid-xu now detects USB devices.
This commit is contained in:
skrll
parent
6ca4ffb177
commit
3ca8763071
@ -1,4 +1,4 @@
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/* $NetBSD: exynos5_reg.h,v 1.19 2014/10/02 16:17:33 skrll Exp $ */
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/* $NetBSD: exynos5_reg.h,v 1.20 2014/12/29 22:58:59 skrll Exp $ */
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/*-
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* Copyright (c) 2014 The NetBSD Foundation, Inc.
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@ -363,41 +363,42 @@
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/* used Exynos5 USB PHY registers */
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#define USB_PHY_HOST_CTRL0 0x00
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#define HOST_CTRL0_PHY_SWRST __BIT(0)
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#define HOST_CTRL0_LINK_SWRST __BIT(1)
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#define HOST_CTRL0_UTMI_SWRST __BIT(2)
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#define HOST_CTRL0_WORDINTERFACE __BIT(3)
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#define HOST_CTRL0_FORCESUSPEND __BIT(4)
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#define HOST_CTRL0_FORCESLEEP __BIT(5)
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#define HOST_CTRL0_SIDDQ __BIT(6)
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#define HOST_CTRL0_COMMONON_N __BIT(9) /* common block configuration during suspend */
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#define HOST_CTRL0_TESTBURNIN __BIT(11)
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#define HOST_CTRL0_RETENABLE __BIT(10)
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#define HOST_CTRL0_FSEL_MASK __BITS(16, 18) /* holds FSEL_CLKSEL_ */
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#define HOST_CTRL0_REFCLKSEL_MASK __BITS(19, 20)
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#define HOST_CTRL0_REFCLKSEL_XTAL __SHIFTIN(HOST_CRTL0_REFCLK_MASK, 0)
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#define HOST_CTRL0_REFCLKSEL_EXTL __SHIFTIN(HOST_CRTL0_REFCLK_MASK, 1)
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#define HOST_CTRL0_REFCLKSEL_CLKCORE __SHIFTIN(HOST_CRTL0_REFCLK_MASK, 2)
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#define HOST_CTRL0_PHY_SWRST_ALL __BIT(31)
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#define HOST_CTRL0_PHY_SWRST __BIT(0)
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#define HOST_CTRL0_LINK_SWRST __BIT(1)
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#define HOST_CTRL0_UTMI_SWRST __BIT(2)
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#define HOST_CTRL0_WORDINTERFACE __BIT(3)
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#define HOST_CTRL0_FORCESUSPEND __BIT(4)
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#define HOST_CTRL0_FORCESLEEP __BIT(5)
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#define HOST_CTRL0_SIDDQ __BIT(6)
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#define HOST_CTRL0_COMMONON_N __BIT(9) /* common block configuration during suspend */
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#define HOST_CTRL0_RETENABLE __BIT(10)
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#define HOST_CTRL0_TESTBURNIN __BIT(11)
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#define HOST_CTRL0_FSEL_MASK __BITS(16, 18) /* holds FSEL_CLKSEL_ */
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#define HOST_CTRL0_REFCLKSEL_MASK __BITS(19, 20)
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#define HOST_CTRL0_REFCLKSEL_XTAL 0
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#define HOST_CTRL0_REFCLKSEL_EXTL 1
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#define HOST_CTRL0_REFCLKSEL_CLKCORE 2
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#define HOST_CTRL0_PHY_SWRST_ALL __BIT(31)
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#define USB_PHY_HSIC_CTRL1 0x10
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#define USB_PHY_HSIC_TUNE1 0x14
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#define USB_PHY_HSIC_CTRL2 0x20
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#define USB_PHY_HSIC_TUNE2 0x24
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#define HSIC_CTRL_PHY_SWRST __BIT(0)
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#define HSIC_CTRL_UTMI_SWRST __BIT(2)
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#define HSIC_CTRL_WORDINTERFACE __BIT(3)
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#define HSIC_CTRL_FORCESUSPEND __BIT(4)
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#define HSIC_CTRL_FORCESLEEP __BIT(5)
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#define HSIC_CTRL_SIDDQ __BIT(6)
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#define HSIC_CTRL_REFCLKDIV_MASK __BITS(16,22)
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#define REFCLKDIV_12 __SHIFTIN(HSIC_CTRL_REFCLKDIV_MASK, 0x24)
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#define REFCLKDIV_15 __SHIFTIN(HSIC_CTRL_REFCLKDIV_MASK, 0x1c)
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#define REFCLKDIV_16 __SHIFTIN(HSIC_CTRL_REFCLKDIV_MASK, 0x1a)
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#define REFCLKDIV_19_2 __SHIFTIN(HSIC_CTRL_REFCLKDIV_MASK, 0x15)
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#define REFCLKDIV_20 __SHIFTIN(HSIC_CTRL_REFCLKDIV_MASK, 0x14)
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#define HSIC_CTRL_REFCLKSEL_MASK __BITS(23, 24)
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#define REFCLKSEL_HSIC_DEFAULT __SHIFTIN(HSIC_CTRL_REFCLKSEL_MASK, 2)
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#define HSIC_CTRL_PHY_SWRST __BIT(0)
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#define HSIC_CTRL_UTMI_SWRST __BIT(2)
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#define HSIC_CTRL_WORDINTERFACE __BIT(3)
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#define HSIC_CTRL_FORCESUSPEND __BIT(4)
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#define HSIC_CTRL_FORCESLEEP __BIT(5)
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#define HSIC_CTRL_SIDDQ __BIT(6)
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#define HSIC_CTRL_REFCLKDIV_MASK __BITS(16,22)
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#define HSIC_CTRL_REFCLKDIV_12 0x24
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#define HSIC_CTRL_REFCLKDIV_15 0x1c
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#define HSIC_CTRL_REFCLKDIV_16 0x1a
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#define HSIC_CTRL_REFCLKDIV_19_2 0x15
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#define HSIC_CTRL_REFCLKDIV_20 0x14
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#define HSIC_CTRL_REFCLKSEL_MASK __BITS(23, 24)
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#define HSIC_CTRL_REFCLKSEL_DEFAULT 2
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#define USB_PHY_HOST_EHCICTRL 0x30
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#define HOST_EHCICTRL_ENA_INCR16 __BIT(26)
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@ -1,4 +1,4 @@
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/* $NetBSD: exynos_soc.c,v 1.26 2014/12/29 22:34:08 skrll Exp $ */
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/* $NetBSD: exynos_soc.c,v 1.27 2014/12/29 22:58:59 skrll Exp $ */
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/*-
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* Copyright (c) 2014 The NetBSD Foundation, Inc.
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@ -34,7 +34,7 @@
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#define _ARM32_BUS_DMA_PRIVATE
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#include <sys/cdefs.h>
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__KERNEL_RCSID(1, "$NetBSD: exynos_soc.c,v 1.26 2014/12/29 22:34:08 skrll Exp $");
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__KERNEL_RCSID(1, "$NetBSD: exynos_soc.c,v 1.27 2014/12/29 22:58:59 skrll Exp $");
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#include <sys/param.h>
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#include <sys/bus.h>
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@ -878,34 +878,55 @@ static void
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exynos5410_usb2phy_enable(bus_space_handle_t usb2phy_bsh)
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{
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uint32_t phyhost; //, phyotg;
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uint32_t phyhsic1, phyhsic2, hsic_ctrl;
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uint32_t ehcictrl; //, ohcictrl;
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uint32_t phyhsic;
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uint32_t ehcictrl, ohcictrl;
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/* host configuration: */
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phyhost = bus_space_read_4(&exynos_bs_tag, usb2phy_bsh,
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USB_PHY_HOST_CTRL0);
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USB_PHY_HOST_CTRL0);
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/* host phy reference clock; assumption its 24 MHz now */
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phyhost &= ~HOST_CTRL0_FSEL_MASK;
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phyhost |= __SHIFTIN(HOST_CTRL0_FSEL_MASK, FSEL_CLKSEL_24M);
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phyhost |= __SHIFTIN(FSEL_CLKSEL_24M, HOST_CTRL0_FSEL_MASK);
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/* enable normal mode of operation */
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phyhost &= ~(HOST_CTRL0_FORCESUSPEND | HOST_CTRL0_FORCESLEEP);
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/* host phy reset */
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phyhost &= ~(HOST_CTRL0_PHY_SWRST | HOST_CTRL0_PHY_SWRST_ALL |
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HOST_CTRL0_SIDDQ | HOST_CTRL0_COMMONON_N);
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HOST_CTRL0_SIDDQ | HOST_CTRL0_FORCESUSPEND |
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HOST_CTRL0_FORCESLEEP);
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/* host link reset */
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phyhost |= HOST_CTRL0_LINK_SWRST | HOST_CTRL0_UTMI_SWRST;
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phyhost |= HOST_CTRL0_LINK_SWRST | HOST_CTRL0_UTMI_SWRST |
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HOST_CTRL0_COMMONON_N;
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/* do the reset */
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bus_space_write_4(&exynos_bs_tag, usb2phy_bsh,
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USB_PHY_HOST_CTRL0, phyhost);
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bus_space_write_4(&exynos_bs_tag, usb2phy_bsh, USB_PHY_HOST_CTRL0,
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phyhost);
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DELAY(10000);
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phyhost &= ~(HOST_CTRL0_LINK_SWRST | HOST_CTRL0_UTMI_SWRST);
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bus_space_write_4(&exynos_bs_tag, usb2phy_bsh,
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USB_PHY_HOST_CTRL0, phyhost);
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bus_space_write_4(&exynos_bs_tag, usb2phy_bsh, USB_PHY_HOST_CTRL0,
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phyhost);
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/* HSIC control */
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phyhsic =
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__SHIFTIN(HSIC_CTRL_REFCLKDIV_12, HSIC_CTRL_REFCLKDIV_MASK) |
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__SHIFTIN(HSIC_CTRL_REFCLKSEL_DEFAULT, HSIC_CTRL_REFCLKSEL_MASK) |
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HSIC_CTRL_PHY_SWRST;
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bus_space_write_4(&exynos_bs_tag, usb2phy_bsh, USB_PHY_HSIC_CTRL1,
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phyhsic);
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bus_space_write_4(&exynos_bs_tag, usb2phy_bsh, USB_PHY_HSIC_CTRL2,
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phyhsic);
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DELAY(10);
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phyhsic &= ~HSIC_CTRL_PHY_SWRST;
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bus_space_write_4(&exynos_bs_tag, usb2phy_bsh, USB_PHY_HSIC_CTRL1,
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phyhsic);
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bus_space_write_4(&exynos_bs_tag, usb2phy_bsh, USB_PHY_HSIC_CTRL2,
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phyhsic);
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DELAY(80);
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#if 0
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/* otg configuration: */
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@ -935,57 +956,21 @@ exynos5410_usb2phy_enable(bus_space_handle_t usb2phy_bsh)
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USB_PHY_OTG_SYS, phyotg);
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#endif
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/* HSIC phy configuration: */
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hsic_ctrl = HSIC_CTRL_FORCESUSPEND | HSIC_CTRL_FORCESLEEP |
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HSIC_CTRL_SIDDQ;
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phyhsic1 = bus_space_read_4(&exynos_bs_tag, usb2phy_bsh,
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USB_PHY_HSIC_CTRL1);
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phyhsic2 = bus_space_read_4(&exynos_bs_tag, usb2phy_bsh,
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USB_PHY_HSIC_CTRL1);
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phyhsic1 &= ~hsic_ctrl;
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phyhsic2 &= ~hsic_ctrl;
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bus_space_write_4(&exynos_bs_tag, usb2phy_bsh,
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USB_PHY_HSIC_CTRL1, phyhsic1);
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bus_space_write_4(&exynos_bs_tag, usb2phy_bsh,
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USB_PHY_HSIC_CTRL2, phyhsic2);
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DELAY(10000);
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hsic_ctrl = REFCLKDIV_12 | REFCLKSEL_HSIC_DEFAULT |
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HSIC_CTRL_UTMI_SWRST;
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phyhsic1 |= hsic_ctrl;
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phyhsic2 |= hsic_ctrl;
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bus_space_write_4(&exynos_bs_tag, usb2phy_bsh,
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USB_PHY_HSIC_CTRL1, phyhsic1);
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bus_space_write_4(&exynos_bs_tag, usb2phy_bsh,
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USB_PHY_HSIC_CTRL2, phyhsic2);
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DELAY(10000);
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hsic_ctrl = HSIC_CTRL_PHY_SWRST | HSIC_CTRL_UTMI_SWRST;
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phyhsic1 &= ~hsic_ctrl;
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phyhsic2 &= ~hsic_ctrl;
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bus_space_write_4(&exynos_bs_tag, usb2phy_bsh,
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USB_PHY_HSIC_CTRL1, phyhsic1);
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bus_space_write_4(&exynos_bs_tag, usb2phy_bsh,
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USB_PHY_HSIC_CTRL2, phyhsic2);
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DELAY(20000);
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/* enable EHCI DMA burst: */
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ehcictrl = bus_space_read_4(&exynos_bs_tag, usb2phy_bsh,
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USB_PHY_HOST_EHCICTRL);
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USB_PHY_HOST_EHCICTRL);
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ehcictrl |= HOST_EHCICTRL_ENA_INCRXALIGN |
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HOST_EHCICTRL_ENA_INCR4 | HOST_EHCICTRL_ENA_INCR8 |
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HOST_EHCICTRL_ENA_INCR16;
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HOST_EHCICTRL_ENA_INCR4 | HOST_EHCICTRL_ENA_INCR8 |
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HOST_EHCICTRL_ENA_INCR16;
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bus_space_write_4(&exynos_bs_tag, usb2phy_bsh,
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USB_PHY_HOST_EHCICTRL, ehcictrl);
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DELAY(10000);
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USB_PHY_HOST_EHCICTRL, ehcictrl);
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/* Set OHCI suspend */
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ohcictrl = bus_space_read_4(&exynos_bs_tag, usb2phy_bsh,
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USB_PHY_HOST_OHCICTRL);
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ohcictrl |= HOST_OHCICTRL_SUSPLGCY;
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bus_space_write_4(&exynos_bs_tag, usb2phy_bsh,
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USB_PHY_HOST_OHCICTRL, ohcictrl);
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}
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