HITACHI PERSONA support. patch by KIYOHARA Takashi
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@ -1,4 +1,4 @@
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/* $NetBSD: hd64461pcmcia.c,v 1.6 2001/07/13 16:21:39 uch Exp $ */
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/* $NetBSD: hd64461pcmcia.c,v 1.7 2001/10/08 15:34:24 uch Exp $ */
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/*-
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* Copyright (c) 2001 The NetBSD Foundation, Inc.
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@ -793,15 +793,18 @@ _chip_socket_enable(pcmcia_chipset_handle_t pch)
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memory_window_16(channel, MEMWIN_16M_COMMON_0);
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/* set the card type */
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r = hd64461_reg_read_1(gcr);
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if (channel == CHANNEL_0) {
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cardtype = pcmcia_card_gettype(ch->ch_pcmcia);
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r = hd64461_reg_read_1(gcr);
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if (cardtype == PCMCIA_IFTYPE_IO)
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r |= HD64461_PCC0GCR_P0PCCT;
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else
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r &= ~HD64461_PCC0GCR_P0PCCT;
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hd64461_reg_write_1(gcr, r);
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} else {
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/* reserved bit must be 0 */
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r &= ~HD64461_PCC1GCR_RESERVED;
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}
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hd64461_reg_write_1(gcr, r);
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DPRINTF("OK.\n");
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}
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@ -906,7 +909,7 @@ power_on(enum controller_channel channel)
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/* detect voltage and supply VCC */
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r = hd64461_reg_read_1(isr);
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switch (r & (HD64461_PCCISR_VS1 | HD64461_PCCISR_VS2)) {
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case (HD64461_PCCISR_VS1 | HD64461_PCCISR_VS2):
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case (HD64461_PCCISR_VS1 | HD64461_PCCISR_VS2): /* 5 V */
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DPRINTF("5V card\n");
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r = hd64461_reg_read_1(gcr);
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r &= ~HD64461_PCCGCR_VCC0;
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@ -915,7 +918,9 @@ power_on(enum controller_channel channel)
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r &= ~HD64461_PCCSCR_VCC1;
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hd64461_reg_write_1(scr, r);
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break;
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case HD64461_PCCISR_VS2:
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case HD64461_PCCISR_VS2: /* 3.3 / 5 V */
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/* FALLTHROUGH */
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case 0: /* x.x / 3.3 / 5 V */
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DPRINTF("3.3V card\n");
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if (channel == CHANNEL_1) {
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r = hd64461_reg_read_1(gcr);
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@ -930,6 +935,10 @@ power_on(enum controller_channel channel)
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r &= ~HD64461_PCCSCR_VCC1;
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hd64461_reg_write_1(scr, r);
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break;
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case HD64461_PCCISR_VS1: /* x.x V */
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/* FALLTHROUGH */
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printf("x.x V not supported.\n");
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return;
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default:
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printf("\nunknown Voltage. don't attach.\n");
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return;
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@ -1,4 +1,4 @@
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/* $NetBSD: hd64461pcmciareg.h,v 1.1 2001/02/21 15:39:09 uch Exp $ */
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/* $NetBSD: hd64461pcmciareg.h,v 1.2 2001/10/08 15:34:24 uch Exp $ */
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/*-
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* Copyright (c) 2001 The NetBSD Foundation, Inc.
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@ -57,7 +57,7 @@
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#define HD64461_PCC0GCR_REG8 0xb0002002
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#define HD64461_PCC0GCR_P0DRVE HD64461_PCCGCR_DRVE
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#define HD64461_PCC0GCR_P0PCCR HD64461_PCCGCR_PCCR
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#define HD64461_PCC0GCR_P0PCCT 0x20
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#define HD64461_PCC0GCR_P0PCCT HD64461_PCCGCR_PCCT
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#define HD64461_PCC0GCR_P0VCC0 HD64461_PCCGCR_VCC0
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#define HD64461_PCC0GCR_P0MMOD HD64461_PCCGCR_MMOD
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#define HD64461_PCC0GCR_P0MMOD_16M HD64461_PCCGCR_MMOD_16M
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@ -116,6 +116,7 @@
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#define HD64461_PCC1GCR_REG8 0xb0002012
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#define HD64461_PCC1GCR_P1DRVE HD64461_PCCGCR_DRVE
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#define HD64461_PCC1GCR_P1PCCR HD64461_PCCGCR_PCCR
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#define HD64461_PCC1GCR_RESERVED HD64461_PCCGCR_PCCT
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#define HD64461_PCC1GCR_P1VCC0 HD64461_PCCGCR_VCC0
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#define HD64461_PCC1GCR_P1MMOD HD64461_PCCGCR_MMOD
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#define HD64461_PCC1GCR_P1MMOD_16M HD64461_PCCGCR_MMOD_16M
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@ -203,6 +204,7 @@
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#define HD64461_PCCGCR_DRVE 0x80
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#define HD64461_PCCGCR_PCCR 0x40
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#define HD64461_PCCGCR_PCCT 0x20
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#define HD64461_PCCGCR_VCC0 0x10
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#define HD64461_PCCGCR_MMOD 0x08
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#define HD64461_PCCGCR_MMOD_16M 0x08
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