Add new headers that describe the 68851 (and 68030) MMU and
68040 (and 68060) MMU structures using names that more closely align with Motorola's documentation. The definitions here automagically adapt to 4K or 8K pages, based on the value of PGSHIFT, which must be a compile-time constant.
This commit is contained in:
thorpej
parent
ca3fed09ea
commit
3c258f0760
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@ -1,4 +1,4 @@
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# $NetBSD: ad.m68k,v 1.68 2023/08/29 04:35:26 mrg Exp $
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# $NetBSD: ad.m68k,v 1.69 2023/12/27 02:40:31 thorpej Exp $
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./usr/bin/elf2aout comp-sysutil-bin
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./usr/include/gcc-4.5/math-68881.h comp-obsolete obsolete
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./usr/include/gcc-4.5/tgmath.h comp-obsolete obsolete
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@ -54,6 +54,8 @@
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./usr/include/m68k/m68k.h comp-c-include
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./usr/include/m68k/math.h comp-c-include
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./usr/include/m68k/mcontext.h comp-c-include
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./usr/include/m68k/mmu_40.h comp-c-include
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./usr/include/m68k/mmu_51.h comp-c-include
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./usr/include/m68k/mutex.h comp-c-include
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./usr/include/m68k/param.h comp-c-include
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./usr/include/m68k/pcb.h comp-c-include
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@ -1,4 +1,4 @@
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# $NetBSD: Makefile,v 1.32 2020/02/01 19:41:48 tsutsui Exp $
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# $NetBSD: Makefile,v 1.33 2023/12/27 02:40:31 thorpej Exp $
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INCSDIR= /usr/include/m68k
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@ -12,7 +12,7 @@ INCS= ansi.h aout_machdep.h asm.h asm_single.h \
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int_const.h int_fmtio.h int_limits.h int_mwgwtypes.h int_types.h \
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kcore.h \
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limits.h lock.h \
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m68k.h math.h mcontext.h mutex.h \
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m68k.h math.h mcontext.h mmu_40.h mmu_51.h mutex.h \
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param.h pmap_motorola.h pcb.h proc.h profile.h \
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psl.h pte_motorola.h ptrace.h \
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reg.h rwlock.h setjmp.h signal.h sync_icache.h \
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@ -0,0 +1,214 @@
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/* $NetBSD: mmu_40.h,v 1.1 2023/12/27 02:40:31 thorpej Exp $ */
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/*-
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* Copyright (c) 2023 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _M68K_MMU_40_H_
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#define _M68K_MMU_40_H_
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/*
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* Translation table structures for the 68040 MMU.
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*
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* The 68040 MMU uses a 3-level tree structure. The root (L1) and
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* and pointer (L2) tables contain the base addresses of the tables
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* at the lext level, and the page (L3) tables contain the addresses
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* of the page descriptors, which may either contain the address of
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* a physical page (4K or 8K) directly, or point to an indirect
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* decriptor which points to the physical page.
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*
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* The L1 and L2 tables contain 128 4-byte descriptors, and are thus 512
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* bytes in size. Each of the 128 L1 descriptors corresponds to a 32MB
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* region of address space. Each of the 128 L2 descriptors corresponds
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* to a 256KB region of address space.
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*
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* For 8K pages, the L3 tables contain 32 4-byte descriptors, and are
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* thus 128 bytes in size.
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*
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* 31 25 24 18 17 13 12 0
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* | | | | |
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* 11111111111111 22222222222222 3333333333 ..........................
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* Root Pointer Page Page
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* Index Index Index Offset
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*
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* For 4K pages, the L3 tables contain 64 4-byte descriptors, and are
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* thus 256 bytes in size.
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*
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* 31 25 24 18 17 12 11 0
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* | | | | |
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* 11111111111111 22222222222222 333333333333 ........................
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* Root Pointer Page Page
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* Index Index Index Offset
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*
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* Logical Address Format
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*/
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#define LA40_L1_NBITS 7U
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#define LA40_L1_SHIFT 25
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#define LA40_L2_NBITS 7U
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#define LA40_L2_SHIFT 18
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#define LA40_L3_NBITS (32U - LA40_L1_NBITS - LA40_L2_NBITS - PGSHIFT)
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#define LA40_L3_SHIFT PGSHIFT
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#define LA40_L1_COUNT __BIT(LA40_L1_NBITS)
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#define LA40_L2_COUNT __BIT(LA40_L2_NBITS)
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#define LA40_L3_COUNT __BIT(LA40_L3_NBITS)
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#define LA40_L1_MASK (__BITS(0,(LA40_L1_NBITS - 1)) << LA40_L1_SHIFT)
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#define LA40_L2_MASK (__BITS(0,(LA40_L2_NBITS - 1)) << LA40_L2_SHIFT)
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#define LA40_L3_MASK (__BITS(0,(LA40_L3_NBITS - 1)) << LA40_L3_SHIFT)
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/* N.B. all tables must be aligned to their size */
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#define TBL40_L1_SIZE (LA40_L1_COUNT * sizeof(uint32_t))
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#define TBL40_L2_SIZE (LA40_L2_COUNT * sizeof(uint32_t))
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#define TBL40_L3_SIZE (LA40_L3_COUNT * sizeof(uint32_t))
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#define LA40_RI(va) __SHIFTOUT((va), LA40_L1_MASK) /* root index */
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#define LA40_PI(va) __SHIFTOUT((va), LA40_L2_MASK) /* pointer index */
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#define LA40_PGI(va) __SHIFTOUT((va), LA40_L3_MASK) /* page index */
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#define LA40_TRUNC_L1(va) (((vaddr_t)(va)) & LA40_L1_MASK)
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#define LA40_TRUNC_L2(va) (((vaddr_t)(va)) & (LA40_L1_MASK | LA40_L2_MASK))
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/*
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* The PTE format for L1 and L2 tables (Upper Tables).
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*/
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#define UTE40_PTA __BITS(9,31) /* Pointer Table Address (L1 PTE) */
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/* Page Table Address (L2 PTE) */
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#define UTE40_PGTA __BITS(8 - (13 - PGSHIFT),31)
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#define UTE40_U __BIT(3) /* Used (referenced) */
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#define UTE40_W __BIT(2) /* Write Protected */
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#define UTE40_UDT __BITS(0,1) /* Upper Descriptor Type */
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/* 00 or 01 -- Invalid */
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/* 10 or 11 -- Resident */
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#define UTE40_INVALID __SHIFTIN(0, UTE_UDT)
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#define UTE40_RESIDENT __SHIFTIN(2, UTE_UDT)
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/*
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* The PTE format for L3 tables.
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*
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* Some notes:
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*
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* - PFLUSH variants that specify non-global entries do not invalidate
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* global entries. If these PFLUSH variants are not used, then the G
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* bit can be used as a software-defined bit.
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*
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* - The UR bits are "reserved for use by the user", so can be
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* used as software-defined bits.
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*
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* - The U0 and U1 "User Page Attribute" bits should *not* be used
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* as software-defined bits; they are reflected on the UPA0 and UPA1
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* CPU signals if an external bus transfer results from the access,
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* meaning that they may have system-specific side-effects.
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*/
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#define PTE40_PGA __BITS(PGSHIFT,31) /* Page Physical Address */
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#define PTE40_UR_x __BIT(12) /* User Reserved (extra avail if 8K) */
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#define PTE40_UR __BIT(11) /* User Reserved */
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#define PTE40_G __BIT(10) /* Global */
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#define PTE40_U1 __BIT(9) /* User Page Attribute 1 */
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#define PTE40_U0 __BIT(8) /* User Page Attribute 0 */
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#define PTE40_S __BIT(7) /* Supervisor Protected */
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#define PTE40_CM __BITS(5,6) /* Cache Mode */
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/* 00 -- write-through */
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/* 01 -- copy-back */
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/* 10 -- non-cacheable, serialized */
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/* 11 -- non-cacheable */
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#define PTE40_M __BIT(4) /* Modified */
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#define PTE40_U __BIT(3) /* Used (referenced) */
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#define PTE40_W __BIT(2) /* Write Protected */
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#define PTE40_PDT __BITS(0,1) /* Page Descriptor Type */
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/* 00 -- Invalid */
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/* 01 or 11 -- Resident */
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/* 10 -- Indirect */
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#define PTE40_CM_WT __SHIFTIN(0, PTE40_CM)
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#define PTE40_CM_CB __SHIFTIN(1, PTE40_CM)
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#define PTE40_CM_NC_SER __SHIFTIN(2, PTE40_CM)
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#define PTE40_CM_NC __SHIFTIN(3, PTE40_CM)
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#define PTE40_INVALID __SHIFTIN(0, PTE40_PDT)
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#define PTE40_RESIDENT __SHIFTIN(1, PTE40_PDT)
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#define PTE40_INDIRECT __SHIFTIN(2, PTE40_PDT)
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/*
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* MMU registers (and the sections in the 68040 manual that
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* describe them).
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*/
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/*
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* 3.1.1 -- User and Supervisor Root Pointer Registers (32-bit)
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*
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* URP and SRP contain the physical address of the L1 table for
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* user and supervisor space, respectively. Bits 8-0 of the address
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* must be 0.
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*/
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/*
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* 3.1.2 -- Translation Control Register (16-bit)
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*/
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#define TCR40_E __BIT(15) /* enable translation */
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#define TCR40_P __BIT(14) /* page size: 0=4K 1=8K */
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/*
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* 3.1.3 -- Transparent Translation Registers (32-bit)
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*
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* There are 2 data translation registers (DTTR0, DTTR1) and 2
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* instruction translation registers (ITTR0, ITTR1).
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*/
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#define TTR40_LAB __BITS(24,31) /* logical address base */
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#define TTR40_LAM __BITS(16,23) /* logical address mask */
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#define TTR40_E __BIT(15) /* enable TTR */
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#define TTR40_SFIELD __BITS(13,14) /* Supervisor Mode field (see below) */
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#define TTR40_U1 PTE40_U1
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#define TTR40_U0 PTE40_U0
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#define TTR40_CM PTE40_CM
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#define TTR40_W PTE40_W
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#define TTR40_USER __SHIFTIN(0, TTR40_SFIELD)
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#define TTR40_SUPER __SHIFTIN(1, TTR40_SFIELD)
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#define TTR40_BOTH __SHIFTIN(2, TTR40_SFIELD)
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/*
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* 3.1.4 -- MMU Status Register
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*
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* N.B. If 8K pages are in use, bit 12 of the PA field is **undefined**.
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*/
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#define MMUSR40_PA PTE40_PGA
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#define MMUSR40_B __BIT(11) /* bus error */
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#define MMUSR40_G PTE40_G
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#define MMUSR40_U1 PTE40_U1
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#define MMUSR40_U0 PTE40_U0
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#define MMUSR40_S PTE40_S
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#define MMUSR40_CM PTE40_CM
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#define MMUSR40_M PTE40_M
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#define MMUSR40_W PTE40_W
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#define MMUSR40_T __BIT(1) /* Transparent Translation hit */
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#define MMUSR40_R PTE40_RESIDENT
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#endif /* _M68K_MMU_40_H_ */
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@ -0,0 +1,266 @@
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/* $NetBSD: mmu_51.h,v 1.1 2023/12/27 02:40:32 thorpej Exp $ */
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/*-
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* Copyright (c) 1997, 2023 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jeremy Cooper and by Jason R. Thorpe.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
|
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* are met:
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* 1. Redistributions of source code must retain the above copyright
|
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* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
|
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _M68K_MMU_51_H_
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#define _M68K_MMU_51_H_
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/*
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* Translation table structures for the 68851 MMU.
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*
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* The 68851 MMU (as well as the 68030's built-in MMU) are pretty flexible and
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* can use a 1, 2, 3, or 4-level tree structure and a number of page sizes.
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*
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* The logical address format is defined as:
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*
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* 31 0
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* | | | | | | |
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* SSSSSSSS AAAAAAAAAA BBBBBBBBBB CCCCCCCCCC DDDDDDDDDD PPPPPPPPPPPPPP
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* Initial A Index B Index C Index D Index Page Offset
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* Shift
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*
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* The Initial Shift, and number of A, B, C, and D index bits are defined
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* in the Translation Control register. Once the MMU encounters a tree
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* level where the number of index bits is 0, tree traversal stops. The
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* values of IS + TIA + TIB + TIC + TID + page offset must equal 32. For
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* example, for a 2-level arrangment using 4KB pages where all 32-bits of
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* the address are significant:
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*
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* IS TIA TIB TIC TID page
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* 0 + 10 + 10 + 0 + 0 + 12 == 32
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*/
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/*
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* The 68851 has 3 descriptor formats:
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*
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* Long Table Descriptors (8 byte)
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* Short Table Descriptors (4 byte)
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* Page Descriptors (4 byte)
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*
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* These occupy the lower 2 bits of each descriptor and the root pointers.
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*/
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#define DT51_INVALID 0
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#define DT51_PAGE 1 /* points to a page */
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#define DT51_SHORT 2 /* points to a short entry table */
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#define DT51_LONG 3 /* points to a long entry table */
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/*
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* Long Format Table Descriptor
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*
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* 63 48
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* +---+---.---.---.---.---.---.---.---.---.---.---.---.---.---.---+
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* |L/U| LIMIT |
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* +---+---.---+---.---.---+---+---+---+---+---+---+---+---+---.---+
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* | RAL | WAL |SG | S | 0 | 0 | 0 | 0 | U |WP | DT |
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* +---.---.---+---.---.---+---+---+---+---+---+---+---+---+---.---+
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* | TABLE PHYSICAL ADDRESS (BITS 31-16) |
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* +---.---.---.---.---.---.---.---.---.---.---.---+---.---.---.---+
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* | TABLE PHYSICAL ADDRESS (15-4) | UNUSED |
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* +---.---.---.---.---.---.---.---.---.---.---.---+---.---.---.---+
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* 15 0
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*
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* DT is either 2 or 3, depending on what next table descriptor format is.
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*/
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struct mmu51_ldte { /* 'dte' stands for 'descriptor table entry' */
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uint32_t ldte_attr;
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uint32_t ldte_addr;
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};
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#define DTE51_ADDR __BITS(4,31) /* table address mask */
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#define DTE51_LOWER __BIT(31) /* L: Index limit is lower limit */
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#define DTE51_LIMIT __BITS(16,30) /* L: Index limit */
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#define DTE51_RAL __BITS(13,15) /* L: Read Access Level */
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#define DTE51_WAL __BITS(10,12) /* L: Write Access Level */
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#define DTE51_SG __BIT(9) /* L: Shared Globally */
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#define DTE51_S __BIT(8) /* L: Supervisor protected */
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#define DTE51_U __BIT(3) /* Used */
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#define DTE51_WP __BIT(2) /* Write Protected */
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/*
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* Short Format Table Descriptor
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*
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* 31 16
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* +---.---.---.---.---.---.---.---.---.---.---.---.---.---.---.---+
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* | TABLE PHYSICAL BASE ADDRESS (BITS 31-16) |
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* +---.---.---.---.---.---.---.---.---.---.---.---+---+---+---.---+
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* | TABLE PHYSICAL BASE ADDRESS (15-4) | U |WP | DT |
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* +---.---.---.---.---.---.---.---.---.---.---.---+---+---+---.---+
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* 15 0
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*
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* DT is either 2 or 3, depending on what next table descriptor format is.
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*/
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/*
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* Long Format Page Descriptor (Level A table only)
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*
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* 63 48
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* +---.---.---.---.---.---.---.---.---.---.---.---.---.---.---.---+
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* | UNUSED |
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* +---.---.---+---.---.---+---+---+---+---+---+---+---+---+---.---+
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* | RAL | WAL |SG | S | G |CI | L | M | U |WP |DT (01)|
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* +---.---.---+---.---.---+---+---+---+---+---+---+---+---+---.---+
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* | PAGE PHYSICAL ADDRESS (BITS 31-16) |
|
||||
* +---.---.---.---.---.---.---.---.---.---.---.---.---.---.---.---+
|
||||
* | PAGE PHYS. ADDRESS (15-8) | UNUSED |
|
||||
* +---.---.---.---.---.---.---.---.---.---.---.---.---.---.---.---+
|
||||
* 15 0
|
||||
*
|
||||
* N.B. Unused bits of the page address (if the page size is larger
|
||||
* than 256 bytes) can be used as software-defined PTE bits.
|
||||
*/
|
||||
struct mmu51_lpte { /* 'pte' stands for 'page table entry' */
|
||||
uint32_t lpte_attr;
|
||||
uint32_t lpte_addr;
|
||||
};
|
||||
#define PTE51_ADDR __BITS(8,31) /* page address mask */
|
||||
#define PTE51_RAL __BITS(13,15) /* L: Read Access Level */
|
||||
#define PTE51_WAL __BITS(10,12) /* L: Write Access Level */
|
||||
#define PTE51_SG __BIT(9) /* L: Shared Globally */
|
||||
#define PTE51_S __BIT(8) /* L: Supervisor protected */
|
||||
#define PTE51_G __BIT(7) /* Gate allowed */
|
||||
#define PTE51_CI __BIT(6) /* Cache inhibit */
|
||||
#define PTE51_L __BIT(5) /* Lock entry */
|
||||
#define PTE51_M __BIT(4) /* Modified */
|
||||
#define PTE51_U __BIT(3) /* Used */
|
||||
#define PTE51_WP __BIT(2) /* Write Protected */
|
||||
|
||||
/*
|
||||
* Short Format Page Descriptor
|
||||
*
|
||||
* 31 16
|
||||
* +---.---.---.---.---.---.---.---.---.---.---.---.---.---.---.---+
|
||||
* | PAGE PHYSICAL BASE ADDRESS (BITS 31-16) |
|
||||
* +---.---.---.---.---.---.---.---+---+---+---+---+---+---+---.---+
|
||||
* | PAGE PHYS. BASE ADDRESS (15-8)| G |CI | L | M | U |WP |DT (01)|
|
||||
* +---.---.---.---.---.---.---.---+---+---+---+---+---+---+---.---+
|
||||
* 15 0
|
||||
*
|
||||
* N.B. Unused bits of the page address (if the page size is larger
|
||||
* than 256 bytes) can be used as software-defined PTE bits.
|
||||
*/
|
||||
|
||||
/*
|
||||
* MMU registers (and the sections in the 68851 manual that
|
||||
* describe them).
|
||||
*/
|
||||
|
||||
/*
|
||||
* 5.1.4 -- Root Pointer
|
||||
* (and also 6.1.1)
|
||||
*
|
||||
* This is a 64-bit register. The upper 32 bits contain configuration
|
||||
* information, and the lower 32 bits contain the A table address.
|
||||
* Bits 3-0 of the address must be 0. The root pointer is essentially
|
||||
* a long format table descriptor with only the U/L, limit, and SG bits.
|
||||
*
|
||||
* The 68851 has 3 root pointers:
|
||||
*
|
||||
* CRP CPU root pointer, for user accesses
|
||||
* SRP Supervisor root pointer
|
||||
* DRP DMA root pointer, for IOMMU functionality (not on '030)
|
||||
*
|
||||
* Selection of root pointer is as follows:
|
||||
*
|
||||
* FC3 FC2 SRE Root pointer used
|
||||
* 0 0 0 CRP
|
||||
* 0 0 1 CRP
|
||||
* 0 1 0 CRP
|
||||
* 0 1 1 SRP
|
||||
* 1 x x DRP
|
||||
*/
|
||||
struct mmu51_rootptr {
|
||||
unsigned long rp_attr; /* Lower/Upper Limit and access flags */
|
||||
unsigned long rp_addr; /* Physical Base Address */
|
||||
};
|
||||
|
||||
/*
|
||||
* 6.1.2 -- PMMU Cache Status (PCSR) (16-bit)
|
||||
*/
|
||||
#define PCSR51_F __BIT(15) /* Flush(ed) */
|
||||
#define PCSR51_LW __BIT(14) /* Lock Warning */
|
||||
#define PCSR51_TA __BITS(0,2) /* Task Alias (not '030) */
|
||||
|
||||
/*
|
||||
* 6.1.3 -- Translation Control (TCR) (32-bit)
|
||||
*/
|
||||
#define TCR51_E __BIT(31) /* Enable translation */
|
||||
#define TCR51_SRE __BIT(25) /* Supervisor Root Enable */
|
||||
#define TCR51_FCL __BIT(24) /* Function Code Lookup */
|
||||
#define TCR51_PS __BITS(20,23) /* Page Size (see below) */
|
||||
#define TCR51_IS __BITS(16,19) /* Initial Shift */
|
||||
#define TCR51_TIA __BITS(12,15) /* Table A Index bits */
|
||||
#define TCR51_TIB __BITS(8,11) /* Table B Index bits */
|
||||
#define TCR51_TIC __BITS(4,7) /* Table C Index bits */
|
||||
#define TCR51_TID __BITS(0,3) /* Table D Index bits */
|
||||
|
||||
/*
|
||||
* Astute readers will note that the value in the PS field is
|
||||
* log2(PAGE_SIZE).
|
||||
*/
|
||||
#define TCR51_PS_256 __SHIFTIN(0x8, TCR51_PS)
|
||||
#define TCR51_PS_512 __SHIFTIN(0x9, TCR51_PS)
|
||||
#define TCR51_PS_1K __SHIFTIN(0xa, TCR51_PS)
|
||||
#define TCR51_PS_2K __SHIFTIN(0xb, TCR51_PS)
|
||||
#define TCR51_PS_4K __SHIFTIN(0xc, TCR51_PS)
|
||||
#define TCR51_PS_8K __SHIFTIN(0xd, TCR51_PS)
|
||||
#define TCR51_PS_16K __SHIFTIN(0xe, TCR51_PS)
|
||||
#define TCR51_PS_32K __SHIFTIN(0xf, TCR51_PS)
|
||||
|
||||
/*
|
||||
* 6.1.4 -- Current Access Level (8-bit)
|
||||
* 6.1.5 -- Validate Access Level
|
||||
*/
|
||||
#define CAL51_AL __BITS(5,7)
|
||||
|
||||
/*
|
||||
* 6.1.6 -- Stack Change Control (8-bit)
|
||||
*/
|
||||
|
||||
/*
|
||||
* 6.1.7 -- Access Control (16-bit)
|
||||
*/
|
||||
#define AC51_MC __BIT(7) /* Module Control */
|
||||
#define AC51_ALC __BITS(4,5) /* Access Level Control */
|
||||
#define AC51_MDS __BITS(0,1) /* Module Descriptor Size */
|
||||
|
||||
/*
|
||||
* 6.1.8 -- PMMU Status Register (PSR) (16-bit)
|
||||
*/
|
||||
#define PSR51_B __BIT(15) /* Bus Error */
|
||||
#define PSR51_L __BIT(14) /* Limit Violation */
|
||||
#define PSR51_S __BIT(13) /* Supervisor Violation */
|
||||
#define PSR51_A __BIT(12) /* Access Level Violation */
|
||||
#define PSR51_W __BIT(11) /* Write Protected */
|
||||
#define PSR51_I __BIT(10) /* Invalid */
|
||||
#define PSR51_M __BIT(9) /* Modified */
|
||||
#define PSR51_G __BIT(8) /* Gate */
|
||||
#define PSR51_C __BIT(7) /* Globally Sharable */
|
||||
#define PSR51_N __BITS(0,2) /* Number of levels */
|
||||
|
||||
#endif /* _M68K_MMU_51_H_ */
|
||||
Loading…
Reference in New Issue