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Use new common, MIPS3 clock handling. This eliminates some port-specific 

code in favor of common MIPS3 code.
This commit is contained in:
gdamore 2006-09-02 22:54:47 +00:00
parent b671de1aa9
commit 3bc99cc29a
6 changed files with 11 additions and 244 deletions
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5
sys/arch/evbmips/conf/files.alchemy
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@ -1,4 +1,4 @@
# $NetBSD: files.alchemy,v 1.5 2006/02/23 17:14:01 shige Exp $ # $NetBSD: files.alchemy,v 1.6 2006/09/02 22:54:47 gdamore Exp $
# Platform support - select just one, please # Platform support - select just one, please
defflag opt_alchemy.h ALCHEMY_GENERIC defflag opt_alchemy.h ALCHEMY_GENERIC
@ -20,14 +20,13 @@ file arch/evbmips/alchemy/omsal400.c alchemy_omsal400
file arch/evbmips/alchemy/pciide_machdep.c pciide_common file arch/evbmips/alchemy/pciide_machdep.c pciide_common
file arch/mips/mips/bus_dma.c file arch/mips/mips/bus_dma.c
file arch/evbmips/evbmips/clock.c
file arch/evbmips/evbmips/disksubr.c file arch/evbmips/evbmips/disksubr.c
file arch/evbmips/evbmips/interrupt.c file arch/evbmips/evbmips/interrupt.c
file arch/evbmips/evbmips/yamon.c file arch/evbmips/evbmips/yamon.c
file arch/mips/mips/mips3_clock.c
file arch/mips/mips/softintr.c file arch/mips/mips/softintr.c
# System bus # System bus
device mainbus { } device mainbus { }
attach mainbus at root attach mainbus at root

5
sys/arch/evbmips/conf/files.atheros
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@ -1,4 +1,4 @@
# $NetBSD: files.atheros,v 1.3 2006/06/08 06:15:59 gdamore Exp $ # $NetBSD: files.atheros,v 1.4 2006/09/02 22:54:47 gdamore Exp $
file arch/evbmips/atheros/mach_intr.c file arch/evbmips/atheros/mach_intr.c
@ -6,13 +6,12 @@ file arch/evbmips/atheros/autoconf.c
file arch/evbmips/atheros/machdep.c file arch/evbmips/atheros/machdep.c
file arch/mips/mips/bus_dma.c file arch/mips/mips/bus_dma.c
file arch/evbmips/evbmips/clock.c
file arch/evbmips/evbmips/disksubr.c file arch/evbmips/evbmips/disksubr.c
file arch/evbmips/evbmips/interrupt.c file arch/evbmips/evbmips/interrupt.c
file arch/mips/mips/mips3_clock.c
file arch/mips/mips/softintr.c file arch/mips/mips/softintr.c
# System bus # System bus
device mainbus { } device mainbus { }
attach mainbus at root attach mainbus at root

4
sys/arch/evbmips/conf/files.malta
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@ -1,4 +1,4 @@
# $NetBSD: files.malta,v 1.11 2006/03/28 03:43:57 gdamore Exp $ # $NetBSD: files.malta,v 1.12 2006/09/02 22:54:47 gdamore Exp $
file arch/evbmips/malta/malta_bus_io.c file arch/evbmips/malta/malta_bus_io.c
file arch/evbmips/malta/malta_bus_mem.c file arch/evbmips/malta/malta_bus_mem.c
@ -10,11 +10,11 @@ file arch/evbmips/malta/leds.c
file arch/evbmips/malta/machdep.c file arch/evbmips/malta/machdep.c
file arch/mips/mips/bus_dma.c file arch/mips/mips/bus_dma.c
file arch/evbmips/evbmips/clock.c
file arch/evbmips/evbmips/disksubr.c file arch/evbmips/evbmips/disksubr.c
file arch/evbmips/evbmips/interrupt.c file arch/evbmips/evbmips/interrupt.c
file arch/evbmips/evbmips/yamon.c # XXX should be in arch/mips/yamon ? file arch/evbmips/evbmips/yamon.c # XXX should be in arch/mips/yamon ?
file arch/mips/mips/mips3_clock.c
file arch/mips/mips/softintr.c file arch/mips/mips/softintr.c
# The autoconfiguration root. # The autoconfiguration root.

162
sys/arch/evbmips/evbmips/clock.c
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@ -1,162 +0,0 @@
/* $NetBSD: clock.c,v 1.13 2006/09/02 20:27:21 gdamore Exp $ */
/*
* Copyright (c) 1992, 1993
* The Regents of the University of California. All rights reserved.
*
* This code is derived from software contributed to Berkeley by
* the Systems Programming Group of the University of Utah Computer
* Science Department and Ralph Campbell.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* from: Utah Hdr: clock.c 1.18 91/01/21
*
* @(#)clock.c 8.1 (Berkeley) 6/10/93
*/
/*
* Copyright (c) 1988 University of Utah.
*
* This code is derived from software contributed to Berkeley by
* the Systems Programming Group of the University of Utah Computer
* Science Department and Ralph Campbell.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the University of
* California, Berkeley and its contributors.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* from: Utah Hdr: clock.c 1.18 91/01/21
*
* @(#)clock.c 8.1 (Berkeley) 6/10/93
*/
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
__KERNEL_RCSID(0, "$NetBSD: clock.c,v 1.13 2006/09/02 20:27:21 gdamore Exp $");
#include <sys/param.h>
#include <sys/kernel.h>
#include <sys/systm.h>
#include <sys/device.h>
#include <sys/sched.h>
#include <sys/timetc.h>
#include <machine/bus.h>
#include <mips/locore.h>
#include <evbmips/evbmips/clockvar.h>
static struct timecounter evbmips_timecounter = {
(timecounter_get_t *)mips3_cp0_count_read, /* get_timecount */
0, /* no poll_pps */
~0u, /* counter_mask */
0, /* frequency */
"mips_cp0", /* name */
0, /* quality */
};
/*
* Start the real-time and statistics clocks. Leave stathz 0 since there
* are no other timers available.
*/
void
cpu_initclocks(void)
{
next_cp0_clk_intr = mips3_cp0_count_read() + curcpu()->ci_cycles_per_hz;
mips3_cp0_compare_write(next_cp0_clk_intr);
evbmips_timecounter.tc_frequency = curcpu()->ci_cpu_freq;
if (mips_cpu_flags & CPU_MIPS_DOUBLE_COUNT)
evbmips_timecounter.tc_frequency /= 2;
tc_init(&evbmips_timecounter);
}
/*
* We assume newhz is either stathz or profhz, and that neither will
* change after being set up above. Could recalculate intervals here
* but that would be a drag.
*/
void
setstatclockrate(int newhz)
{
/* nothing we can do */
}
/*
* Wait for at least "n" microseconds.
*/
void
delay(int n)
{
uint32_t cur, last, delta, usecs;
last = mips3_cp0_count_read();
delta = usecs = 0;
while (n > usecs) {
cur = mips3_cp0_count_read();
/* Check to see if the timer has wrapped around. */
if (cur < last)
delta += ((curcpu()->ci_cycles_per_hz - last) + cur);
else
delta += (cur - last);
last = cur;
if (delta >= curcpu()->ci_divisor_delay) {
usecs += delta / curcpu()->ci_divisor_delay;
delta %= curcpu()->ci_divisor_delay;
}
}
}

34
sys/arch/evbmips/evbmips/clockvar.h
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@ -1,34 +0,0 @@
/* $NetBSD: clockvar.h,v 1.5 2006/03/28 03:43:57 gdamore Exp $ */
/*
* Copyright (c) 1994, 1995 Carnegie-Mellon University.
* All rights reserved.
*
* Author: Chris G. Demetriou
*
* Permission to use, copy, modify and distribute this software and
* its documentation is hereby granted, provided that both the copyright
* notice and this permission notice appear in all copies of the
* software, derivative works or modified versions, and any portions
* thereof, and that both notices appear in supporting documentation.
*
* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
*
* Carnegie Mellon requests users of this software to return to
*
* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
* School of Computer Science
* Carnegie Mellon University
* Pittsburgh PA 15213-3890
*
* any improvements or extensions that they make and grant Carnegie the
* rights to redistribute these changes.
*/
/* XXX need better places for following two declarations */
/* CP0 count register; set in interrupt handler, used by microtime. */
extern uint32_t last_cp0_count;
/* CP0 compare register; set initially in cpu_initclocks. */
extern uint32_t next_cp0_clk_intr;

45
sys/arch/evbmips/evbmips/interrupt.c
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@ -1,4 +1,4 @@
/* $NetBSD: interrupt.c,v 1.7 2005/12/11 12:17:11 christos Exp $ */ /* $NetBSD: interrupt.c,v 1.8 2006/09/02 22:54:47 gdamore Exp $ */
/*- /*-
* Copyright (c) 2001 The NetBSD Foundation, Inc. * Copyright (c) 2001 The NetBSD Foundation, Inc.
@ -37,29 +37,21 @@
*/ */
#include <sys/cdefs.h> #include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: interrupt.c,v 1.7 2005/12/11 12:17:11 christos Exp $"); __KERNEL_RCSID(0, "$NetBSD: interrupt.c,v 1.8 2006/09/02 22:54:47 gdamore Exp $");
#include <sys/param.h> #include <sys/param.h>
#include <sys/device.h> #include <sys/device.h>
#include <uvm/uvm_extern.h> #include <uvm/uvm_extern.h>
#include <mips/mips3_clock.h>
#include <machine/intr.h> #include <machine/intr.h>
#include <machine/locore.h> #include <machine/locore.h>
#include <evbmips/evbmips/clockvar.h>
struct evcnt mips_int5_evcnt =
EVCNT_INITIALIZER(EVCNT_TYPE_INTR, NULL, "mips", "int 5 (clock)");
uint32_t last_cp0_count; /* used by microtime() */
uint32_t next_cp0_clk_intr; /* used to schedule hard clock interrupts */
void void
intr_init(void) intr_init(void)
{ {
evcnt_attach_static(&mips_int5_evcnt);
evbmips_intr_init(); /* board specific stuff */ evbmips_intr_init(); /* board specific stuff */
softintr_init(); softintr_init();
@ -68,38 +60,11 @@ intr_init(void)
void void
cpu_intr(u_int32_t status, u_int32_t cause, u_int32_t pc, u_int32_t ipending) cpu_intr(u_int32_t status, u_int32_t cause, u_int32_t pc, u_int32_t ipending)
{ {
struct clockframe cf;
uint32_t new_cnt;
uvmexp.intrs++; uvmexp.intrs++;
if (ipending & MIPS_INT_MASK_5) { if (ipending & MIPS_INT_MASK_5) {
last_cp0_count = next_cp0_clk_intr; /* call the common MIPS3 clock interrupt handler */
next_cp0_clk_intr += curcpu()->ci_cycles_per_hz; mips3_clockintr(status, pc);
mips3_cp0_compare_write(next_cp0_clk_intr);
/* Check for lost clock interrupts */
new_cnt = mips3_cp0_count_read();
/*
* Missed one or more clock interrupts, so let's start
* counting again from the current value.
*/
if ((next_cp0_clk_intr - new_cnt) & 0x80000000) {
#if 0 /* XXX - should add an event counter for this */
missed_clk_intrs++;
#endif
next_cp0_clk_intr = new_cnt +
curcpu()->ci_cycles_per_hz;
mips3_cp0_compare_write(next_cp0_clk_intr);
}
cf.pc = pc;
cf.sr = status;
hardclock(&cf);
mips_int5_evcnt.ev_count++;
/* Re-enable clock interrupts. */ /* Re-enable clock interrupts. */
cause &= ~MIPS_INT_MASK_5; cause &= ~MIPS_INT_MASK_5;