Use new common, MIPS3 clock handling. This eliminates some port-specific
code in favor of common MIPS3 code.
This commit is contained in:
parent
b671de1aa9
commit
3bc99cc29a
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@ -1,4 +1,4 @@
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# $NetBSD: files.alchemy,v 1.5 2006/02/23 17:14:01 shige Exp $
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# $NetBSD: files.alchemy,v 1.6 2006/09/02 22:54:47 gdamore Exp $
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# Platform support - select just one, please
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# Platform support - select just one, please
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defflag opt_alchemy.h ALCHEMY_GENERIC
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defflag opt_alchemy.h ALCHEMY_GENERIC
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@ -20,14 +20,13 @@ file arch/evbmips/alchemy/omsal400.c alchemy_omsal400
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file arch/evbmips/alchemy/pciide_machdep.c pciide_common
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file arch/evbmips/alchemy/pciide_machdep.c pciide_common
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file arch/mips/mips/bus_dma.c
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file arch/mips/mips/bus_dma.c
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file arch/evbmips/evbmips/clock.c
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file arch/evbmips/evbmips/disksubr.c
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file arch/evbmips/evbmips/disksubr.c
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file arch/evbmips/evbmips/interrupt.c
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file arch/evbmips/evbmips/interrupt.c
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file arch/evbmips/evbmips/yamon.c
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file arch/evbmips/evbmips/yamon.c
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file arch/mips/mips/mips3_clock.c
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file arch/mips/mips/softintr.c
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file arch/mips/mips/softintr.c
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# System bus
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# System bus
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device mainbus { }
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device mainbus { }
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attach mainbus at root
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attach mainbus at root
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@ -1,4 +1,4 @@
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# $NetBSD: files.atheros,v 1.3 2006/06/08 06:15:59 gdamore Exp $
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# $NetBSD: files.atheros,v 1.4 2006/09/02 22:54:47 gdamore Exp $
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file arch/evbmips/atheros/mach_intr.c
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file arch/evbmips/atheros/mach_intr.c
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@ -6,13 +6,12 @@ file arch/evbmips/atheros/autoconf.c
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file arch/evbmips/atheros/machdep.c
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file arch/evbmips/atheros/machdep.c
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file arch/mips/mips/bus_dma.c
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file arch/mips/mips/bus_dma.c
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file arch/evbmips/evbmips/clock.c
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file arch/evbmips/evbmips/disksubr.c
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file arch/evbmips/evbmips/disksubr.c
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file arch/evbmips/evbmips/interrupt.c
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file arch/evbmips/evbmips/interrupt.c
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file arch/mips/mips/mips3_clock.c
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file arch/mips/mips/softintr.c
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file arch/mips/mips/softintr.c
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# System bus
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# System bus
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device mainbus { }
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device mainbus { }
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attach mainbus at root
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attach mainbus at root
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@ -1,4 +1,4 @@
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# $NetBSD: files.malta,v 1.11 2006/03/28 03:43:57 gdamore Exp $
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# $NetBSD: files.malta,v 1.12 2006/09/02 22:54:47 gdamore Exp $
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file arch/evbmips/malta/malta_bus_io.c
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file arch/evbmips/malta/malta_bus_io.c
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file arch/evbmips/malta/malta_bus_mem.c
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file arch/evbmips/malta/malta_bus_mem.c
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@ -10,11 +10,11 @@ file arch/evbmips/malta/leds.c
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file arch/evbmips/malta/machdep.c
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file arch/evbmips/malta/machdep.c
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file arch/mips/mips/bus_dma.c
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file arch/mips/mips/bus_dma.c
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file arch/evbmips/evbmips/clock.c
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file arch/evbmips/evbmips/disksubr.c
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file arch/evbmips/evbmips/disksubr.c
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file arch/evbmips/evbmips/interrupt.c
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file arch/evbmips/evbmips/interrupt.c
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file arch/evbmips/evbmips/yamon.c # XXX should be in arch/mips/yamon ?
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file arch/evbmips/evbmips/yamon.c # XXX should be in arch/mips/yamon ?
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file arch/mips/mips/mips3_clock.c
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file arch/mips/mips/softintr.c
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file arch/mips/mips/softintr.c
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# The autoconfiguration root.
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# The autoconfiguration root.
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@ -1,162 +0,0 @@
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/* $NetBSD: clock.c,v 1.13 2006/09/02 20:27:21 gdamore Exp $ */
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/*
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* Copyright (c) 1992, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* the Systems Programming Group of the University of Utah Computer
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* Science Department and Ralph Campbell.
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*
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* Redistribution and use in source and binary forms, with or without
|
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* modification, are permitted provided that the following conditions
|
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* are met:
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* 1. Redistributions of source code must retain the above copyright
|
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
|
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* notice, this list of conditions and the following disclaimer in the
|
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
|
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: Utah Hdr: clock.c 1.18 91/01/21
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*
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* @(#)clock.c 8.1 (Berkeley) 6/10/93
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*/
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/*
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* Copyright (c) 1988 University of Utah.
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*
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* This code is derived from software contributed to Berkeley by
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* the Systems Programming Group of the University of Utah Computer
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* Science Department and Ralph Campbell.
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*
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* Redistribution and use in source and binary forms, with or without
|
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* modification, are permitted provided that the following conditions
|
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* are met:
|
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* 1. Redistributions of source code must retain the above copyright
|
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* notice, this list of conditions and the following disclaimer.
|
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* 2. Redistributions in binary form must reproduce the above copyright
|
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* notice, this list of conditions and the following disclaimer in the
|
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
|
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
|
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
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||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
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* SUCH DAMAGE.
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*
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* from: Utah Hdr: clock.c 1.18 91/01/21
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*
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* @(#)clock.c 8.1 (Berkeley) 6/10/93
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*/
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#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
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__KERNEL_RCSID(0, "$NetBSD: clock.c,v 1.13 2006/09/02 20:27:21 gdamore Exp $");
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#include <sys/param.h>
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#include <sys/kernel.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <sys/sched.h>
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#include <sys/timetc.h>
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#include <machine/bus.h>
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#include <mips/locore.h>
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#include <evbmips/evbmips/clockvar.h>
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static struct timecounter evbmips_timecounter = {
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(timecounter_get_t *)mips3_cp0_count_read, /* get_timecount */
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0, /* no poll_pps */
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~0u, /* counter_mask */
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0, /* frequency */
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"mips_cp0", /* name */
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0, /* quality */
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};
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/*
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* Start the real-time and statistics clocks. Leave stathz 0 since there
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* are no other timers available.
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*/
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void
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cpu_initclocks(void)
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{
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next_cp0_clk_intr = mips3_cp0_count_read() + curcpu()->ci_cycles_per_hz;
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mips3_cp0_compare_write(next_cp0_clk_intr);
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evbmips_timecounter.tc_frequency = curcpu()->ci_cpu_freq;
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if (mips_cpu_flags & CPU_MIPS_DOUBLE_COUNT)
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evbmips_timecounter.tc_frequency /= 2;
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tc_init(&evbmips_timecounter);
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}
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/*
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* We assume newhz is either stathz or profhz, and that neither will
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* change after being set up above. Could recalculate intervals here
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* but that would be a drag.
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*/
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void
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setstatclockrate(int newhz)
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{
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/* nothing we can do */
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}
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/*
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* Wait for at least "n" microseconds.
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*/
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void
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delay(int n)
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{
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uint32_t cur, last, delta, usecs;
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last = mips3_cp0_count_read();
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delta = usecs = 0;
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while (n > usecs) {
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cur = mips3_cp0_count_read();
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/* Check to see if the timer has wrapped around. */
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if (cur < last)
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delta += ((curcpu()->ci_cycles_per_hz - last) + cur);
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else
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delta += (cur - last);
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last = cur;
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if (delta >= curcpu()->ci_divisor_delay) {
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usecs += delta / curcpu()->ci_divisor_delay;
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delta %= curcpu()->ci_divisor_delay;
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}
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}
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}
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@ -1,34 +0,0 @@
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/* $NetBSD: clockvar.h,v 1.5 2006/03/28 03:43:57 gdamore Exp $ */
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/*
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* Copyright (c) 1994, 1995 Carnegie-Mellon University.
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* All rights reserved.
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*
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* Author: Chris G. Demetriou
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*
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* Permission to use, copy, modify and distribute this software and
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* its documentation is hereby granted, provided that both the copyright
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* notice and this permission notice appear in all copies of the
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* software, derivative works or modified versions, and any portions
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* thereof, and that both notices appear in supporting documentation.
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*
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* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
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* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
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* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
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*
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* Carnegie Mellon requests users of this software to return to
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*
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* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
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* School of Computer Science
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* Carnegie Mellon University
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* Pittsburgh PA 15213-3890
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*
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* any improvements or extensions that they make and grant Carnegie the
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* rights to redistribute these changes.
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*/
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/* XXX need better places for following two declarations */
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/* CP0 count register; set in interrupt handler, used by microtime. */
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extern uint32_t last_cp0_count;
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/* CP0 compare register; set initially in cpu_initclocks. */
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extern uint32_t next_cp0_clk_intr;
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/* $NetBSD: interrupt.c,v 1.7 2005/12/11 12:17:11 christos Exp $ */
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/* $NetBSD: interrupt.c,v 1.8 2006/09/02 22:54:47 gdamore Exp $ */
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/*-
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/*-
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* Copyright (c) 2001 The NetBSD Foundation, Inc.
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* Copyright (c) 2001 The NetBSD Foundation, Inc.
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@ -37,29 +37,21 @@
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*/
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*/
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#include <sys/cdefs.h>
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: interrupt.c,v 1.7 2005/12/11 12:17:11 christos Exp $");
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__KERNEL_RCSID(0, "$NetBSD: interrupt.c,v 1.8 2006/09/02 22:54:47 gdamore Exp $");
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#include <sys/param.h>
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#include <sys/param.h>
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#include <sys/device.h>
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#include <sys/device.h>
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#include <uvm/uvm_extern.h>
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#include <uvm/uvm_extern.h>
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#include <mips/mips3_clock.h>
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#include <machine/intr.h>
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#include <machine/intr.h>
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#include <machine/locore.h>
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#include <machine/locore.h>
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#include <evbmips/evbmips/clockvar.h>
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struct evcnt mips_int5_evcnt =
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EVCNT_INITIALIZER(EVCNT_TYPE_INTR, NULL, "mips", "int 5 (clock)");
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uint32_t last_cp0_count; /* used by microtime() */
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uint32_t next_cp0_clk_intr; /* used to schedule hard clock interrupts */
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void
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void
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intr_init(void)
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intr_init(void)
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{
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{
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evcnt_attach_static(&mips_int5_evcnt);
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evbmips_intr_init(); /* board specific stuff */
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evbmips_intr_init(); /* board specific stuff */
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softintr_init();
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softintr_init();
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void
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void
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cpu_intr(u_int32_t status, u_int32_t cause, u_int32_t pc, u_int32_t ipending)
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cpu_intr(u_int32_t status, u_int32_t cause, u_int32_t pc, u_int32_t ipending)
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{
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{
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struct clockframe cf;
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uint32_t new_cnt;
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uvmexp.intrs++;
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uvmexp.intrs++;
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if (ipending & MIPS_INT_MASK_5) {
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if (ipending & MIPS_INT_MASK_5) {
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last_cp0_count = next_cp0_clk_intr;
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/* call the common MIPS3 clock interrupt handler */
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next_cp0_clk_intr += curcpu()->ci_cycles_per_hz;
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mips3_clockintr(status, pc);
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mips3_cp0_compare_write(next_cp0_clk_intr);
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/* Check for lost clock interrupts */
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new_cnt = mips3_cp0_count_read();
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/*
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* Missed one or more clock interrupts, so let's start
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* counting again from the current value.
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*/
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if ((next_cp0_clk_intr - new_cnt) & 0x80000000) {
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#if 0 /* XXX - should add an event counter for this */
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missed_clk_intrs++;
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#endif
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next_cp0_clk_intr = new_cnt +
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curcpu()->ci_cycles_per_hz;
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mips3_cp0_compare_write(next_cp0_clk_intr);
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}
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cf.pc = pc;
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cf.sr = status;
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hardclock(&cf);
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mips_int5_evcnt.ev_count++;
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/* Re-enable clock interrupts. */
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/* Re-enable clock interrupts. */
|
||||||
cause &= ~MIPS_INT_MASK_5;
|
cause &= ~MIPS_INT_MASK_5;
|
||||||
|
|
Loading…
Reference in New Issue