Make GDIUM build again after matt-nb5-mips64 merge. untested as I don't have
this hardware, but I'll use this as a base for Lemote Fulong support.
This commit is contained in:
bouyer
parent
b58f35c978
commit
3b0bc4ff9e
@ -1,4 +1,4 @@
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# $NetBSD: files.gdium,v 1.1 2009/08/06 00:50:25 matt Exp $
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# $NetBSD: files.gdium,v 1.2 2011/06/08 17:47:48 bouyer Exp $
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file arch/evbmips/gdium/gdium_bus_io.c
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file arch/evbmips/gdium/gdium_bus_mem.c
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@ -15,7 +15,6 @@ file arch/evbmips/evbmips/interrupt.c
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file arch/mips/mips/mips3_clock.c
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file arch/mips/mips/mips3_clockintr.c
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file arch/mips/mips/softintr.c
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# The autoconfiguration root.
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device mainbus { [addr = -1] }
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@ -1,4 +1,4 @@
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/* $NetBSD: gdium_dma.c,v 1.2 2009/08/06 16:37:01 matt Exp $ */
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/* $NetBSD: gdium_dma.c,v 1.3 2011/06/08 17:47:48 bouyer Exp $ */
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/*-
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* Copyright (c) 2001 The NetBSD Foundation, Inc.
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@ -34,7 +34,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: gdium_dma.c,v 1.2 2009/08/06 16:37:01 matt Exp $");
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__KERNEL_RCSID(0, "$NetBSD: gdium_dma.c,v 1.3 2011/06/08 17:47:48 bouyer Exp $");
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#include <sys/param.h>
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@ -55,20 +55,9 @@ gdium_dma_init(struct gdium_config *gc)
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t = &gc->gc_pci_dmat;
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t->_cookie = gc;
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t->_wbase = GDIUM_DMA_PCI_PCIBASE;
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t->_physbase = GDIUM_DMA_PCI_PHYSBASE;
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t->_wsize = GDIUM_DMA_PCI_SIZE;
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t->_dmamap_create = _bus_dmamap_create;
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t->_dmamap_destroy = _bus_dmamap_destroy;
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t->_dmamap_load = _bus_dmamap_load;
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t->_dmamap_load_mbuf = _bus_dmamap_load_mbuf;
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t->_dmamap_load_uio = _bus_dmamap_load_uio;
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t->_dmamap_load_raw = _bus_dmamap_load_raw;
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t->_dmamap_unload = _bus_dmamap_unload;
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t->_dmamap_sync = _bus_dmamap_sync;
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t->_dmamem_alloc = _bus_dmamem_alloc;
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t->_dmamem_free = _bus_dmamem_free;
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t->_dmamem_map = _bus_dmamem_map;
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t->_dmamem_unmap = _bus_dmamem_unmap;
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t->_dmamem_mmap = _bus_dmamem_mmap;
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t->_bounce_alloc_lo = GDIUM_DMA_PCI_PHYSBASE;
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t->_bounce_alloc_hi = GDIUM_DMA_PCI_PHYSBASE + GDIUM_DMA_PCI_SIZE;
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t->_dmamap_ops = mips_bus_dmamap_ops;
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t->_dmamem_ops = mips_bus_dmamem_ops;
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t->_dmatag_ops = mips_bus_dmatag_ops;
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}
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@ -1,4 +1,4 @@
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/* $NetBSD: gdium_intr.c,v 1.2 2009/08/07 01:27:14 matt Exp $ */
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/* $NetBSD: gdium_intr.c,v 1.3 2011/06/08 17:47:48 bouyer Exp $ */
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/*-
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* Copyright (c) 2001 The NetBSD Foundation, Inc.
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@ -37,7 +37,10 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: gdium_intr.c,v 1.2 2009/08/07 01:27:14 matt Exp $");
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__KERNEL_RCSID(0, "$NetBSD: gdium_intr.c,v 1.3 2011/06/08 17:47:48 bouyer Exp $");
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#define __INTR_PRIVATE
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#include "opt_ddb.h"
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@ -129,7 +132,7 @@ struct gdium_cpuintr {
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};
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struct gdium_cpuintr gdium_cpuintrs[NINTRS];
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const char *gdium_cpuintrnames[NINTRS] = {
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const char * const gdium_cpuintrnames[NINTRS] = {
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"int 0 (pci)",
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"int 1 (errors)",
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};
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@ -138,20 +141,11 @@ const char *gdium_cpuintrnames[NINTRS] = {
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* This is a mask of bits to clear in the SR when we go to a
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* given hardware interrupt priority level.
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*/
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const uint32_t ipl_sr_bits[_IPL_N] = {
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[IPL_NONE] = 0,
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[IPL_SOFTCLOCK] =
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MIPS_SOFT_INT_MASK_0,
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#if IPL_SOFTCLOCK != IPL_SOFTBIO
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[IPL_SOFTBIO] =
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MIPS_SOFT_INT_MASK_0,
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#endif
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[IPL_SOFTNET] =
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MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1,
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#if IPL_SOFTNET != IPL_SOFTSERIAL
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[IPL_SOFTSERIAL] =
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MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1,
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#endif
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static const struct ipl_sr_map gdium_ipl_sr_map = {
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.sr_bits = {
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[IPL_NONE] = 0,
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[IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
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[IPL_SOFTNET] = MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1,
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[IPL_VM] =
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MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1 |
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MIPS_INT_MASK_0 |
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@ -167,25 +161,12 @@ const uint32_t ipl_sr_bits[_IPL_N] = {
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MIPS_INT_MASK_3 |
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MIPS_INT_MASK_4 |
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MIPS_INT_MASK_5,
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[IPL_DDB] = MIPS_INT_MASK,
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[IPL_HIGH] = MIPS_INT_MASK,
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},
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};
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/*
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* This is a mask of bits to clear in the SR when we go to a
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* given software interrupt priority level.
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* Hardware ipls are port/board specific.
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*/
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const uint32_t mips_ipl_si_to_sr[] = {
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[IPL_SOFTCLOCK-IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
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#if IPL_SOFTCLOCK != IPL_SOFTBIO
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[IPL_SOFTBIO-IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
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#endif
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[IPL_SOFTNET-IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_1,
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#if IPL_SOFTNET != IPL_SOFTSERIAL
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[IPL_SOFTSERIAL-IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_1,
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#endif
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};
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int gdium_pci_intr_map(struct pci_attach_args *, pci_intr_handle_t *);
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int gdium_pci_intr_map(const struct pci_attach_args *, pci_intr_handle_t *);
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const char *gdium_pci_intr_string(void *, pci_intr_handle_t);
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const struct evcnt *gdium_pci_intr_evcnt(void *, pci_intr_handle_t);
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void *gdium_pci_intr_establish(void *, pci_intr_handle_t, int,
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@ -196,11 +177,13 @@ void gdium_pci_conf_interrupt(void *, int, int, int, int, int *);
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void
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evbmips_intr_init(void)
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{
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struct gdium_config *gc = &gdium_configuration;
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struct gdium_config * const gc = &gdium_configuration;
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struct bonito_config *bc = &gc->gc_bonito;
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const struct gdium_irqmap *irqmap;
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uint32_t intbit;
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int i;
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size_t i;
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ipl_sr_map = gdium_ipl_sr_map;
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for (i = 0; i < NINTRS; i++) {
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LIST_INIT(&gdium_cpuintrs[i].cintr_list);
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@ -316,8 +299,7 @@ evbmips_intr_disestablish(void *cookie)
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}
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void
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evbmips_iointr(uint32_t status, uint32_t cause, uint32_t pc,
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uint32_t ipending)
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evbmips_iointr(int ipl, vaddr_t pc, uint32_t ipending)
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{
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const struct gdium_irqmap *irqmap;
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struct evbmips_intrhand *ih;
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@ -341,11 +323,7 @@ evbmips_iointr(uint32_t status, uint32_t cause, uint32_t pc,
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(*ih->ih_func)(ih->ih_arg);
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}
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}
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cause &= ~(MIPS_INT_MASK_0 << level);
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}
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/* Re-enable anything that we have processed. */
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_splset(MIPS_SR_INT_IE | ((status & ~cause) & MIPS_HARD_INT_MASK));
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}
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/*****************************************************************************
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@ -353,7 +331,7 @@ evbmips_iointr(uint32_t status, uint32_t cause, uint32_t pc,
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*****************************************************************************/
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int
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gdium_pci_intr_map(struct pci_attach_args *pa,
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gdium_pci_intr_map(const struct pci_attach_args *pa,
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pci_intr_handle_t *ihp)
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{
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static const int8_t pciirqmap[5/*device*/] = {
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@ -1,4 +1,4 @@
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/* $NetBSD: machdep.c,v 1.13 2011/02/20 07:48:34 matt Exp $ */
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/* $NetBSD: machdep.c,v 1.14 2011/06/08 17:47:48 bouyer Exp $ */
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/*
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* Copyright 2001, 2002 Wasabi Systems, Inc.
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@ -74,7 +74,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.13 2011/02/20 07:48:34 matt Exp $");
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__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.14 2011/06/08 17:47:48 bouyer Exp $");
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#include "opt_ddb.h"
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#include "opt_execfmt.h"
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@ -106,6 +106,8 @@ __KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.13 2011/02/20 07:48:34 matt Exp $");
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#include <machine/cpu.h>
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#include <machine/psl.h>
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#include <mips/locore.h>
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#include <mips/bonito/bonitoreg.h>
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#include <evbmips/gdium/gdiumvar.h>
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@ -126,9 +128,6 @@ struct gdium_config gdium_configuration = {
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/* For sysctl_hw. */
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extern char cpu_model[];
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/* Our exported CPU info; we can have only one. */
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struct cpu_info cpu_info_store;
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/* Maps for VM objects. */
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struct vm_map *phys_map = NULL;
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@ -200,9 +199,6 @@ mach_init(int argc, char **argv, char **envp, void *callvec)
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{
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struct gdium_config *gc = &gdium_configuration;
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void *kernend;
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u_long first, last;
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struct pcb *pcb0;
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vaddr_t v;
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#ifdef NOTYET
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char *cp;
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int howto;
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@ -225,7 +221,7 @@ mach_init(int argc, char **argv, char **envp, void *callvec)
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* first printf() after that is called).
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* Also clears the I+D caches.
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*/
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mips_vector_init(NULL, bool);
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mips_vector_init(NULL, false);
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/* set the VM page size */
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uvm_setpagesize();
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@ -261,7 +257,7 @@ mach_init(int argc, char **argv, char **envp, void *callvec)
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}
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}
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if (mips_cpu_flags & CPU_MIPS_DOUBLE_COUNT)
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if (mips_options.mips_cpu_flags & CPU_MIPS_DOUBLE_COUNT)
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curcpu()->ci_cpu_freq /= 2;
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/* Compute the number of ticks for hz. */
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@ -275,7 +271,7 @@ mach_init(int argc, char **argv, char **envp, void *callvec)
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* Get correct cpu frequency if the CPU runs at twice the
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* external/cp0-count frequency.
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*/
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if (mips_cpu_flags & CPU_MIPS_DOUBLE_COUNT)
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if (mips_options.mips_cpu_flags & CPU_MIPS_DOUBLE_COUNT)
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curcpu()->ci_cpu_freq *= 2;
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#ifdef DEBUG
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@ -330,10 +326,8 @@ mach_init(int argc, char **argv, char **envp, void *callvec)
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/*
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* Load the rest of the available pages into the VM system.
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*/
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first = round_page(MIPS_KSEG0_TO_PHYS(kernend));
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last = mem_clusters[0].start + mem_clusters[0].size;
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uvm_page_physload(atop(first), atop(last), atop(first), atop(last),
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VM_FREELIST_DEFAULT);
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mips_page_physload(MIPS_KSEG0_START, (vaddr_t)kernend,
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mem_clusters, mem_cluster_cnt, NULL, 0);
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/*
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* Initialize error message buffer (at end of core).
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@ -345,13 +339,7 @@ mach_init(int argc, char **argv, char **envp, void *callvec)
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/*
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* Allocate uarea page for lwp0 and set it.
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*/
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v = uvm_pageboot_alloc(USPACE);
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uvm_lwp_setuarea(&lwp0, v);
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pcb0 = lwp_getpcb(&lwp0);
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pcb0->pcb_context[11] = MIPS_INT_MASK | MIPS_SR_INT_IE; /* SR */
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lwp0.l_md.md_regs = (struct frame *)(v + USPACE) - 1;
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mips_init_lwp0_uarea();
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/*
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* Initialize debuggers, and break into them, if appropriate.
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@ -378,15 +366,10 @@ consinit(void)
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void
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cpu_startup(void)
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{
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vaddr_t minaddr, maxaddr;
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char pbuf[9];
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/*
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* Good {morning,afternoon,evening,night}.
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* Do the common startup items.
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*/
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printf("%s%s", copyright, version);
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format_bytes(pbuf, sizeof(pbuf), ctob(physmem));
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printf("total memory = %s\n", pbuf);
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cpu_startup_common();
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/*
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* Virtual memory is bootstrapped -- notify the bus spaces
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@ -394,21 +377,6 @@ cpu_startup(void)
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*/
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gdium_configuration.gc_mallocsafe = 1;
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minaddr = 0;
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/*
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* Allocate a submap for physio.
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*/
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phys_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr,
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VM_PHYS_SIZE, 0, FALSE, NULL);
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/*
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* (No need to allocate an mbuf cluster submap. Mbuf clusters
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* are allocated via the pool allocator, and we use KSEG to
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* map those pages.)
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*/
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format_bytes(pbuf, sizeof(pbuf), ptoa(uvmexp.free));
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printf("avail memory = %s\n", pbuf);
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}
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int waittime = -1;
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@ -418,8 +386,7 @@ cpu_reboot(int howto, char *bootstr)
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{
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/* Take a snapshot before clobbering any registers. */
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if (curproc)
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savectx(curpcb);
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savectx(curpcb);
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if (cold) {
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howto |= RB_HALT;
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@ -1,4 +1,4 @@
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/* $NetBSD: cache.c,v 1.46 2011/03/15 07:39:22 matt Exp $ */
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/* $NetBSD: cache.c,v 1.47 2011/06/08 17:47:48 bouyer Exp $ */
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/*
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* Copyright 2001, 2002 Wasabi Systems, Inc.
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@ -68,7 +68,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: cache.c,v 1.46 2011/03/15 07:39:22 matt Exp $");
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__KERNEL_RCSID(0, "$NetBSD: cache.c,v 1.47 2011/06/08 17:47:48 bouyer Exp $");
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#include "opt_cputype.h"
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#include "opt_mips_cache.h"
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@ -586,40 +586,40 @@ primary_cache_is_2way:
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#endif /* ENABLE_MIPS4_CACHE_R10K */
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#ifdef MIPS3_LOONGSON2
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case MIPS_LOONGSON2:
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mips_picache_ways = 4;
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mips_pdcache_ways = 4;
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mci->mci_picache_ways = 4;
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mci->mci_pdcache_ways = 4;
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mips3_get_cache_config(csizebase);
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mips_sdcache_line_size = 32; /* don't trust config reg */
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mci->mci_sdcache_line_size = 32; /* don't trust config reg */
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if (mips_picache_size / mips_picache_ways > PAGE_SIZE ||
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mips_pdcache_size / mips_pdcache_ways > PAGE_SIZE)
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mips_cache_virtual_alias = 1;
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if (mci->mci_picache_size / mci->mci_picache_ways > PAGE_SIZE ||
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mci->mci_pdcache_size / mci->mci_pdcache_ways > PAGE_SIZE)
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mci->mci_cache_virtual_alias = 1;
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mips_cache_ops.mco_icache_sync_all =
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mco->mco_icache_sync_all =
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ls2_icache_sync_all;
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mips_cache_ops.mco_icache_sync_range =
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mco->mco_icache_sync_range =
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ls2_icache_sync_range;
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mips_cache_ops.mco_icache_sync_range_index =
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mco->mco_icache_sync_range_index =
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ls2_icache_sync_range_index;
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mips_cache_ops.mco_pdcache_wbinv_all =
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mco->mco_pdcache_wbinv_all =
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ls2_pdcache_wbinv_all;
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mips_cache_ops.mco_pdcache_wbinv_range =
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mco->mco_pdcache_wbinv_range =
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ls2_pdcache_wbinv_range;
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mips_cache_ops.mco_pdcache_wbinv_range_index =
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mco->mco_pdcache_wbinv_range_index =
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ls2_pdcache_wbinv_range_index;
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mips_cache_ops.mco_pdcache_inv_range =
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mco->mco_pdcache_inv_range =
|
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ls2_pdcache_inv_range;
|
||||
mips_cache_ops.mco_pdcache_wb_range =
|
||||
mco->mco_pdcache_wb_range =
|
||||
ls2_pdcache_wb_range;
|
||||
|
||||
/*
|
||||
* For current version chips, [the] operating system is
|
||||
* obliged to eliminate the potential for virtual aliasing.
|
||||
*/
|
||||
uvmexp.ncolors = mips_pdcache_ways;
|
||||
uvmexp.ncolors = mci->mci_pdcache_ways;
|
||||
break;
|
||||
#endif
|
||||
#endif /* MIPS3 || MIPS4 */
|
||||
@ -768,19 +768,19 @@ primary_cache_is_2way:
|
||||
#endif /* ENABLE_MIPS4_CACHE_R10K */
|
||||
#ifdef MIPS3_LOONGSON2
|
||||
case MIPS_LOONGSON2:
|
||||
mips_sdcache_ways = 4;
|
||||
mips_sdcache_size = 512*1024;
|
||||
mips_scache_unified = 1;
|
||||
mci->mci_sdcache_ways = 4;
|
||||
mci->mci_sdcache_size = 512*1024;
|
||||
mci->mci_scache_unified = 1;
|
||||
|
||||
mips_cache_ops.mco_sdcache_wbinv_all =
|
||||
mco->mco_sdcache_wbinv_all =
|
||||
ls2_sdcache_wbinv_all;
|
||||
mips_cache_ops.mco_sdcache_wbinv_range =
|
||||
mco->mco_sdcache_wbinv_range =
|
||||
ls2_sdcache_wbinv_range;
|
||||
mips_cache_ops.mco_sdcache_wbinv_range_index =
|
||||
mco->mco_sdcache_wbinv_range_index =
|
||||
ls2_sdcache_wbinv_range_index;
|
||||
mips_cache_ops.mco_sdcache_inv_range =
|
||||
mco->mco_sdcache_inv_range =
|
||||
ls2_sdcache_inv_range;
|
||||
mips_cache_ops.mco_sdcache_wb_range =
|
||||
mco->mco_sdcache_wb_range =
|
||||
ls2_sdcache_wb_range;
|
||||
|
||||
/*
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: cache_ls2.c,v 1.3 2009/08/11 00:34:29 matt Exp $ */
|
||||
/* $NetBSD: cache_ls2.c,v 1.4 2011/06/08 17:47:48 bouyer Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 2009 The NetBSD Foundation, Inc.
|
||||
@ -30,7 +30,7 @@
|
||||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__KERNEL_RCSID(0, "$NetBSD: cache_ls2.c,v 1.3 2009/08/11 00:34:29 matt Exp $");
|
||||
__KERNEL_RCSID(0, "$NetBSD: cache_ls2.c,v 1.4 2011/06/08 17:47:48 bouyer Exp $");
|
||||
|
||||
#include <sys/param.h>
|
||||
|
||||
@ -55,11 +55,12 @@ __asm(".set mips3");
|
||||
void
|
||||
ls2_icache_sync_range(vaddr_t va, vsize_t size)
|
||||
{
|
||||
struct mips_cache_info * const mci = &mips_cache_info;
|
||||
const vaddr_t eva = round_line(va + size);
|
||||
|
||||
va = trunc_line(va);
|
||||
|
||||
if (va + mips_picache_size <= eva) {
|
||||
if (va + mci->mci_picache_size <= eva) {
|
||||
ls2_icache_sync_all();
|
||||
return;
|
||||
}
|
||||
@ -81,6 +82,7 @@ void
|
||||
ls2_icache_sync_range_index(vaddr_t va, vsize_t size)
|
||||
{
|
||||
vaddr_t eva;
|
||||
struct mips_cache_info * const mci = &mips_cache_info;
|
||||
|
||||
/*
|
||||
* Since we're doing Index ops, we expect to not be able
|
||||
@ -89,13 +91,13 @@ ls2_icache_sync_range_index(vaddr_t va, vsize_t size)
|
||||
* address out of them.
|
||||
*/
|
||||
|
||||
va = MIPS_PHYS_TO_KSEG0(va & mips_picache_way_mask);
|
||||
va = MIPS_PHYS_TO_KSEG0(va & mci->mci_picache_way_mask);
|
||||
eva = round_line(va + size);
|
||||
va = trunc_line(va);
|
||||
|
||||
if (va + mips_picache_way_size < eva) {
|
||||
if (va + mci->mci_picache_way_size < eva) {
|
||||
va = MIPS_PHYS_TO_KSEG0(0);
|
||||
eva = mips_picache_way_size;
|
||||
eva = mci->mci_picache_way_size;
|
||||
}
|
||||
|
||||
for (; va + 8 * 32 <= eva; va += 8 * 32) {
|
||||
@ -114,7 +116,8 @@ ls2_icache_sync_range_index(vaddr_t va, vsize_t size)
|
||||
void
|
||||
ls2_icache_sync_all(void)
|
||||
{
|
||||
ls2_icache_sync_range_index(0, mips_picache_way_size);
|
||||
struct mips_cache_info * const mci = &mips_cache_info;
|
||||
ls2_icache_sync_range_index(0, mci->mci_picache_way_size);
|
||||
}
|
||||
|
||||
void
|
||||
@ -166,6 +169,7 @@ void
|
||||
ls2_pdcache_wbinv_range_index(vaddr_t va, vsize_t size)
|
||||
{
|
||||
vaddr_t eva;
|
||||
struct mips_cache_info * const mci = &mips_cache_info;
|
||||
|
||||
/*
|
||||
* Since we're doing Index ops, we expect to not be able
|
||||
@ -173,14 +177,14 @@ ls2_pdcache_wbinv_range_index(vaddr_t va, vsize_t size)
|
||||
* bits that determine the cache index, and make a KSEG0
|
||||
* address out of them.
|
||||
*/
|
||||
va = MIPS_PHYS_TO_KSEG0(va & mips_pdcache_way_mask);
|
||||
va = MIPS_PHYS_TO_KSEG0(va & mci->mci_pdcache_way_mask);
|
||||
|
||||
eva = round_line(va + size);
|
||||
va = trunc_line(va);
|
||||
|
||||
if (va + mips_pdcache_way_size > eva) {
|
||||
if (va + mci->mci_pdcache_way_size > eva) {
|
||||
va = MIPS_PHYS_TO_KSEG0(0);
|
||||
eva = mips_pdcache_way_size;
|
||||
eva = mci->mci_pdcache_way_size;
|
||||
}
|
||||
|
||||
for (; va + 8 * 32 <= eva; va += 8 * 32) {
|
||||
@ -197,7 +201,8 @@ ls2_pdcache_wbinv_range_index(vaddr_t va, vsize_t size)
|
||||
void
|
||||
ls2_pdcache_wbinv_all(void)
|
||||
{
|
||||
ls2_pdcache_wbinv_range_index(0, mips_pdcache_way_size);
|
||||
struct mips_cache_info * const mci = &mips_cache_info;
|
||||
ls2_pdcache_wbinv_range_index(0, mci->mci_pdcache_way_size);
|
||||
}
|
||||
|
||||
/*
|
||||
@ -262,6 +267,7 @@ void
|
||||
ls2_sdcache_wbinv_range_index(vaddr_t va, vsize_t size)
|
||||
{
|
||||
vaddr_t eva;
|
||||
struct mips_cache_info * const mci = &mips_cache_info;
|
||||
|
||||
/*
|
||||
* Since we're doing Index ops, we expect to not be able
|
||||
@ -269,14 +275,14 @@ ls2_sdcache_wbinv_range_index(vaddr_t va, vsize_t size)
|
||||
* bits that determine the cache index, and make a KSEG0
|
||||
* address out of them.
|
||||
*/
|
||||
va = MIPS_PHYS_TO_KSEG0(va & mips_sdcache_way_mask);
|
||||
va = MIPS_PHYS_TO_KSEG0(va & mci->mci_sdcache_way_mask);
|
||||
|
||||
eva = round_line(va + size);
|
||||
va = trunc_line(va);
|
||||
|
||||
if (va + mips_sdcache_way_size > eva) {
|
||||
if (va + mci->mci_sdcache_way_size > eva) {
|
||||
va = MIPS_PHYS_TO_KSEG0(0);
|
||||
eva = va + mips_sdcache_way_size;
|
||||
eva = va + mci->mci_sdcache_way_size;
|
||||
}
|
||||
|
||||
for (; va + 8 * 32 <= eva; va += 8 * 32) {
|
||||
@ -295,5 +301,6 @@ ls2_sdcache_wbinv_range_index(vaddr_t va, vsize_t size)
|
||||
void
|
||||
ls2_sdcache_wbinv_all(void)
|
||||
{
|
||||
ls2_sdcache_wbinv_range_index(0, mips_sdcache_way_size);
|
||||
struct mips_cache_info * const mci = &mips_cache_info;
|
||||
ls2_sdcache_wbinv_range_index(0, mci->mci_sdcache_way_size);
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user