A driver for I2C modules found in TI Sitara SoCs. Should also work
for some OMAP4 CPUs with little work.
This commit is contained in:
bouyer
parent
654699b334
commit
3a9336e624
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@ -0,0 +1,603 @@
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/* $NetBSD: ti_iic.c,v 1.1 2013/04/17 14:33:06 bouyer Exp $ */
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/*
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* Copyright (c) 2013 Manuel Bouyer. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*-
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* Copyright (c) 2012 Jared D. McNeill <jmcneill@invisible.ca>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: ti_iic.c,v 1.1 2013/04/17 14:33:06 bouyer Exp $");
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#include "opt_omap.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <sys/conf.h>
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#include <sys/bus.h>
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#include <sys/proc.h>
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#include <sys/kernel.h>
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#include <sys/mutex.h>
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#include <dev/i2c/i2cvar.h>
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#include <arm/omap/omap2_obiovar.h>
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#include <arm/omap/omap2_reg.h>
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#include <arm/omap/ti_iicreg.h>
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#ifdef TI_AM335X
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# include <arm/omap/am335x_prcm.h>
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# include <arm/omap/omap2_prcm.h>
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# include <arm/omap/sitara_cm.h>
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# include <arm/omap/sitara_cmreg.h>
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#endif
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#ifndef OMAP2_I2C_SLAVE_ADDR
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#define OMAP2_I2C_SLAVE_ADDR 0x01
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#endif
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#ifdef I2CDEBUG
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#define DPRINTF(args) printf args
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#else
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#define DPRINTF(args)
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#endif
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struct ti_iic_softc {
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device_t sc_dev;
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struct i2c_controller sc_ic;
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kmutex_t sc_lock;
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device_t sc_i2cdev;
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bus_space_tag_t sc_iot;
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bus_space_handle_t sc_ioh;
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int sc_rxthres;
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int sc_txthres;
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};
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#define I2C_READ_REG(sc, reg) \
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bus_space_read_2((sc)->sc_iot, (sc)->sc_ioh, (reg))
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#define I2C_READ_DATA(sc) \
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bus_space_read_1((sc)->sc_iot, (sc)->sc_ioh, OMAP2_I2C_DATA);
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#define I2C_WRITE_REG(sc, reg, val) \
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bus_space_write_2((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
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#define I2C_WRITE_DATA(sc, val) \
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bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, OMAP2_I2C_DATA, (val))
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static int ti_iic_match(device_t, cfdata_t, void *);
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static void ti_iic_attach(device_t, device_t, void *);
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static int ti_iic_rescan(device_t, const char *, const int *);
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static void ti_iic_childdet(device_t, device_t);
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static int ti_iic_acquire_bus(void *, int);
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static void ti_iic_release_bus(void *, int);
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static int ti_iic_exec(void *, i2c_op_t, i2c_addr_t, const void *,
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size_t, void *, size_t, int);
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static int ti_iic_reset(struct ti_iic_softc *);
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static int ti_iic_read(struct ti_iic_softc *, i2c_addr_t,
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uint8_t *, size_t, int);
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static int ti_iic_write(struct ti_iic_softc *, i2c_addr_t,
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const uint8_t *, size_t, int);
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static int ti_iic_wait(struct ti_iic_softc *, uint16_t, uint16_t);
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static int ti_iic_stat(struct ti_iic_softc *);
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static int ti_iic_flush(struct ti_iic_softc *);
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i2c_tag_t ti_iic_get_tag(device_t);
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#ifdef TI_AM335X
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struct am335x_iic {
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const char *as_name;
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bus_addr_t as_base_addr;
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int as_intr;
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struct omap_module as_module;
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};
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static const struct am335x_iic am335x_iic[] = {
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{ "I2C0", OMAP2_I2C0_BASE, 70, { AM335X_PRCM_CM_WKUP, 0xb8 } },
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{ "I2C1", OMAP2_I2C1_BASE, 71, { AM335X_PRCM_CM_PER, 0x48 } },
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{ "I2C2", OMAP2_I2C1_BASE, 30, { AM335X_PRCM_CM_PER, 0x44 } },
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};
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#endif
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CFATTACH_DECL2_NEW(ti_iic, sizeof(struct ti_iic_softc),
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ti_iic_match, ti_iic_attach, NULL, NULL,
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ti_iic_rescan, ti_iic_childdet);
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static int
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ti_iic_match(device_t parent, cfdata_t match, void *opaque)
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{
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struct obio_attach_args *obio = opaque;
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#if defined(TI_AM335X)
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if (obio->obio_addr == OMAP2_I2C0_BASE ||
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obio->obio_addr == OMAP2_I2C1_BASE ||
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obio->obio_addr == OMAP2_I2C2_BASE)
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return 1;
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#endif
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return 0;
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}
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static void
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ti_iic_attach(device_t parent, device_t self, void *opaque)
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{
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struct ti_iic_softc *sc = device_private(self);
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struct obio_attach_args *obio = opaque;
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uint16_t rev;
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#ifdef TI_AM335X
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int i;
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const char *mode;
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u_int state;
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#endif
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aprint_naive("\n");
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sc->sc_dev = self;
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sc->sc_iot = obio->obio_iot;
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mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_NONE);
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sc->sc_ic.ic_cookie = sc;
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sc->sc_ic.ic_acquire_bus = ti_iic_acquire_bus;
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sc->sc_ic.ic_release_bus = ti_iic_release_bus;
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sc->sc_ic.ic_exec = ti_iic_exec;
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sc->sc_rxthres = sc->sc_txthres = 4;
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if (bus_space_map(obio->obio_iot, obio->obio_addr, obio->obio_size,
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0, &sc->sc_ioh) != 0) {
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aprint_error(": couldn't map address space\n");
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return;
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}
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#ifdef TI_AM335X
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for (i = 0; i < __arraycount(am335x_iic); i++) {
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if ((obio->obio_addr == am335x_iic[i].as_base_addr) &&
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(obio->obio_intr == am335x_iic[i].as_intr)) {
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prcm_module_enable(&am335x_iic[i].as_module);
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break;
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}
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}
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KASSERT(i < __arraycount(am335x_iic));
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if (sitara_cm_padconf_get("I2C0_SDA", &mode, &state) == 0) {
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aprint_debug(": SDA mode %s state %d ", mode, state);
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}
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if (sitara_cm_padconf_get("I2C0_SCL", &mode, &state) == 0) {
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aprint_debug(": SCL mode %s state %d ", mode, state);
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}
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if (sitara_cm_padconf_set("I2C0_SDA", "I2C0_SDA",
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(0x01 << 4) | (0x01 << 5) | (0x01 << 6)) != 0) {
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aprint_error(": can't switch SDA pad\n");
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return;
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}
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if (sitara_cm_padconf_set("I2C0_SCL", "I2C0_SCL",
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(0x01 << 4) | (0x01 << 5) | (0x01 << 6)) != 0) {
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aprint_error(": can't switch SCL pad\n");
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return;
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}
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#endif
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rev = I2C_READ_REG(sc, OMAP2_I2C_REVNB_LO);
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aprint_normal(": rev %d.%d\n",
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(int)I2C_REVNB_LO_MAJOR(rev),
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(int)I2C_REVNB_LO_MINOR(rev));
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ti_iic_reset(sc);
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ti_iic_flush(sc);
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ti_iic_rescan(self, NULL, NULL);
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}
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static int
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ti_iic_rescan(device_t self, const char *ifattr, const int *locs)
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{
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struct ti_iic_softc *sc = device_private(self);
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struct i2cbus_attach_args iba;
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if (ifattr_match(ifattr, "i2cbus") && sc->sc_i2cdev == NULL) {
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memset(&iba, 0, sizeof(iba));
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iba.iba_tag = &sc->sc_ic;
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sc->sc_i2cdev = config_found_ia(self, "i2cbus",
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&iba, iicbus_print);
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}
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return 0;
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}
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static void
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ti_iic_childdet(device_t self, device_t child)
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{
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struct ti_iic_softc *sc = device_private(self);
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if (sc->sc_i2cdev == child)
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sc->sc_i2cdev = NULL;
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}
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static int
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ti_iic_acquire_bus(void *opaque, int flags)
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{
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struct ti_iic_softc *sc = opaque;
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if (flags & I2C_F_POLL) {
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if (!mutex_tryenter(&sc->sc_lock))
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return EBUSY;
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} else {
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mutex_enter(&sc->sc_lock);
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}
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return 0;
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}
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static void
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ti_iic_release_bus(void *opaque, int flags)
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{
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struct ti_iic_softc *sc = opaque;
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mutex_exit(&sc->sc_lock);
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}
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static int
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ti_iic_exec(void *opaque, i2c_op_t op, i2c_addr_t addr,
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const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags)
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{
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struct ti_iic_softc *sc = opaque;
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int err;
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DPRINTF(("ti_iic_exec: op 0x%x cmdlen %zd len %zd flags 0x%x\n",
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op, cmdlen, len, flags));
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if (cmdlen > 0) {
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err = ti_iic_write(sc, addr, cmdbuf, cmdlen,
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I2C_OP_READ_P(op) ? 0 : I2C_F_STOP);
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if (err)
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goto done;
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}
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if (I2C_OP_STOP_P(op))
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flags |= I2C_F_STOP;
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/*
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* I2C controller doesn't allow for zero-byte transfers.
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*/
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if (len == 0) {
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err = EINVAL;
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goto done;
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}
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if (I2C_OP_READ_P(op)) {
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err = ti_iic_read(sc, addr, buf, len, flags);
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} else {
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err = ti_iic_write(sc, addr, buf, len, flags);
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}
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done:
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if (err)
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ti_iic_reset(sc);
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ti_iic_flush(sc);
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DPRINTF(("ti_iic_exec: done %d\n", err));
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return err;
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}
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static int
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ti_iic_reset(struct ti_iic_softc *sc)
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{
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uint32_t psc, scll, sclh;
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int i;
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/* Disable */
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I2C_WRITE_REG(sc, OMAP2_I2C_CON, 0);
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/* Soft reset */
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I2C_WRITE_REG(sc, OMAP2_I2C_SYSC, I2C_SYSC_SRST);
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delay(1000);
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/* enable so that we can check for reset complete */
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I2C_WRITE_REG(sc, OMAP2_I2C_CON, I2C_CON_EN);
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delay(1000);
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for (i = 0; i < 1000; i++) { /* 1s delay for reset */
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if (I2C_READ_REG(sc, OMAP2_I2C_SYSS) & I2C_SYSS_RDONE)
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break;
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}
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/* Disable again */
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I2C_WRITE_REG(sc, OMAP2_I2C_CON, 0);
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delay(50000);
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if (i >= 1000) {
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aprint_error_dev(sc->sc_dev, ": couldn't reset module\n");
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return 1;
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}
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/* XXX standard speed only */
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psc = 3;
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scll = 53;
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sclh = 55;
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/* Clocks */
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I2C_WRITE_REG(sc, OMAP2_I2C_PSC, psc);
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I2C_WRITE_REG(sc, OMAP2_I2C_SCLL, scll);
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I2C_WRITE_REG(sc, OMAP2_I2C_SCLH, sclh);
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/* Own I2C address */
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I2C_WRITE_REG(sc, OMAP2_I2C_OA, OMAP2_I2C_SLAVE_ADDR);
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/* 5 bytes fifo */
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I2C_WRITE_REG(sc, OMAP2_I2C_BUF,
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I2C_BUF_RXTRSH(sc->sc_rxthres) | I2C_BUF_TXTRSH(sc->sc_txthres));
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/* Enable */
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I2C_WRITE_REG(sc, OMAP2_I2C_CON, I2C_CON_EN);
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return 0;
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}
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static int
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ti_iic_read(struct ti_iic_softc *sc, i2c_addr_t addr, uint8_t *buf,
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size_t buflen, int flags)
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{
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uint16_t con, stat;
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int err, i, retry;
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size_t len;
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err = ti_iic_wait(sc, I2C_IRQSTATUS_BB, 0);
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if (err) {
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DPRINTF(("ti_iic_read: wait error %d\n", err));
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return err;
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}
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con = I2C_CON_EN;
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con |= I2C_CON_MST;
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con |= I2C_CON_STT;;
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if (flags & I2C_F_STOP)
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con |= I2C_CON_STP;
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if (addr & ~0x7f)
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con |= I2C_CON_XSA;
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I2C_WRITE_REG(sc, OMAP2_I2C_CON, I2C_CON_EN | I2C_CON_MST | I2C_CON_STP);
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DPRINTF(("ti_iic_read: con 0x%x ", con));
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I2C_WRITE_REG(sc, OMAP2_I2C_CNT, buflen);
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I2C_WRITE_REG(sc, OMAP2_I2C_SA, (addr & I2C_SA_MASK));
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DPRINTF(("SA 0x%x len %d\n", I2C_READ_REG(sc, OMAP2_I2C_SA), I2C_READ_REG(sc, OMAP2_I2C_CNT)));
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I2C_WRITE_REG(sc, OMAP2_I2C_CON, con);
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i = 0;
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while (1) {
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stat = ti_iic_stat(sc);
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DPRINTF(("ti_iic_read stat 0x%x\n", stat));
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if (stat & (I2C_IRQSTATUS_NACK|I2C_IRQSTATUS_AL)) {
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err = EIO;
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break;
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}
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if (stat & I2C_IRQSTATUS_ARDY) {
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err = 0;
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break;
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}
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if (stat & I2C_IRQSTATUS_RDR) {
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len = I2C_READ_REG(sc, OMAP2_I2C_BUFSTAT);
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len = I2C_BUFSTAT_RXSTAT(len);
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DPRINTF(("ti_iic_read receive drain len %zd left %d\n",
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len, I2C_READ_REG(sc, OMAP2_I2C_CNT)));
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} else if (stat & I2C_IRQSTATUS_RRDY) {
|
||||
len = sc->sc_rxthres + 1;
|
||||
DPRINTF(("ti_iic_read receive len %zd left %d\n",
|
||||
len, I2C_READ_REG(sc, OMAP2_I2C_CNT)));
|
||||
} else {
|
||||
DELAY(1);
|
||||
continue;
|
||||
}
|
||||
for (; i < buflen && len > 0; i++, len--) {
|
||||
buf[i] = I2C_READ_DATA(sc);
|
||||
DPRINTF(("ti_iic_read got b[%d]=0x%x\n",
|
||||
i, buf[i]));
|
||||
}
|
||||
I2C_WRITE_REG(sc, OMAP2_I2C_IRQSTATUS, stat);
|
||||
}
|
||||
|
||||
I2C_WRITE_REG(sc, OMAP2_I2C_IRQSTATUS, stat);
|
||||
retry = 10000;
|
||||
I2C_WRITE_REG(sc, OMAP2_I2C_CON, 0);
|
||||
while (I2C_READ_REG(sc, OMAP2_I2C_IRQSTATUS_RAW) ||
|
||||
(I2C_READ_REG(sc, OMAP2_I2C_CON) & I2C_CON_MST)) {
|
||||
delay(100);
|
||||
if (--retry == 0)
|
||||
break;
|
||||
}
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static int
|
||||
ti_iic_write(struct ti_iic_softc *sc, i2c_addr_t addr, const uint8_t *buf,
|
||||
size_t buflen, int flags)
|
||||
{
|
||||
uint16_t con, stat;
|
||||
int err, i, retry;
|
||||
size_t len;
|
||||
|
||||
err = ti_iic_wait(sc, I2C_IRQSTATUS_BB, 0);
|
||||
if (err) {
|
||||
DPRINTF(("ti_iic_write wait error %d\n", err));
|
||||
return err;
|
||||
}
|
||||
|
||||
con = I2C_CON_EN;
|
||||
con |= I2C_CON_MST;
|
||||
con |= I2C_CON_STT;
|
||||
if (flags & I2C_F_STOP)
|
||||
con |= I2C_CON_STP;
|
||||
con |= I2C_CON_TRX;
|
||||
if (addr & ~0x7f)
|
||||
con |= I2C_CON_XSA;
|
||||
|
||||
I2C_WRITE_REG(sc, OMAP2_I2C_CON, I2C_CON_EN | I2C_CON_MST | I2C_CON_STP);
|
||||
DPRINTF(("ti_iic_write: con 0x%x ", con));
|
||||
I2C_WRITE_REG(sc, OMAP2_I2C_SA, (addr & I2C_SA_MASK));
|
||||
I2C_WRITE_REG(sc, OMAP2_I2C_CNT, buflen);
|
||||
DPRINTF(("SA 0x%x len %d\n", I2C_READ_REG(sc, OMAP2_I2C_SA), I2C_READ_REG(sc, OMAP2_I2C_CNT)));
|
||||
I2C_WRITE_REG(sc, OMAP2_I2C_CON, con);
|
||||
|
||||
i = 0;
|
||||
while (1) {
|
||||
stat = ti_iic_stat(sc);
|
||||
DPRINTF(("ti_iic_write stat 0x%x\n", stat));
|
||||
if (stat & (I2C_IRQSTATUS_NACK|I2C_IRQSTATUS_AL)) {
|
||||
err = EIO;
|
||||
break;
|
||||
}
|
||||
if (stat & I2C_IRQSTATUS_ARDY) {
|
||||
err = 0;
|
||||
break;
|
||||
}
|
||||
|
||||
if (stat & I2C_IRQSTATUS_XDR) {
|
||||
len = I2C_READ_REG(sc, OMAP2_I2C_BUFSTAT);
|
||||
len = I2C_BUFSTAT_TXSTAT(len);
|
||||
DPRINTF(("ti_iic_write transmit drain len %zd left %d\n",
|
||||
len, I2C_READ_REG(sc, OMAP2_I2C_CNT)));
|
||||
} else if (stat & I2C_IRQSTATUS_XRDY) {
|
||||
len = sc->sc_txthres + 1;
|
||||
DPRINTF(("ti_iic_write transmit len %zd left %d\n",
|
||||
len, I2C_READ_REG(sc, OMAP2_I2C_CNT)));
|
||||
} else {
|
||||
DELAY(1);
|
||||
continue;
|
||||
}
|
||||
for (; i < buflen && len > 0; i++, len--) {
|
||||
DPRINTF(("ti_iic_write send b[%d]=0x%x\n",
|
||||
i, buf[i]));
|
||||
I2C_WRITE_DATA(sc, buf[i]);
|
||||
}
|
||||
I2C_WRITE_REG(sc, OMAP2_I2C_IRQSTATUS, stat);
|
||||
}
|
||||
|
||||
I2C_WRITE_REG(sc, OMAP2_I2C_IRQSTATUS, stat);
|
||||
retry = 10000;
|
||||
I2C_WRITE_REG(sc, OMAP2_I2C_CON, 0);
|
||||
while (I2C_READ_REG(sc, OMAP2_I2C_IRQSTATUS_RAW) ||
|
||||
(I2C_READ_REG(sc, OMAP2_I2C_CON) & I2C_CON_MST)) {
|
||||
delay(100);
|
||||
if (--retry == 0)
|
||||
break;
|
||||
}
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static int
|
||||
ti_iic_wait(struct ti_iic_softc *sc, uint16_t mask, uint16_t val)
|
||||
{
|
||||
int retry = 10;
|
||||
uint16_t v;
|
||||
|
||||
while (((v = I2C_READ_REG(sc, OMAP2_I2C_IRQSTATUS_RAW)) & mask) != val) {
|
||||
--retry;
|
||||
if (retry == 0) {
|
||||
aprint_error_dev(sc->sc_dev, ": wait timeout, "
|
||||
"mask = %#x val = %#x stat = %#x\n",
|
||||
mask, val, v);
|
||||
return EBUSY;
|
||||
}
|
||||
delay(50000);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
ti_iic_stat(struct ti_iic_softc *sc)
|
||||
{
|
||||
uint16_t v;
|
||||
int retry = 100;
|
||||
|
||||
while (--retry > 0) {
|
||||
v = I2C_READ_REG(sc, OMAP2_I2C_IRQSTATUS_RAW);
|
||||
if ((v & (I2C_IRQSTATUS_ROVR|I2C_IRQSTATUS_XUDF|
|
||||
I2C_IRQSTATUS_XDR|I2C_IRQSTATUS_RDR|
|
||||
I2C_IRQSTATUS_XRDY|I2C_IRQSTATUS_RRDY|
|
||||
I2C_IRQSTATUS_ARDY|I2C_IRQSTATUS_NACK|
|
||||
I2C_IRQSTATUS_AL)) != 0)
|
||||
break;
|
||||
delay(100);
|
||||
}
|
||||
|
||||
return v;
|
||||
}
|
||||
|
||||
static int
|
||||
ti_iic_flush(struct ti_iic_softc *sc)
|
||||
{
|
||||
#if 0
|
||||
int retry = 1000;
|
||||
uint16_t v;
|
||||
|
||||
while ((v = I2C_READ_REG(sc, OMAP2_I2C_IRQSTATUS_RAW)) & I2C_IRQSTATUS_RRDY) {
|
||||
if (--retry == 0) {
|
||||
aprint_error_dev(sc->sc_dev,
|
||||
": flush timeout, stat = %#x\n", v);
|
||||
return EBUSY;
|
||||
}
|
||||
(void)I2C_READ_DATA(sc);
|
||||
delay(1000);
|
||||
}
|
||||
#endif
|
||||
|
||||
I2C_WRITE_REG(sc, OMAP2_I2C_CNT, 0);
|
||||
return 0;
|
||||
}
|
||||
|
||||
i2c_tag_t
|
||||
ti_iic_get_tag(device_t dev)
|
||||
{
|
||||
struct ti_iic_softc *sc;
|
||||
|
||||
if (dev == NULL)
|
||||
return NULL;
|
||||
sc = device_private(dev);
|
||||
|
||||
return &sc->sc_ic;
|
||||
}
|
||||
|
|
@ -0,0 +1,141 @@
|
|||
/* $NetBSD: ti_iicreg.h,v 1.1 2013/04/17 14:33:06 bouyer Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2013 Manuel Bouyer. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/* register definitions for the i2c controller found in the
|
||||
* Texas Instrument AM335x SOC
|
||||
*/
|
||||
|
||||
#ifndef _OMAP2IICREG_H
|
||||
#define _OMAP2IICREG_H
|
||||
|
||||
#define OMAP2_I2C_REVNB_LO 0x00
|
||||
#define I2C_REVNB_LO_RTL(x) (((x) >> 11) & 0x01f)
|
||||
#define I2C_REVNB_LO_MAJOR(x) (((x) >> 8) & 0x007)
|
||||
#define I2C_REVNB_LO_CUSTOM(x) (((x) >> 6) & 0x003)
|
||||
#define I2C_REVNB_LO_MINOR(x) (((x) >> 0) & 0x01f)
|
||||
#define OMAP2_I2C_REVNB_HI 0x04
|
||||
#define I2C_REVNB_HI_SCHEME(x) (((x) >> 14) & 0x003)
|
||||
#define I2C_REVNB_HI_FUNC(x) (((x) >> 0) & 0xfff)
|
||||
#define OMAP2_I2C_SYSC 0x10
|
||||
#define I2C_SYSC_CLKACTIVITY_OCP 0x0010
|
||||
#define I2C_SYSC_CLKACTIVITY_SYSTEM 0x0020
|
||||
#define I2C_SYSC_IDLE_MASK 0x0018
|
||||
#define I2C_SYSC_IDLE_FORCE 0x0000
|
||||
#define I2C_SYSC_IDLE_SMART 0x0010
|
||||
#define I2C_SYSC_IDLE_NONE 0x0008
|
||||
#define I2C_SYSC_ENAWAKEUP 0x0004
|
||||
#define I2C_SYSC_SRST 0x0002
|
||||
#define I2C_SYSC_AUTOIDLE 0x0001
|
||||
#define OMAP2_I2C_IRQSTATUS_RAW 0x24
|
||||
#define OMAP2_I2C_IRQSTATUS 0x28
|
||||
#define OMAP2_I2C_IRQENABLE_SET 0x2C
|
||||
#define OMAP2_I2C_IRQENABLE_CLR 0x30
|
||||
#define OMAP2_I2C_WE 0x34
|
||||
#define I2C_IRQSTATUS_XDR 0x4000
|
||||
#define I2C_IRQSTATUS_RDR 0x2000
|
||||
#define I2C_IRQSTATUS_BB 0x1000
|
||||
#define I2C_IRQSTATUS_ROVR 0x0800
|
||||
#define I2C_IRQSTATUS_XUDF 0x0400
|
||||
#define I2C_IRQSTATUS_AAS 0x0200
|
||||
#define I2C_IRQSTATUS_BF 0x0100
|
||||
#define I2C_IRQSTATUS_AERR 0x0080
|
||||
#define I2C_IRQSTATUS_STC 0x0040
|
||||
#define I2C_IRQSTATUS_GC 0x0020
|
||||
#define I2C_IRQSTATUS_XRDY 0x0010
|
||||
#define I2C_IRQSTATUS_RRDY 0x0008
|
||||
#define I2C_IRQSTATUS_ARDY 0x0004
|
||||
#define I2C_IRQSTATUS_NACK 0x0002
|
||||
#define I2C_IRQSTATUS_AL 0x0001
|
||||
#define OMAP2_I2C_DMARXENABLE_SET 0x38
|
||||
#define OMAP2_I2C_DMATXENABLE_SET 0x3C
|
||||
#define OMAP2_I2C_DMARXENABLE_CLR 0x40
|
||||
#define I2C_DMARXENABLE 0x0001
|
||||
#define OMAP2_I2C_DMATXENABLE_CLR 0x44
|
||||
#define I2C_DMATXENABLE 0x0001
|
||||
#define OMAP2_I2C_DMARXWAKE_EN 0x48
|
||||
/* use same bits as IRQ */
|
||||
#define OMAP2_I2C_DMATXWAKE_EN 0x4C
|
||||
/* use same bits as IRQ */
|
||||
#define OMAP2_I2C_SYSS 0x90
|
||||
#define I2C_SYSS_RDONE 0x0001
|
||||
#define OMAP2_I2C_BUF 0x94
|
||||
#define I2C_BUF_RDMA_EN 0x8000
|
||||
#define I2C_BUF_RXFIFO_CLR 0x4000
|
||||
#define I2C_BUF_RXTRSH_MASK 0x3f00
|
||||
#define I2C_BUF_RXTRSH(x) ((x) << 8)
|
||||
#define I2C_BUF_XDMA_EN 0x0080
|
||||
#define I2C_BUF_TXFIFO_CLR 0x0040
|
||||
#define I2C_BUF_TXTRSH_MASK 0x003f
|
||||
#define I2C_BUF_TXTRSH(x) ((x) << 0)
|
||||
#define OMAP2_I2C_CNT 0x98
|
||||
#define I2C_CNT_MASK 0xffff
|
||||
#define OMAP2_I2C_DATA 0x9C
|
||||
#define I2C_DATA_MASK 0x00ff
|
||||
#define OMAP2_I2C_CON 0xA4
|
||||
#define I2C_CON_EN 0x8000
|
||||
#define I2C_CON_STB 0x0800
|
||||
#define I2C_CON_MST 0x0400
|
||||
#define I2C_CON_TRX 0x0200
|
||||
#define I2C_CON_XSA 0x0100
|
||||
#define I2C_CON_XOA0 0x0080
|
||||
#define I2C_CON_XOA1 0x0040
|
||||
#define I2C_CON_XOA2 0x0020
|
||||
#define I2C_CON_XOA3 0x0010
|
||||
#define I2C_CON_STP 0x0002
|
||||
#define I2C_CON_STT 0x0001
|
||||
#define OMAP2_I2C_OA 0xA8
|
||||
#define I2C_OA_MASK 0x03ff
|
||||
#define OMAP2_I2C_SA 0xAC
|
||||
#define I2C_SA_MASK 0x03ff
|
||||
#define OMAP2_I2C_PSC 0xB0
|
||||
#define I2C_PSC_MASK 0x000f
|
||||
#define OMAP2_I2C_SCLL 0xB4
|
||||
#define I2C_SCLL_MASK 0x000f
|
||||
#define OMAP2_I2C_SCLH 0xB8
|
||||
#define I2C_SCLH_MASK 0x000f
|
||||
#define OMAP2_I2C_SYSTEST 0xBC
|
||||
#define OMAP2_I2C_BUFSTAT 0xC0
|
||||
#define I2C_BUFSTAT_FIFODEPTH(x) (((x) >> 14) & 0x03)
|
||||
#define I2C_BUFSTAT_RXSTAT(x) (((x) >> 8) & 0x3f)
|
||||
#define I2C_BUFSTAT_TXSTAT(x) (((x) >> 0) & 0x3f)
|
||||
#define OMAP2_I2C_OA1 0xC4
|
||||
#define OMAP2_I2C_OA2 0xC8
|
||||
#define OMAP2_I2C_OA3 0xCC
|
||||
/* same bits as I2C_OA */
|
||||
#define OMAP2_I2C_ACTOA 0xD0
|
||||
#define OMAP2_I2C_SBLOCK 0xD4
|
||||
#define I2C_ACTOA_OA3_ACT 0x0008
|
||||
#define I2C_ACTOA_OA2_ACT 0x0004
|
||||
#define I2C_ACTOA_OA1_ACT 0x0002
|
||||
#define I2C_ACTOA_OA0_ACT 0x0001
|
||||
|
||||
#if defined(TI_AM335X)
|
||||
#define OMAP2_I2C0_BASE 0x44E0B000
|
||||
#define OMAP2_I2C1_BASE 0x4802A000
|
||||
#define OMAP2_I2C2_BASE 0x4819C000
|
||||
#endif /* TI_AM335X */
|
||||
|
||||
#endif /* _OMAP2IICREG_H */
|
||||
Loading…
Reference in New Issue