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Trailing whitespace

This commit is contained in:
skrll 2017-06-22 08:44:21 +00:00
parent 4f6bbf24ed
commit 3a7df9df31
1 changed files with 4 additions and 4 deletions
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8
sys/arch/arm/include/arm32/frame.h
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@ -1,4 +1,4 @@
/* $NetBSD: frame.h,v 1.42 2015/04/17 17:28:33 matt Exp $ */ /* $NetBSD: frame.h,v 1.43 2017/06/22 08:44:21 skrll Exp $ */
/* /*
* Copyright (c) 1994-1997 Mark Brinicombe. * Copyright (c) 1994-1997 Mark Brinicombe.
@ -64,7 +64,7 @@ struct switchframe {
u_int sf_sp; u_int sf_sp;
u_int sf_pc; u_int sf_pc;
}; };
/* /*
* System stack frames. * System stack frames.
*/ */
@ -240,7 +240,7 @@ void validate_trapframe(trapframe_t *, int);
#define ENABLE_ALIGNMENT_FAULTS \ #define ENABLE_ALIGNMENT_FAULTS \
and r7, r0, #(PSR_MODE) /* Test for USR32 mode */ ;\ and r7, r0, #(PSR_MODE) /* Test for USR32 mode */ ;\
GET_CURCPU(r4) /* r4 = cpuinfo */ GET_CURCPU(r4) /* r4 = cpuinfo */
#define DO_AST_AND_RESTORE_ALIGNMENT_FAULTS \ #define DO_AST_AND_RESTORE_ALIGNMENT_FAULTS \
DO_PENDING_SOFTINTS ;\ DO_PENDING_SOFTINTS ;\
@ -423,7 +423,7 @@ LOCK_CAS_DEBUG_LOCALS
* This should only be used if the processor is not currently in SVC32 * This should only be used if the processor is not currently in SVC32
* mode. The processor mode is switched to SVC mode and the trap frame is * mode. The processor mode is switched to SVC mode and the trap frame is
* stored. The SVC lr field is used to store the previous value of * stored. The SVC lr field is used to store the previous value of
* lr in SVC mode. * lr in SVC mode.
* *
* NOTE: r13 and r14 are stored separately as a work around for the * NOTE: r13 and r14 are stored separately as a work around for the
* SA110 rev 2 STM^ bug * SA110 rev 2 STM^ bug