From 3a2ce178a40c4d2a4b1977edda20d84c4034b57c Mon Sep 17 00:00:00 2001
From: tsutsui <tsutsui@NetBSD.org>
Date: Wed, 12 Dec 2012 16:24:49 +0000
Subject: [PATCH] Sprinkle redundant comments about PAD_P1_SWITCH to avoid
 stupid confusion.

---
 sys/arch/sh3/sh3/cache_sh4.c | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/sys/arch/sh3/sh3/cache_sh4.c b/sys/arch/sh3/sh3/cache_sh4.c
index 4a96002cfd92..8d83c1964dd1 100644
--- a/sys/arch/sh3/sh3/cache_sh4.c
+++ b/sys/arch/sh3/sh3/cache_sh4.c
@@ -1,4 +1,4 @@
-/*	$NetBSD: cache_sh4.c,v 1.22 2012/12/12 15:43:44 tsutsui Exp $	*/
+/*	$NetBSD: cache_sh4.c,v 1.23 2012/12/12 16:24:49 tsutsui Exp $	*/
 
 /*-
  * Copyright (c) 2002 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cache_sh4.c,v 1.22 2012/12/12 15:43:44 tsutsui Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cache_sh4.c,v 1.23 2012/12/12 16:24:49 tsutsui Exp $");
 
 #include "opt_cache.h"
 
@@ -230,6 +230,7 @@ sh4_icache_sync_all(void)
 		cache_sh4_op_8lines_32(va, SH4_CCIA, CCIA_ENTRY_MASK, CCIA_V);
 		va += 32 * 8;
 	}
+	/* assume we are returning into a P1 caller */
 	PAD_P1_SWITCH;
 }
 
@@ -249,6 +250,7 @@ sh4_icache_sync_range(vaddr_t va, vsize_t sz)
 		_reg_write_4(ccia, va & CCIA_TAGADDR_MASK); /* V = 0 */
 		va += 32;
 	}
+	/* assume we are returning into a P1 caller */
 	PAD_P1_SWITCH;
 }
 
@@ -271,6 +273,7 @@ sh4_icache_sync_range_index(vaddr_t va, vsize_t sz)
 		cache_sh4_op_line_32(va, SH4_CCIA, CCIA_ENTRY_MASK, CCIA_V);
 		va += 32;
 	}
+	/* assume we are returning into a P1 caller */
 	PAD_P1_SWITCH;
 }
 
@@ -286,6 +289,7 @@ sh4_dcache_wbinv_all(void)
 		    (CCDA_U | CCDA_V));
 		va += 32 * 8;
 	}
+	/* assume we are returning into a P1 caller */
 	PAD_P1_SWITCH;
 }
 
@@ -319,6 +323,7 @@ sh4_dcache_wbinv_range_index(vaddr_t va, vsize_t sz)
 		    (CCDA_U | CCDA_V));
 		va += 32;
 	}
+	/* assume we are returning into a P1 caller */
 	PAD_P1_SWITCH;
 }
 
@@ -421,6 +426,7 @@ sh4_emode_icache_sync_all(void)
 		    CCIA_V, 13);
 		va += 32 * 8;
 	}
+	/* assume we are returning into a P1 caller */
 	PAD_P1_SWITCH;
 }
 
@@ -444,6 +450,7 @@ sh4_emode_icache_sync_range_index(vaddr_t va, vsize_t sz)
 		    CCIA_V, 13);
 		va += 32;
 	}
+	/* assume we are returning into a P1 caller */
 	PAD_P1_SWITCH;
 }