Kill CLOCK_VA, INTERREG_VA. Do spl0() and splx(x) inline too.
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gwr
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7cd046827a
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399b15ebf9
@ -1,4 +1,5 @@
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/*
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* Copyright (c) 1994 Gordon W. Ross
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* Copyright (c) 1993 Adam Glass
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* Copyright (c) 1988 University of Utah.
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* Copyright (c) 1982, 1986, 1990, 1993
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@ -38,11 +39,13 @@
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*
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* from: Utah Hdr: machparam.h 1.16 92/12/20
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* from: @(#)param.h 8.1 (Berkeley) 6/10/93
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* $Id: param.h,v 1.17 1994/09/16 02:41:16 jtc Exp $
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* $Id: param.h,v 1.18 1994/09/20 16:31:03 gwr Exp $
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*/
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#ifndef MACHINE
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/*
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* Machine dependent constants for HP9000 series 300.
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* Machine dependent constants for the Sun3 series.
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*/
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#define MACHINE "sun3"
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#define MACHINE_ARCH "m68k"
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@ -80,10 +83,6 @@
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#define SINCR 1 /* increment of stack/NBPG */
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#define UPAGES 3 /* pages of u-area */
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#define USPACE (UPAGES * NBPG)
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#define CLOCK_VA (0x0FFE0000+(UPAGES*NBPG*2))
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#define INTERREG_VA (0x0FFE0000+(UPAGES*NBPG*2)+NBPG)
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/*
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* Constants related to network buffer management.
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@ -151,21 +150,27 @@
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#define sun3_ptob(x) ((unsigned)(x) << PGSHIFT)
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/*
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* spl functions; all but spl0 are done in-line
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* Suns have a REAL interrupt register, so spl0() and splx(s)
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* have no need to check for any simulated interrupts, etc.
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* All are done in-line (if optimization turned on).
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*/
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#include <machine/psl.h>
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#ifdef __GNUC__
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#define _spl(s) \
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({ \
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register int _spl_r; \
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\
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__asm __volatile ("clrl %0; movew sr,%0; movew %1,sr" : \
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"&=d" (_spl_r) : "di" (s)); \
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_spl_r; \
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})
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#endif
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/* spl0 requires checking for software interrupts */
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/*
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* This is as close to a macro as one can get.
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* (See the GCC extensions info document.)
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*/
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extern __inline__ int _spl(int new)
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{
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register int old;
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__asm__ __volatile ("clrl %0; movw sr,%0; movw %1,sr" :
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"&=d" (old) : "di" (new));
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return (old);
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}
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#endif /* GNUC */
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#define spl0() _spl(PSL_S|PSL_IPL0)
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#define spl1() _spl(PSL_S|PSL_IPL1)
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#define spl2() _spl(PSL_S|PSL_IPL2)
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#define spl3() _spl(PSL_S|PSL_IPL3)
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@ -173,6 +178,7 @@
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#define spl5() _spl(PSL_S|PSL_IPL5)
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#define spl6() _spl(PSL_S|PSL_IPL6)
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#define spl7() _spl(PSL_S|PSL_IPL7)
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#define splx(x) _spl(x)
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#define splsoftclock() spl1()
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#define splnet() spl3()
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@ -186,9 +192,6 @@
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#define splhigh() spl7()
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#define splsched() spl7()
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/* watch out for side effects */
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#define splx(s) (s & PSL_IPL ? _spl(s) : spl0())
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#ifdef KERNEL
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#ifndef LOCORE
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#define DELAY(n) delay(n)
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@ -197,3 +200,5 @@
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#else
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#define DELAY(n) { register int N = (n); while (--N > 0); }
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#endif
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#endif /* MACHINE */
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@ -1,4 +1,5 @@
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/*
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* Copyright (c) 1994 Gordon W. Ross
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* Copyright (c) 1993 Adam Glass
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* Copyright (c) 1988 University of Utah.
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* Copyright (c) 1982, 1986, 1990, 1993
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@ -38,11 +39,13 @@
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*
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* from: Utah Hdr: machparam.h 1.16 92/12/20
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* from: @(#)param.h 8.1 (Berkeley) 6/10/93
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* $Id: param3.h,v 1.17 1994/09/16 02:41:16 jtc Exp $
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* $Id: param3.h,v 1.18 1994/09/20 16:31:03 gwr Exp $
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*/
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#ifndef MACHINE
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/*
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* Machine dependent constants for HP9000 series 300.
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* Machine dependent constants for the Sun3 series.
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*/
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#define MACHINE "sun3"
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#define MACHINE_ARCH "m68k"
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@ -80,10 +83,6 @@
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#define SINCR 1 /* increment of stack/NBPG */
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#define UPAGES 3 /* pages of u-area */
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#define USPACE (UPAGES * NBPG)
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#define CLOCK_VA (0x0FFE0000+(UPAGES*NBPG*2))
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#define INTERREG_VA (0x0FFE0000+(UPAGES*NBPG*2)+NBPG)
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/*
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* Constants related to network buffer management.
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@ -151,21 +150,27 @@
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#define sun3_ptob(x) ((unsigned)(x) << PGSHIFT)
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/*
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* spl functions; all but spl0 are done in-line
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* Suns have a REAL interrupt register, so spl0() and splx(s)
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* have no need to check for any simulated interrupts, etc.
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* All are done in-line (if optimization turned on).
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*/
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#include <machine/psl.h>
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#ifdef __GNUC__
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#define _spl(s) \
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({ \
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register int _spl_r; \
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\
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__asm __volatile ("clrl %0; movew sr,%0; movew %1,sr" : \
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"&=d" (_spl_r) : "di" (s)); \
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_spl_r; \
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})
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#endif
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/* spl0 requires checking for software interrupts */
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/*
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* This is as close to a macro as one can get.
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* (See the GCC extensions info document.)
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*/
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extern __inline__ int _spl(int new)
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{
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register int old;
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__asm__ __volatile ("clrl %0; movw sr,%0; movw %1,sr" :
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"&=d" (old) : "di" (new));
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return (old);
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}
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#endif /* GNUC */
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#define spl0() _spl(PSL_S|PSL_IPL0)
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#define spl1() _spl(PSL_S|PSL_IPL1)
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#define spl2() _spl(PSL_S|PSL_IPL2)
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#define spl3() _spl(PSL_S|PSL_IPL3)
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@ -173,6 +178,7 @@
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#define spl5() _spl(PSL_S|PSL_IPL5)
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#define spl6() _spl(PSL_S|PSL_IPL6)
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#define spl7() _spl(PSL_S|PSL_IPL7)
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#define splx(x) _spl(x)
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#define splsoftclock() spl1()
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#define splnet() spl3()
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@ -186,9 +192,6 @@
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#define splhigh() spl7()
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#define splsched() spl7()
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/* watch out for side effects */
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#define splx(s) (s & PSL_IPL ? _spl(s) : spl0())
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#ifdef KERNEL
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#ifndef LOCORE
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#define DELAY(n) delay(n)
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@ -197,3 +200,5 @@
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#else
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#define DELAY(n) { register int N = (n); while (--N > 0); }
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#endif
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#endif /* MACHINE */
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